PhD Students - SLS | TIMA - Université Grenoble Alpes

Nathan BAIN

Methods for the learning and adapting formal neural networks to the constraints of hardware accelerators for applications optimized in power and / or throughput.

Keywords: Low power, Deep learning, IA accelerator

Chandana DESHPANDE

Building an Efficient 128-bit General Purpose Processor

Keywords: Microarchitecture, RISC-V, Power (energy) efficiency

Valentin ISAAC--CHASSANDE

Design of a Memory System for Sparse Data Processing

Keywords: Scientific computing, Sparse data, Memory system

Kilian MC GOVERN

Hardware Accelerator for Data Choregraphy Efficiency

Keywords: Computer architecture, Hardware design, Hardware Acceleration

Davy MILLION

Open Source Heterogeneous Multi-Core Chiplet Architecture Exploration

Keywords: Heterogeneous Architecture, Multi-Core, Chiplet, Architecture Exploration, Open Source Hardware, RISC-V

Van Quan PHAM

Digital hardware implementation of large neural networks under resource and memoory bandwidth constraints using network folding

Keywords: Digital hardware implementation, large neural networks, network folding

Pierre RAVENEL

Improving the performance of in-order processors under hardware complexity constraints

Keywords: Processors, in-order, hardware complexity

Olivier ROMANE

Data compression for high-performance hardware acceleration circuits

Keywords: neural networks, data compression, hardware acceleration

Eduardo TOMASI RIBEIRO

Single address space for massively parallel computers

Keywords: Virtual, address, parallel, computers