• Fast and accurate simulation of multi/many-core SoCs
    Communication, multiprocessor, cache, network, simulation
  • Methods for the learning and adapting formal neural networks to the constraints of hardware accelerators for applications optimized in power and / or throughput.
    Low power, Deep learning, IA accelerator
  • Study of an architectural model for code generation taking into account the real time constraints of an embedded system in the electrical measure and protection domain
    Embedded, Real time, Code Generation
  • Abstracting FPGA Development Flow Towards Agile Development Flows and High-Level Programming Paradigms
    Hardware Generation, Hardware construction languages, Hardware development, Chisel
  • Learning in very low precision
    Computer Arithmetic, Deep Learning, Digital Circuits and Systems
  • Building an Efficient 128-bit General Purpose Processor
    Microarchitecture, RISC-V, Power (energy) efficiency
  • Single address space for massively parallel computers
    Virtual, address, parallel, computers,
  • Integration of a Manycore Accelerator in a High-Performance Processor
    HPC, MPPA, cache coherency