Print Share Share on Facebook Share on X Share on LinkedIn Share this page URL Nathan BAIN Methods for the learning and adapting formal neural networks to the constraints of hardware accelerators for applications optimized in power and / or throughput. Keywords: Low power, Deep learning, IA accelerator Read more Chandana DESHPANDE Building an Efficient 128-bit General Purpose Processor Keywords: Microarchitecture, RISC-V, Power (energy) efficiency Read more Valentin ISAAC--CHASSANDE Design of a Memory System for Sparse Data Processing Keywords: Scientific computing, Sparse data, Memory system Read more Davy MILLION Open Source Heterogeneous Multi-Core Chiplet Architecture Exploration Keywords: Heterogeneous Architecture, Multi-Core, Chiplet, Architecture Exploration, Open Source Hardware, RISC-V Read more Pierre RAVENEL Improving the performance of in-order processors under hardware complexity constraints Keywords: Processors, in-order, hardware complexity Read more Olivier ROMANE Data compression for high-performance hardware acceleration circuits Keywords: neural networks, data compression, hardware acceleration Read more Eduardo TOMASI RIBEIRO Single address space for massively parallel computers Keywords: Virtual, address, parallel, computers Read more Print Share Share on Facebook Share on X Share on LinkedIn Share this page URL
Nathan BAIN Methods for the learning and adapting formal neural networks to the constraints of hardware accelerators for applications optimized in power and / or throughput. Keywords: Low power, Deep learning, IA accelerator Read more
Chandana DESHPANDE Building an Efficient 128-bit General Purpose Processor Keywords: Microarchitecture, RISC-V, Power (energy) efficiency Read more
Valentin ISAAC--CHASSANDE Design of a Memory System for Sparse Data Processing Keywords: Scientific computing, Sparse data, Memory system Read more
Davy MILLION Open Source Heterogeneous Multi-Core Chiplet Architecture Exploration Keywords: Heterogeneous Architecture, Multi-Core, Chiplet, Architecture Exploration, Open Source Hardware, RISC-V Read more
Pierre RAVENEL Improving the performance of in-order processors under hardware complexity constraints Keywords: Processors, in-order, hardware complexity Read more
Olivier ROMANE Data compression for high-performance hardware acceleration circuits Keywords: neural networks, data compression, hardware acceleration Read more
Eduardo TOMASI RIBEIRO Single address space for massively parallel computers Keywords: Virtual, address, parallel, computers Read more