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PhD Students - SLS

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Marie BADAROUX

Fast and accurate simulation of multi/many-core SoCs

Keywords: Communication, multiprocessor, cache, network, simulation

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Nathan BAIN

Methods for the learning and adapting formal neural networks to the constraints of hardware accelerators for applications optimized in power and / or throughput.

Keywords: Low power, Deep learning, IA accelerator

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Chandana DESHPANDE

Building an Efficient 128-bit General Purpose Processor

Keywords: Microarchitecture, RISC-V, Power (energy) efficiency

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Timothée LE BERRE

Neural Nets with Hybrid Quantization: Theory, Design, and Hardware Acceleration

Keywords: Artificial Intelligence, FPGA, quantization

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Davy MILLION

Open Source Heterogeneous Multi-Core Chiplet Architecture Exploration

Keywords: Heterogeneous Architecture, Multi-Core, Chiplet, Architecture Exploration, Open Source Hardware, RISC-V

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Pierre RAVENEL

Improving the performance of in-order processors under hardware complexity constraints

Keywords: Processors, in-order, hardware complexity

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Submitted on September 21, 2021

Updated on March 11, 2024