Eduardo TOMASI RIBEIRO

Abstract: The generalization of a hierarchical organization of HPC machines into nodes of several dozen computing cores interconnected by a high-performance communication network has fragmented operating systems and greatly complicated the writing of applications. The proposalof a 128 bit processor architecture by the RISC-V community offers the possibility of reinterpreting the fundamental concepts in view ofthese fundamental changes in the structure of the machines. In particular, this proposal offers the opportunity to rethink memoryaddressing at the scale of the entire machine, and not locally at the level of each node.The purpose of this thesis will be to study the opportunities thus offered, to propose strategies for managing a 128-bit addressing space onthe scale of the machine, and to evaluate its technical feasibility, hardware and software and expected performance.