Kilian MC GOVERN

Abstract: In the realm of computing architecture and systems, the memory bottleneck emerges as a critical obstacle for performance, particularly in architectures featuring multi-core processors and specialized accelerators. This bottleneck poses significant challenges for implementing certain image processing computations, often resulting in suboptimal performance (far from peak performance) and excessive power consumption. This is primarily attributed to non-contiguous memory data, random strides, and intricate memory access patterns.
While innovations in processor architectures, such as 128-bit RISC-V instruction sets, scratch-pad architectures, and in-memory computing, show promise, they often struggle to efficiently handle complex data structures and image processing tasks. This underscores the need for innovative approaches, especially tailored accelerators for memory access optimization based on specific data processing requirements coming from complex image processing algorithms. Stencils patterns (Wikipedia: https://en.wikipedia.org/wiki/Iterative_Stencil_Loops) are typical complex data structures to be managed.
Application domains: Image filtering, video compression, Partial Differential Equations (PDE) for physic simulation, sparse computation, Computation on variable lengths data.