Design of cryogenic circuits in FD-SOI technology for Qubit read-out
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RMS
Keywords: CMOS integrated circuit design, cryogenic temperatures, quantum applications
Abstract: The design of cryogenic silicon circuits has become increasingly important in recent years, particularly for applications such as silicon quantum computers, which require 4 K interface electronics with ultra-low power consumption levels. The design of these circuits is complicated by the lack of standard design kits for simulating them at these temperatures. Alternative approaches to avoid costly design and manufacturing cycles for optimising these circuits are possible, in particular the use of techniques basedon look-up tables (LUTs) that exploit the characterisation of components at cryogenic temperatures and the use of simplified transistor models such as s-EKV or ACM.
Informations
Thesis director: Salvador MIR (TIMA - RMS)
Thesis co-supervisors:
Estelle LAUGA-LARROZE (TIMA - RMS)
Brian MARTINEZ (CEA LETI)
Thesis started on: 01/01/2026
Doctoral school: EEATS
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