LU Jiajin

Abstract: The main question of this exploratory thesis is:
How can a multi-core / many-core system based on in-order SMT processors be designed while meeting performance and area constraints? This is particularly relevant because it is possible either to build a system with fewer processors and a high SMT degree, in order to reduce pressure on the coherent memory system, or to build a system with more processors and a lower SMT degree, in order to reduce the area pressure imposed by the hardware contexts of each core, but at the cost of increased pressure on the cache coherence system.
This trade-off may be adjusted in either direction depending on hardware techniques aimed at reducing the cost of SMT, thereby enabling a high SMT degree without necessarily paying the cost of numerous hardware contexts, or aimed at reducing the cost of cache coherence.
The objective of this thesis will be to develop and evaluate simulation and exploration methods for such architectures, integrating both hardware and software dimensions. The execution of code on a large number of cores and/or threads, as well as the associated data sharing, should be possible without requiring substantial modifications to the programming model.