PhD Students - MADMAX | TIMA - Université Grenoble Alpes

DEPIN Emeric Erwan

Estimation of the Power Consumption of Multi-Chiplet Systems-on-Chip Incorporating Processors Using High-Level Simulation Models

Keywords: processors, energy estimation, simulation, chiplets

DUBOIS Jules

Combined Software and Hardware Approaches for Large Scale Sparse Matrix Acceleration

Keywords: Hpc, Sparse data, heterogenous architecture

ILIN Andrei

CHIPCO : CHIPlet-aware cache Coherency

Keywords: cache coherence, communication protocol, quality of service, chiplet

LU Jiajin

Efficient multi-core and multi-threaded system for scalable communication applications

Keywords: in-order processor architecture, simultaneous multithreading, memory hierarchy, cache coherence, multi-core / many-core processor

MC GOVERN Kilian

Hardware Accelerator for Data Choregraphy Efficiency

Keywords: Computer architecture, Hardware design, Hardware Acceleration

MEEBED Abdallah

Efficient hardware implementations of neural networks with intra-layer heteroge- neous quantization

Keywords: Number representation, Quantization, Neural networks, Hardware acceleration

MILLION Davy

Open Source Heterogeneous Multi-Core Chiplet Architecture Exploration

Keywords: Heterogeneous Architecture, Multi-Core, Chiplet, Architecture Exploration, Open Source Hardware, RISC-V

PHAM Van Quan

Digital hardware implementation of large neural networks under resource and memoory bandwidth constraints using network folding

Keywords: Digital hardware implementation, large neural networks, network folding

ROMANE Olivier

Data compression for high-performance hardware acceleration circuits

Keywords: neural networks, data compression, hardware acceleration

SARTORI Dorian

Distributed address translation mechanisms integrated into the network-on-chip for RISC-V processors

Keywords: RISC-V, IOMMU, MMU, NOC, TLB,

SÖDERSTRÖM Johan

Accelerating Hardware Coherence Using Programmer Input in Multi/Manycore Systems

Keywords: RISC-V, cache coherence, manycore

YERLY Louka

PhD in Computer Architecture (HW/SW interaction between operating system and microarchitecture)

Keywords: Computer Architecture, Microarchitecture, Operating System, HW/SW

ZHIRI Mohamed Amine

Self-adaptive and reliable interconnect network for AI accelerator architectures

Keywords: to be defined