ILIN Andrei

Abstract: Industry has adopted chiplets to continue scaling computing systems, particularly for applications like High-Performance Computing (HPC) and Artificial Intelligence (AI). Chiplets are smaller, cheaper, and more reusable than large monolithic chips. At the same time, modern chips are becoming more heterogeneous, composed of general-purpose (GP) processor cores and domain-specific cores (accelerators) to increase performance and energy efficiency. This heterogeneity presents design and research challenges, particularly in the communication infrastructure, which includes the Network-on-Chip (NoC) and memory hierarchy.
The memory hierarchy in modern systems contains multiple levels of cache memories, which keep copies of data close to the cores. Cache coherency, ensuring that multiple caches have a consistent view of memory, is a critical issue. Cache coherency protocols, which involve exchanging messages between caches, can significantly impact power consumption and performance. These protocols need to be re- evaluated for multi-chiplet systems.
Different questions need still to be addressed for such systems. To list a few: (1) how to organize cache memories to limit inter-chiplet traffic? (2) shall cache coherency protocols be redefined to be more heterogeneous and chiplet aware? (3) how to guarantee quality-of-service in multi-chiplet systems with multiple types of traffic?
The PhD objectives include building a simulation platform to model heterogeneous chiplet-based processors, evaluating the performance for specific applications, and proposing new techniques to increase the performance and energy efficiency of these systems, with a particular focus on the cache coherency protocol. The goal is to address the research questions above.
The PhD supervision team includes researchers from Grenoble-INP and Inria (Université Grenoble Alpes) on the one hand, Universitat Politécnica de Catalunya (UPC) and Barcelona Supercomputing Center (BSC) on the other hand. The PhD will be co-funded by UGA and BSC.