Designing asynchronous monitoring integrated circuits for safety and reliability
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CDSI
Keywords: design, integrated circuits, asynchonous, reliability,
Abstract: The study of asynchronous circuits incorporating protection and monitoring mechanisms in order to guarantee safe and/or secure operation. The structure of asynchronous circuits makes it possible to know the movement of data in the circuit. This remarkable property also makes it possible to monitor the operation of the circuit and detect potential problems in advance. Thus, it is possible to imagine a monitoring strategy for asynchronous circuits. This approach will be studied and analyzed in detail in order to define a method that could be used systematically for circuits requiring greater robustness or operational reliability, such as a RISC V processor operating at very low voltage.
Informations
Thesis directors:
- Laurent FESQUET (TIMA - CDSI)
- Sylvain ENGELS (TIMA - RMS)
Thesis started on: 01/10/2024
Doctoral school: EEATS
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