Adrien GODARD

Abstract: The objective of the thesis will be to study a RISC-V microprocessor-type circuit, in order to find the most appropriate asynchronous design strategies to target a very low power consumption and a very low voltage. The study will focus on analyzing the benefits of such a controller in an NFC subsystem application, in order to find an effective compromise between embedded software flexibility and hardware efficiency. The synchronization protocol will be thoroughly selected to reduce the circuit's power consumption and robustness under low voltage conditions. Finally, the circuit's behavior will be studied at low voltage to validate the design flow and the energy efficiency.
In order to efficiently demodulate RF and especially NFC signals, the thesis will target a low-power system based on a microcontroller unit containing a dedicated hardware accelerator. This solution will be designed using a high-level synthesis (HLS) approach to evaluate several processor configurations. In addition, processor inputs will benefit from parsimonious sampling and asynchronous implementation. This approach considerably reduces the number of samples processed and, consequently, the system's power consumption.