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Robust and Secure RISC-V Architecture



Keywords: Hardware security, RISC-V, dependability

Abstract: Modern microprocessors aim at providing the best possible performance (at a reasonable cost). For this reason, several architectural optimizations are often designed, engineered, and implemented, but such complexity is usually transparent to users and developers, who cannot see the hidden elements. Indeed, microarchitecture designers have progressively added many complex hardware blocks (for example, pipeline, cache memory, branch prediction, speculative execution, specialized blocks) in order to optimize program executions.
The increasing complexity of the microprocessor architectures and the applications they run, however, means that foreseeing the behavior of the system under nonnominal conditions is a hard and critical challenge. The behavior of the CPU (and of the full system) when external interferences affect the system may be largely affected by these hidden elements. Thus, it is highly important that the design flow should take into consideration from the very beginning the possibility of perturbations on the external clock, the power supply, or the electromagnetic surrounding that might alter the safe and secure execution of code.
The candidate is expected to develop a RISC-V architecture intrinsically robust and secure against perturbation, error occurrences, and fault injections. A first step will focus on modeling the effects of complex fault occurrences and perturbations on the micro-architecture. The objective is to have a thorough understanding of the error mechanisms occurring within the RISC-V architecture, at different levels. Subsequently, the candidate will propose and evaluate architectural solutions in order to mitigate the identified vulnerabilities.


Thesis directors: Giorgio DI NATALE / Paolo MAISTRI (TIMA - AMfoRS)
Thesis started on: Oct. 2022
Doctoral school: EEATS

Submitted on October 26, 2022

Updated on April 8, 2024