DEPIN Emeric Erwan

Abstract: Current estimation methods, such as netlist-level simulations (a logic-gate-level representation of a circuit), are too slow for real-world applications and incompatible with the modularity of chiplets (limited access to complete netlists). It is therefore essential to develop high-level abstraction models that: (1) Preserve supplier confidentiality, (2) Speed up simulations compared to RTL/netlist approaches, (3) Incorporate power and thermal estimation mechanisms for heterogeneous architectures.
The objectives of this PhD are:
(1) extend the GEM5 simulator (the academic and industry standard for SoCs) to model the specific characteristics of multi-chiplet systems, including the integration of configurable power and thermal models, as well as standardized interfaces to facilitate interoperability between chiplets from different vendors

(2) determine the optimal level of detail for models to balance accuracy and simulation speed, (3) propose synchronization mechanisms to combine data from heterogeneous models.