SARTORI Dorian

Abstract: The main objective of this thesis is to study, evaluate, and propose different organizations of address translation mechanisms for efficient integration into the Network-on-Chip (NoC) of processors. Efficiency in this context will be defined in terms of performance per Watt (GOPS/W), performance per silicon area (GOPS/mm²), and peak performance (GOPS). Address translation mechanisms include MMUs (Memory Management Units) or IOMMUs (Input/Output Memory Management Units) and their associated TLBs (Translation Lookaside Buffers) to accelerate the translation of virtual addresses into physical addresses.
The NoC is a fundamental component of modern SoCs as it provides the communication medium between processor cores, memory, and peripherals. However, depending on the application domain for which the SoC is designed, bandwidth and latency requirements can vary greatly. Since Arteris is one of the world leaders in NoC design for various application domains, it is necessary that the organization of address translation mechanisms be highly configurable to adapt to the needs of the target SoC.
Therefore, the main question this thesis seeks to answer is: can we propose a methodology to match the organization of the NoC integrating TLBs (for MMUs and IOMMUs) with the target application domain? Indeed, virtual-to-physical address translation represents one of the performance bottlenecks for modern SoCs. The growing demand for data and instructions in applications increases pressure on TLBs, requiring larger sizes to reduce miss rates and thus lower average memory access latency. However, TLBs can represent significant silicon area and energy consumption costs since they are on-chip memory components. Therefore, it will be necessary to extract the essential characteristics of SoC components and applications to design the distribution of TLBs integrated into the NoC. More generally, could such a methodology be implemented in automatic NoC generation tools? This would facilitate the automatic generation of NoCs for different types of connected components.
Initially, this thesis focuses on SoCs implementing RISC-V cores. However, an interesting research question is: could we design mechanisms to support different instruction sets (and their specificities regarding virtual addressing) while reusing the same infrastructure as much as possible? This offers the possibility of reducing NoC development costs and opens the door to introducing heterogeneity in terms of instruction sets within the same SoC. The case study would involve systems containing ARM and/or RISC-V cores. Therefore, more specifically, this thesis will address the design of an IOMMU (or MMU) usable within an SoC based on ARM and/or RISC-V processors.