Enhancing the Security of RISC-V Microarchitectures Against Laser Fault Injection: Fault Modeling and Countermeasure Development at the RTL Level
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AMfoRS
Keywords: Cybersecurity, RISCV processor, Hardware design
Abstract: This PhD is part of the TWINSEC project, which aims to enhance the security of RISC-V microarchitectures against laser fault injection attacks. These physical attacks allow adversaries to disturb the processor's behavior, potentially bypassing security features or extracting confidential data. Current fault models are overly generic and fail to capture the complex interactions between hardware, microarchitecture, and software. The goals of this PhD are to: Develop realistic RTL-level fault models for laser-induced faults; Assess the vulnerability of well-known RISC-V microarchitectures (e.g., OpenTitan, CV32, CVA6); Improve or design new hardware/software countermeasures, ensuring low overhead and suitability for embedded systems. The research will be jointly supervised by LCIS (Valence) and TIMA (Grenoble), two leading French labs in hardware fault simulation and secure circuit design.
Informations
Thesis directors:
Vincent BEROULLE (LCIS)
Paolo MAISTRI (TIMA - AMfoRS)
David HELY (LCIS)
Thesis started on: 01/11/2025
Doctoral school: EEATS
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