AIT BELKACEM Sabrina

Abstract: In the context of the growth of embedded systems, Internet of Things (IoT) devices, and hardware security applications (notably in cryptography, authentication, or blockchain), SRAM memory remains a key component. Widely used for its fast access, low power consumption, and CMOS compatibility, it often represents a critical storage point for sensitive data such as cryptographic keys, temporary states, sensor data, or device identifiers.
However, these memories are exposed to subtle physical vulnerabilities, particularly those related to aging mechanisms and secondary effects inherent to advanced CMOS technologies. One of the most critical mechanisms in this regard is NBTI (Negative Bias Temperature Instability), a progressive degradation phenomenon affecting PMOS transistors under prolonged bias stress. By altering the electrical characteristics of transistors, NBTI can leave exploitable residual traces (so-called burn-in effect), indirectly revealing past memory states — which constitutes a major security risk.
In systems with strict security requirements (e.g., secure erasure of volatile keys after use, or prevention of delayed post-mortem analysis), it becomes essential to control not only the logical content of SRAM but also the residual physical traces that its operation leaves in the silicon. These traces can be exploited in semi-invasive or deferred attacks, notably through electrical, thermal, or differential aging observation techniques.
PhD Objective:
The proposed research aims to design dedicated circuits for the physical security of SRAM memory, with a particular focus on resistance to the exploitation of NBTI effects. The objective is to prevent an attacker from inferring sensitive information from previously stored states, even after logical erasure.
To this end, the PhD candidate will build upon prior laboratory work, notably on techniques for fast erasure and initialization of SRAM. The next steps will involve proposing, modeling, and validating circuits and memory access strategies that ensure effective reset operations — not only logical but also physical — while minimizing stress asymmetries responsible for differential aging.
PhD Work Plan:
- Comprehensive state of the art:
On physical attacks exploiting SRAM aging (NBTI, PBTI, HCI, etc.),
On existing countermeasures, both software and hardware,
On secure memory architectures and zero-trace design approaches.
- Physical characterization:
Experimental study of existing SRAM cells (through electrical or post-silicon measurements),
Highlighting differentiated aging effects depending on data patterns,
Development of a dedicated test bench, if required.
- Design of secure SRAM circuits:
Definition of NBTI-aware architectures (reinforced erasure, symmetric write schemes, active scrambling, etc.),
Simulation in SPICE / Cadence / Synopsys environments for functional and electrical validation,
Integration of dedicated logic for secure startup, trace-free shutdown, and cryptographic access modes.
- Silicon measurement and validation:
Fabrication or use of test chips,
Evaluation of robustness against delayed attacks, data remanence, and differential post-exploitation readout,
Scientific valorization (publications, potential patents) and perspectives for integration into secure embedded systems.