Karim AIT LAHSSAINE

Abstract: Since 2018 and the announcement of the Spectre[1] and Meltdown[2] vulnerabilities, the hard- won performance gains of desktop and server processors over the past decades have been called into question. These vulnerabilities effectively exploit the speculative and out of order execution found in all modern processors to gain in the number of instructions performed per clock cycle. These types of execution open the door to transient microarchitectural changes that can be disclosed due to shared resources within the pipeline and caches and the presence of covert channels that allow the extraction of leaked data. The latter can be caches but also other internal buffers.
The objectives of the PhD will be to understand these mechanisms through the implementation of attacks and leakage evaluation systems via for example the mutual information calculation.
Then, for each leak and each microarchitecture (branch prediction, prefetcher, TLB, Load Store unit, execution stage, caches,...), we will have to find the approach that penalizes the least performance. An implementation of these countermeasures is planned on the open source NaxRiscV[3] 64 bits processor and Out of Order written in the SpinalHDL language which allows to host and test them with a great modularity.
The resolution of these problems can both take advantage of the work done in the laboratory on authenticated memory encryption and the partitioning in the pipeline of data and instructions according to the processes executed. Logical elements will also have to be added to ensure the boundary between the different processes inside the CPU. Finally, random addressing and/or highly selective eviction techniques will be used for microarchitectural components where partitioning would be too costly, especially in caches. Finally, the implemented countermeasures will have to be characterized with respect to the developed evaluation tools.