Clément TARDY

Abstract: The thesis focuses on the problem of fault attacks, which aim to disturb the operating environment of a circuit to introduce a logical fault and corrupt execution. To detect fault injections, various protections are deployed in security architectures, ranging from physical environment change detectors to redundancy-based mechanisms. However, these protections have limitations in terms of cost, performance, and adaptability.
The thesis aims to propose complementary mechanisms to spatial redundancy-based protections to enhance circuit security with moderate hardware cost and minimal or zero memory cost. Performance degradation may be tolerated and ideally can be modulated depending on the context. The adaptation of these mechanisms based on a security policy and a deviation monitoring mechanism from normal behaviors will also be investigated.
Finally, to evaluate the robustness of existing and proposed mechanisms and their adaptability over time, the thesis aims to study evaluation methods and tools, both by simulation and formal methods, to develop a method that considers state-of-the-art attackers and provides a reasonable robustness score for a given platform. The thesis will explore solutions with minimal surface and memory impact, potentially high-performance overhead, and adaptability (execution variability is a plus), to be activated when there is suspicion of an attack or against an expert attacker. The thesis will also investigate techniques for attack detection and triggering of execution-time adaptation of activated mechanisms.