Damiano ZUCCALA

During this thesis we will focus on methods for automatic generation of dysfunctional models from a functional description in a "Hardware Description Language" (HDL) such as VHDL or Verilog. We will develop automatic methods for generating Altarica functional safety models from a Hardware Description Language (HDL) targeting digital blocks composing a System-On-a-Chip (SoC) by using formal methods of large state space analysis and code analysis.