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Generation Automatique de Modeles de Sureté pour l'Analyse de Systemes Numeriques Complexes

Relibility, Safety Models, Hardware digital design

During this thesis we will focus on methods for automatic generation of dysfunctional models from a functional description in a "Hardware Description Language" (HDL) such as VHDL or Verilog. We will develop automatic methods for generating Altarica functional safety models from a Hardware Description Language (HDL) targeting digital blocks composing a System-On-a-Chip (SoC) by using formal methods of large state space analysis and code analysis.


Thesis director: Katell MORIN-ALLORY
Thesis supervisor: Jean-Marc DAVEAU (ST Microelectronics)
Thesis started on: March 2022
Doctoral school: EEATS

Submitted on April 29, 2022

Updated on April 29, 2022