Back To The Future (BTF)

As instruction windows have kept growing in the recent year, modern processors may hold hundreds of instructions waiting to be execute in their internal structures. As a result, when it turns out that the speculated control flow path containing those instructions is the incorrect one, hundreds of instructions, some of which have already executed (e.g., read memory) have to be thrown away. As a result, control flow misspeculation remains a major cause of wasted work (hence energy) in modern high performance pipelines.

Within the Intel Corporation Collaborative Research Center for Transformative Server Architecture (TSA), the Back to the Future project aims at improving control flow speculation accuracy by leveraging microarchitectural information. More specifically, we plan to explore the idea of using *future* information tied to younger instructions to predict *past* (older) long latency branches prone to mispredictions that are waiting to be resolved in the pipeline. Those future instructions are on the incorrect control path, therefore, we plan on identifying events of interest on the wrong path and correlate them to incorrectly predicted control path, to determine when the processor gets resteered. This will help improve performance and reduce wasted work.

Partners:

• Intel Corporation
• University of Cyprus