Print Share Share on Facebook Share on X Share on LinkedIn Share this page URL BADAROUX Marie Fast and accurate simulation of multi/many-core SoCs BAIN Nathan Methods for the learning and adapting formal neural networks to the constraints of hardware accelerators for applications optimized in power and / or throughput. BONICEL Louis Study of an architectural model for code generation taking into account the real time constraints of an embedded system in the electrical measure and protection domain BRUANT Jean Abstracting FPGA Development Flow Towards Agile Development Flows and High-Level Programming Paradigms CATHELINEAU Benjamin Test and reliability analysis for cyber-physical system models CHRIST Maxime Learning in very low precision DESHPANDE Chandana Building an Efficient 128-bit General Purpose Processor LE BERRE Timothée Neural Nets with Hybrid Quantization: Theory, Design, and Hardware Acceleration VIANES Arthur Integration of a Manycore Accelerator in a High-Performance Processor Print Share Share on Facebook Share on X Share on LinkedIn Share this page URL
BAIN Nathan Methods for the learning and adapting formal neural networks to the constraints of hardware accelerators for applications optimized in power and / or throughput.
BONICEL Louis Study of an architectural model for code generation taking into account the real time constraints of an embedded system in the electrical measure and protection domain
BRUANT Jean Abstracting FPGA Development Flow Towards Agile Development Flows and High-Level Programming Paradigms
