Thesis defence of Jean BRUANT (SLS team): Abstracting Hardware Architectures for Agile Design of High-performance Applications on FPGA

Jean BRUANT - SLS team

Composition of the jury
Olivier MULLER (thesis director) - Associate professor - Grenoble Institute of Technology (Grenoble INP)
Frédéric PETROT (co-thesis director) - Professor - Grenoble Institute of Technology (Grenoble INP)
Steven DERRIEN (rapporteur) - Professor - Université Rennes 1
Matthieu ARZEL (rapporteur) - Professor - IMT Atlantique
Florence MARANINCHI (examinator) - Professor - Grenoble Institute of Technology (Grenoble INP)
Roselyne CHOTIN-AVOT (examinator) - Associate professor HDR - Sorbonne Université
Megan WACHS (examinator) - Engineer - SiFive company

Abstracting Hardware Architectures for Agile Design of High-performance Applications on FPGA
In a context of ever-growing worldwide communication traffic and fast deployment of IoT devices, network attacks have become a daily challenge with record-breaking throughput levels.
Compared to software solutions based on general purpose CPUs, FPGA-based mitigation appliances appear as an energy-efficient alternative which combines configurability with guaranteed high-throughput and low-latency.
However, implementation of such dedicated hardware accelerators based on the register-transfer level (RTL) abstraction is a much slower and tedious process than functionally equivalent software developments.
The latter have indeed benefited from the introduction of countless high-level paradigms over the past decades, whereas traditional hardware description languages (HDLs) have consistently remained rigid and verbose.
As a result, the agility gap between hardware and software developments is expanding at a steady pace, leaving hardware design experts frustrated by the lack of re-usability of their carefully crafted architectures.
This thesis tackles this generic hardware development issue within the context of high-performance networking appliance design at OVHcloud.
Mimicking the successful trajectory of software evolution, it aims at leveraging a stack of abstraction levels to instill flexibility within hardware descriptions.
As a key enabler, Hardware Construction Languages (HCLs) apply some existing software abstractions to hardware design, which permits descriptions of circuit generators with high-level software paradigms, such as object-oriented and functional programming.
This thesis first exhibits the relevance of such software inherited paradigms to develop highly re-usable network functions, inspecting both implementation and design perspectives. Based on this strong base layer, we introduce an additional hardware-oriented abstraction focusing on high-performance pipelined applications.
Finally, the integration ability of these novel design methodologies within existing HDL hierarchies is reviewed in details, yielding two final contributions aiming at ensuring a smooth cohabitation of both methodologies.
The first one provides a direct path from existing HDL sources to their functionally equivalent HCL counterparts, thanks to an automated translation tool.
This word-for-word translation is intended as the first step of an iterative manual upgrade to truly benefit from high-level abstractions of HCLs.
The second one focuses on the smooth integration of HCL-generated hierarchies back into a top-level HDL hierarchy, which is a key acceptance factor for these new methodologies in long-running projects.