Development Service manager
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Research Engineer, PhD (CNRS)
In charge of the Development Service of the lab
Research and Development, hardware and software
C / C++ development
High-level synthesis (HLS)
Digital circuit design (VHDL, netlist)
Static Timing Analysis (STA)
FPGA hardware acceleration
CAM / TCAM memories
Data mining, frequent itemset mining, string mining
Quantized neural networks, acceleration of AI inference
PCI-Express with RIFFA framework
Xilinx Zynq SoCs, AXI channels
Contacts
Office: T105
adrien.prost-boucle
univ-grenoble-alpes.fr (adrien[dot]prost-boucle[at]univ-grenoble-alpes[dot]fr)
Tel: +33 4 76 57 47 21
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