Development engineer
- Share
- Share on Facebook
- Share on X
- Share on LinkedIn
ASICs: Technical support on design-kits & CAD tools (Cadence Virtuoso, Siemens/Mentor Calibre, etc...).
ASICs & FPGAs: digital design (VHDL/Verilog synthesis, Place & Route, simulations, final DRC/LVS).
Can also help on: tests & verification (DFT, JTAG, BIST, etc...) ; layout designs ; acceleration of AI inference.
Contacts
Office: T105
christelle.rabacheuniv-grenoble-alpes.fr (christelle[dot]rabache[at]univ-grenoble-alpes[dot]fr)
Tel: +33 4 76 57 48 72
- Share
- Share on Facebook
- Share on X
- Share on LinkedIn