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Christelle RABACHE

Development engineer

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ASICs: Technical support on design-kits & CAD tools (Cadence Virtuoso, Siemens/Mentor Calibre, etc...).
ASICs & FPGAs: digital design (VHDL/Verilog synthesis, Place & Route, simulations, final DRC/LVS).
Can also help on: tests & verification (DFT, JTAG, BIST, etc...) ; layout designs ; acceleration of AI inference.

Contacts

Office: T105
christelle.rabacheatuniv-grenoble-alpes.fr (christelle[dot]rabache[at]univ-grenoble-alpes[dot]fr)
Tel: +33 4 76 57 48 72

Submitted on June 30, 2023

Updated on April 17, 2024