Towards robust, low power and adjustable accuracy Bayesian computers
Stochastic computing, Sensor fusion, RNG,Bayesian inference, AI,Low power
By reducing multiplication to a single AND logic gate, stochastic arithmetic significantly reduces the size of operators (and therefore manufacturing costs) and their consumption at the expense of a lower computing speed, making it particularly suitable for Bayesian inference calculations. Initial results show the energy efficiency of this stochastic approach when the size of the problem to be treated is reduced and the accuracy required is low.
These results nevertheless raise two main bottlenecks when the size of the problem increases: the memory space needed to store probability distributions and the energy cost to generate random numbers.
This thesis aims to design Bayesian machine architectures that are efficient in low and high accuracy with a low energy consumption. To do so, it is necessary, on the one hand, to bypass the limits defined previously by rethinking the methods of storing distributions and generating random numbers necessary for stochastic calculation. And on the other hand, to exploit the specificities of these architectures, such as robustness allowing the increase of PVT margins and therefore the reduction of the circuit supply voltage, or the event-based nature of the Bayesian approach making an asynchronous implementation relevant.
Thesis director: Laurent FESQUET
Thesis supervisor: Karim CHERKAOUI (Hawai.Tech)
Thesis started on: Sept. 2019
Thesis defence: 12/10/2022
Doctoral school: EEATS