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Strategies for securing a memory hierarchy against software side-channel attacks

RISC-V, Hardware security, DRAM, memory hierarchy, software side-channel attack

The objective of this thesis is to develop new ways of securing a memory hierarchy. A first primary focus of work will be to understand all current attacks on the memory hierarchy and possibly identify potential new vulnerabilities. This analysis will then make it possible to derive a set of quantitative criteria for the security of the hierarchy. We will, therefore, have the appropriate tools to compare the architecture proposed to secure the memory hierarchy in the state-of-the-art and identify their limits. From this, we can build countermeasures that are thought out globally, and that target the entire memory hierarchy. The innovations proposed in this thesis are intended to be integrated into the secure RISC-V processor developed in the Nanoelect Nanotrust IRT project.


Thesis director: Giorgio DI NATALE
Thesis supervisor: Thomas HISCOCK (CEA)
Thesis started on: Nov. 2019
Thesis defence: Dec. 12th, 2022
Doctoral school: EEATS

Submitted on January 12, 2022

Updated on September 6, 2023