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Clock Generation For Low Power Receiver based on N-Path Mixers


Keywords: Horloge, N-path mélangeurs, Consommation

Abstract: Because of the increasing number of connected devices, mobile communications, and wireless applications for remote operations, health purpose, domotics, or high data rates, more and more frequencies are allocated in the RF spectrum (let's say 300 MHz to 5 GHz). As a consequence, there is a need for multistandards receiver. One solution would be to use multiple parallel receivers, each one dedicated to one specific application / frequency / protocol. This solution takes a lot place on a board and also it consumes much power. This leads, finally, to high costs either to fabricate or to use. The other solution, that is the one we propose to study in this PhD work, enables to manage a large frequency band, sometimes as large as a decade, by using only one receiver, which reduces power consumption thanks to lower complexity (i.e. a lower number of basic blocks). This domain in RFIC finds huge interest in software defined radios domain, that can cover that way a large amount of radio frequencies, with one data processor only. The price to pay is the large frequency band to be available for each basic block: low noise amplifiers (LNA), mixers, voltage controlled oscillators (VCO). For that purpose, harmonic rejection based N-path mixers, HR-NPM, are very good candidates, requiring the availability of wideband LNAs (typically 300 MHz-2.4 GHz) and also wideband VCOs (typically based on ring oscillators, that are made tunable thanks to current starving). There is much room for research in this area by inventing innovative architectures for N-Path mixers enabling to reduce the number of necessary LNAs, to reduce the time constraints on the clocks generators, enabling to relax the constraints on phase and amplitude RF or clocks mismatches. Usually, HR-NPMs, are based on architectures for which the number of paths, N, is a 2 power N integer. Other integer number of paths, even odd numbers, will be studied, in association with original clocks generations, in order to implement low complexity, low power consumption, resilient to mismatches, wideband receivers. The designs will be implemented in a FD-SOI 28nm technology, in the framework of OCEAN12 European ECSEL contract.


Thesis director: Florence PODEVIN (TIMA - RMS)
Thesis started on: Aug. 2020
Doctoral school: EEATS

Submitted on January 12, 2022

Updated on December 12, 2023