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IPs for mixed-signal/high-speed integrated circuits dependability and control


Keywords: Test, Jitter, Mixed-signal circuits

Abstract: This thesis is aimed at developing advanced IPs (Intellectual Property) for enhancing the testability, safety, reliability or performance of mixed-signal and high-speed IC blocks, such as Analog-to-Digital converters (ADCs), PLLs, high-speed digital interfaces, etc. These IPs will make possible built-in test features that can be exploited in the different life phases of a product, from IP and technology characterization to production testing and in-field monitoring. The IPs can also provide the means of guaranteeing signal integrity and the safe functionality of mixed-signal SoCs, especially in the context of low-power consumption, exploiting the built-in test structures for power monitoring and control.


Thesis director: Salvador MIR (TIMA - RMS)
Thesis supervisors:
- Jai Narayan TRIPATHI (Indian Institute of Technology Jodhpur)
Thesis started on: Jan. 2020
Thesis defence: March 21, 2024
Doctoral school: EEATS

Submitted on January 12, 2022

Updated on April 8, 2024