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Fast and accurate simulation of multi/many-core SoCs

Communication, multiprocessor, cache, network, simulation

The de facto way of programming multi/manycore chips assumes that the memory is logically shared, and the hardware support for that is cache coherence throughout the memory hierarchy. The question of enabling the scaling of the protocol needed to ensure coherence is recurrent, because it requires to broadcast coherence messages to all the caches, or to multicast these messages to an identified subset of the caches. Similarly, collective synchronizations like barriers or condition signaling hardly scale.
Current fast functional simulators do not take non-functional models, such as caches, TLB, and so on, into account. Several attempts have been made to introduce such information in the models, at the price of high slowdowns. At the other end of the spectrum, very fast trace-based simulation has been developed. In that case traces gathered during executions are filtered following certain criteria and replayed on an abstract view of the system. However, the behavior of the system cannot be influenced by timings.
The goal of this research is to investigate the needed simulation strategies to simulate, at system level but with an acceptable accuracy, a multiprocessor and its wireless communication infrastructure to support the design and implementation of software-centric systems based around wireless NoCs. The “radio” part is out of the scope of this position proposal, but the capabilities it offers and the constraints it imposes are to be taken into account to evaluate solutions for large scale cache coherency and some collective operations like synchronization barriers or condition signaling.


Thesis director: Frédéric PETROT
Thesis started on: Oct. 2020
Doctoral school: MSTII

Submitted on January 12, 2022

Updated on March 17, 2022