Abstracting FPGA Development Flow Towards Agile Development Flows and High-Level Programming Paradigms
Hardware Generation, Hardware construction languages, Hardware development, Chisel
This thesis aims at exploring innovative high-level hardware development tools, in order to design and implement a flexible, resilient and open-source hardware development flow. It differs from the standard HLS (High-Level Synthesis) which aims at converting a software-defined feature in its hardware description directly. Here the goal is to incrementally increase the level of abstraction, building on elementary hardware description as they are currently expressed with languages such as Verilog or VHDL. The development flow shall allow raw hardware development and also provide advanced code generation features, such as the automated generation of pipelines, interfaces or even software API.
Mis à jour le 15 September 2022