IPs for mixed-signal/high-speed integrated circuits dependability and control
Test, Jitter, Mixed-signal circuits
This thesis is aimed at developing advanced IPs (Intellectual Property) for enhancing the testability, safety, reliability or performance of mixed-signal and high-speed IC blocks, such as Analog-to-Digital converters (ADCs), PLLs, high-speed digital interfaces, etc. These IPs will make possible built-in test features that can be exploited in the different life phases of a product, from IP and technology characterization to production testing and in-field monitoring. The IPs can also provide the means of guaranteeing signal integrity and the safe functionality of mixed-signal SoCs, especially in the context of low-power consumption, exploiting the built-in test structures for power monitoring and control.
Mis à jour le 17 March 2022