Study of ESD/CDM stresses phenomena from elementary charged devices to package discharge
Integrated circuits, ESD, CDM
Before we put a new device /product into mass production, we should test it to know how sensitive it is to Electro Static Discharge (ESD) and particularly regarding Charging Device Model (CDM) stresses. It is necessary to guarantee an ESD CDM robustness of a product to achieve a good production / customer handling yield.
The official ST CDM target is about 500V/11A for a long time but this specification is becoming harder and harder to achieve due to technology and process constraints because of:
- Wafer-level packaging
- Technology shrink
- Increasing Product size
- RF/CDM trade-off on RF pins…
In this context, the aims of this thesis are:
- State of the art regarding CDM scientific community knowledge
- Charges migration during CDM phenomenon understanding in a whole chip
- Understanding on devices failure mechanisms in BULK and FDSOI technology during CDM events.
- Studying the design of a CDM reference testchip to qualify our solution
- Elaborating /validating a set of CDM robust design rules.
- Elaborating /validating a set of CDM protections and strategies adapted to sensitive context as RADAR for example.
- Investigation on CDM Simulation tool or algorithms at package level (package + die)
Mis à jour le 17 March 2022