Seminar by Prof. Abhijit CHATTERJEE (School of ECE, Atlanta - USA) - "Machine Learning Driven AMS Validation, Test and Tuning: Pre Through Post-Silicon"

on the 8 December 2022
08/12/2022 - 14:00

"Machine Learning Driven AMS Validation, Test and Tuning: Pre Through Post-Silicon"
By Abhijit CHATTERJEE, School of ECE, Georgia Institute of Technology, Atlanta, GA
Introduced by Manuel BARRAGAN (RMS team)

Abstract: Top-down design transformation from behavioral models to transistor netlists to physical layout consists of iterative refinement of the parameters of the component models in a hierarchical manner until the design parameters at the transistor netlist and physical layout of the system are optimal. Throughout this process, discrepancies between input-output behavior as predicted by higher level models vs. low level design descriptions need to be detected and debugged at each step and may arise from modeling errors (including process variability effects) or unknown design bugs. Consequently, the debugging technique cannot be predicated on assumed design bug models; the bugs need to be discovered and modeled during design debug itself. To address these issues, we develop collaborative test generation and behavior learning algorithms for detection of behavioral discrepancies between high level behavioral design descriptions (AHDL) and low level (netlist, silicon) module implementations across the entire stimulus space of the design. For post-silicon, we also investigate how machine learning algorithms can be used to self-test and self-tune complex AMS systems using prior alternative test techniques combined with novel reinforcement learning algorithms. Novel embedded sensors for high-speed circuits can be used to reconstruct the response of embedded circuits components using back-end signal processing. Simulation results and hardware measurements demonstrate the viability of the proposed techniques.

Bio: Abhijit CHATTERJEE is a Professor in the School of Electrical and Computer Engineering at Georgia Tech and a Fellow of the IEEE. He received his Ph.D in electrical and computer engineering from the University of Illinois at Urbana-Champaign in 1990. Dr. CHATTERJEE received the NSF Research Initiation Award in 1993 and the NSF CAREER Award in 1995. He has received seven Best Paper Awards and three Best Paper Award nominations. His work on self-healing chips was featured as one of General Electric’s key technical achievements in 1992 and was cited by the Wall Street Journal. In 1995, he was named a Collaborating Partner in NASA’s New Millennium project. In 1996, he received the Outstanding Faculty for Research Award from the Georgia Tech Packaging Research Center, and in 2000, he received the Outstanding Faculty for Technology Transfer Award, also given by the Packaging Research Center. In 2007, his group received the Margarida Jacome Award for work on VIZOR: Virtually Zero Margin Adaptive RF from the Berkeley Gigascale Research Center (GSRC). Dr. CHATTERJEE has authored over 450 papers in refereed journals and meetings and has 22 patents. He is a co-founder of Ardext Technologies Inc., a mixed-signal test solutions company and served as chairman and chief scientist from 2000-2002. His research interests include error-resilient signal processing and control systems, mixed-signal/RF/multi-GHz design and test and adaptive real-time systems.

Mis à jour le 8 December 2022