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114 résultats

  21 Revues internationales
   1 Brevets
   5 Conférences invitées
  61 Conférences internationales
   8 Chapitres de livre
   2 Revues nationales
   7 Conférences nationales
   2 Autres communications
   7 Rapports

21 Revues internationales

 1 Charif A., Coelho A., Ebrahimi M., Bagherzadeh N., Zergainoh N.-E., First-Last: A Cost-Effective Adaptive Routing Solution for TSV-Based Three-Dimensional Networks-on-Chip, IEEE Transactions on Computers, Ed. IEEE, Vol. 67, No. 10, pp. 1430-1444, DOI: 10.1109/TC.2018.2822269, octobre 2018
 
 2 Bonnoit T., Zergainoh N.-E., Nicolaidis M., Reducing Rollback Cost in VLSI Circuits to Improve Fault Tolerance, Transactions on Very Large Scale Integration (VLSI) Systems, Ed. IEEE, Vol. 26, No. 8, pp. 1438-1451, DOI: 10.1109/TVLSI.2018.2818021, août 2018
 
 3 Ramos P., Vargas V., Baylac M., Zergainoh N.-E., Velazco R., SEE error-rate evaluation of an application implemented in COTS Multi/Many-core processors, IEEE Transactions on Nuclear Science, Ed. IEEE, Vol. 65, No. 8, pp. 1879-1886, DOI: 10.1109/TNS.2018.2838526, août 2018
 
 4 Ramos P., Vargas V., Zergainoh N.-E., Velazco R., Assessing the Static and Dynamic Sensitivity of a Commercial Off-the-Shelf Multicore Processor for Noncritical Avionic Applications, Journal of Nanotechnology, Ed. Hindawi Publishing Corporation, Vol. 2018, No. ID 2926392, pp. 1-8, DOI: 10.1155/2018/2926392, juillet 2018
 
 5 Charif A., Coelho A., Zergainoh N.-E., Nicolaidis M., A Framework for Scalable TSV Assignment and Selection in Three-Dimensional Networks-on-Chip, Journal of VLSI Design, Ed. Hindawi Publishing Corporation, Vol. , DOI: 10.1155/2017/9427678, 2017
 
 6 Charif A., Coelho A., Zergainoh N.-E., Nicolaidis M., A Dynamic Sufficient Condition of Deadlock-Freedom for High-Performance Fault-Tolerant Routing in Networks-on-Chips, IEEE Transactions on Emerging Topics in Computing, Ed. IEEE, Vol. PP, No. 99, DOI: 10.1109/TETC.2017.2776909, novembre 2017
 
 7 Fraire J., Madoery P., Burleigh S., Charif A., Zergainoh N.-E., Velazco R., Assessing Contact Graph Routing Performance and Reliability in Distributed Satellite Constellations, Journal of Computer Networks and Communications, Ed. Hindawi Publishing Corporation, Vol. 2017, pp. 1-18, DOI: 10.1155/2017/2830542, juillet 2017
 
 8 Coelho A., Laurent R., Solinas M., Fraire J., Mazer E., Zergainoh N.-E., Velazco R., On the Robustness of Stochastic Bayesian Machines, IEEE Transactions on Nuclear Science, Ed. IEEE, Vol. PP, No. 99, DOI: 10.1109/TNS.2017.2678204, mars 2017
 
 9 Vargas V., Ramos P., Ray V., Jalier C., Stevens R., Dupont De Dinechin B., Baylac M., Villa F., Rey S., Zergainoh N.-E., Méhaut J-F., Velazco R., Radiation Experiments on a 28nm Single-Chip Many-core Processor and SEU error-rate prediction, IEEE Transactions on Nuclear Science, Ed. IEEE, Vol. 64, No. 1, pp. 483-490, DOI: 10.1109/TNS.2016.2638081, janvier 2017
 
10 Ramos P., Vargas V., Clemente J.A., Zergainoh N.-E., Méhaut J-F., Velazco R., Evaluating the SEE Sensitivity of a 45 nm SOI Multi-Core Processor Due to 14 MeV Neutrons, IEEE Transactions on Nuclear Science, Ed. IEEE, Vol. 63, No. 4, pp. 2193 - 2200, DOI: 10.1109/TNS.2016.2537643, juillet 2016
 
11 Dimopoulos M., Gang Yi, Anghel L., Benabdenbi M., Zergainoh N.-E., Nicolaidis M., Fault-Tolerant Adaptive Routing under an Unconstrained Set of Node and Link Failures for Many-Core Systems-on-Chip, Microprocessors and Microsystems, Ed. Elsevier, Vol. 38, No. 6, pp. 620–635, DOI: 10.1016/j.micpro.2014.04.003, août 2014
 
12 Bonnoit T., Nicolaidis M., Zergainoh N.-E., Using Error Correcting Codes without Speed Penalty in Embedded Memories: Algorithm, Implementation and Case Study, Journal of Electronic Testing: Theory and Applications, Ed. Springer , Vol. 29, No. 3, pp. 383-400, DOI: 10.1007/s10836-013-5386-8, juin 2013
 
13 Vivet P., Beigné E., Lebreton H., Zergainoh N.-E., On-line Power Optimization of Data Flow Multi-Core Architecture Based on Vdd-Hopping for Local Dynamic Voltage and Frequency Scaling, Journal of Low Power Electronics (JOLPE), Ed. American Scientific Publishers, Vol. 7, No. 2, pp. 265-273, DOI: http://dx.doi.org/10.1166/jolpe.2011.1135, avril 2011
 
14 Cho Y., Zergainoh N.-E., Yoo S., Jerraya A. A., Choi K., Scheduling with accurate communication delay model and scheduler implementation for multiprocessor system-on-chip , Design Automation for Embedded Systems, Ed. Springer , Vol. 11, No. 2-3, pp. 167-191, DOI: 10.1007/s10617-007-9004-9, 2007
 
15 Zergainoh N.-E., Tambour L., Urard P., Jerraya A. A., Macrocell builder: IP block-based design Environment for high-throughput VLSI dedicated digital signal processing systems, Journal on Applied Signal Processing, Vol. 2006, No. 1/Article ID 28636, pp. 1-11, DOI: 10.1155/ASP/2006/28636, décembre 2006
 
16 Zergainoh N.-E., Tambour L., Jerraya A. A., Automatic delay correction method for IP block-based design of VLSI dedicated digital signal processing systems: theoretical foundations and implementation, Transactions on Very Large Scale Integration (VLSI) Systems, Ed. IEEE, Vol. 14, No. 4, pp. 349- 360, janvier 2006
 
17 Zergainoh N.-E., Baghdadi A., Jerraya A. A., Hardware/software codesign of on-chip communication architecture for application-specific multiprocessor system-on-chip, IJES - International Journal of Embedded Systems , Ed. InderScience Publishers, Vol. 1/2, No. 1, pp. 112-124, janvier 2005
 
18 Zergainoh N.-E., Baghdadi A., Jerraya A. A., A generic architecture platform based-methodology for an efficient design of Hardware/Software application-specific multiprocessor System-On-Chip , Annals of Telecommunications - annales des télécommunications, Ed. Springer , Vol. 59, No. 7-8, pp. 784-806, juillet-août 2004
 
19 Baghdadi A., Zergainoh N.-E., Cesario W., Jerraya A. A., Combining a performance estimation methodology with a hardware/software codesign flow supporting multiprocessor systems, IEEE Transactions on Software Engineering, Ed. IEEE, Vol. 28, No. 9, pp. 822 - 831, DOI: 10.1109/TSE.2002.1033223, septembre 2002
 
20 Hessel F., Coste P., Le Marrec Ph., Zergainoh N.-E., Nicolescu G., Daveau J.- M., Jerraya A. A., Interlanguage Communication Synthesis for Heterogeneous Specifications, Design Automation for Embedded Systems, Ed. Springer , Vol. 5, No. 3-4, pp. 223-236, DOI: 10.1023/A:1008945917092, août 2000
 
21 Zergainoh N.-E., Sorel Y., An Architecture for an efficient multiprocessor development environment: the fast distributed executive for reactive system, Journal of Systems Architecture (JSA), Ed. Elsevier, Vol. , décembre 1995
 
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1 Brevets

1 Sahnine C., Callonnec D., Zergainoh N.-E., Pétrot F., Composant de traitement d'un signal numérique, dispositif de modulation et/ou de démodulation multiporteuse, procédé de modulation et/ou de démodulation et programme d'ordinateur correspondants , No. WO/2008/145915 / PCT/FR2008/050703, 4 décembre 2008
 
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5 Conférences invitées

1 Chaix F., Bizot G. , Nicolaidis M., Zergainoh N.-E., Variability-aware task mapping strategies for many-cores processor chips, IEEE International On-line Testing Symposium (IOLTS'11), pp. 55 - 60 , Athens, GREECE, DOI: 10.1109/IOLTS.2011.5993811 , 13 au 15 juillet 2011
 
2 Bizot G. , Zergainoh N.-E., Nicolaidis M., Energy and variability aware scheduling for clusterized mpsoc architecture, IEEE Design for Reliability and Variability (DRVW'09), Austin,TX, UNITED STATES, 5 au 6 novembre 2009
 
3 Bizot G. , Zergainoh N.-E., Nicolaidis M., Variability and Reliability-Aware Application tasks scheduling and power control (Voltage and Frequency Scaling) in the future Nanoscale Chip Multiprocessors, IEEE International On-line Testing Symposium (IOLTS'09), Lisbon, PORTUGAL, 24 au 26 juin 2009
 
4 Zergainoh N.-E., Marchioro G.F., Jerraya A. A., Hw/Sw codesign of an ATM network interface card starting from a system level specification, URSI International Symposium on Signals, Systems, and Electronics (ISSSE'98), pp. 315-320, Pisa, ITALY, DOI: 10.1109/ISSSE.1998.738090, 29 septembre au 2 octobre 1998
 
5 Zergainoh N.-E., Marchioro G.F., Daveau J.- M., Jerraya A. A., Using SDL for hardware/software co-design of an ATM network interface card, 1st Workshop of the forum society on SDL and MSC, Berlin, GERMANY, 29 juin au 1 juillet 1998
 
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61 Conférences internationales

 1 Coelho A., Charif A., Zergainoh N.-E., Velazco R., A Runtime Fault-Tolerant Routing Scheme for Partially Connected 3D Networks-on-Chip, IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT 2018), pp. 1-6, Chicago, UNITED STATES, 8 au 10 octobre 2018
 
 2 Coelho A., Charif A., Zergainoh N.-E., Fraire J., Velazco R., A soft-error resilient route computation unit for 3D Networks-on-Chips, Design, Automation & Test in Europe (DATE'2018), Dresden, GERMANY, 19 au 23 mars 2018
 
 3 Bonnoit T., Bouesse G.F., Zergainoh N.-E., Nicolaidis M., Designing reliable processor cores in ultimate CMOS and beyond: A double sampling solution, Design, Automation & Test in Europe (DATE'2018), Dresden, GERMANY, 19 au 23 mars 2018
 
 4 Charif A., Zergainoh N.-E., Coelho A., Nicolaidis M., Rout3D: A Lightweight Adaptive Routing Algorithm for Tolerating Faulty Vertical Links in 3D-NoCs, 22th IEEE European Test Symposium (ETS 2017), pp. 1-6, Limassol, CYPRUS, 22 au 26 mai 2017
 
 5 Solinas M., Coelho A., Fraire J., Zergainoh N.-E., Velazco R., TGV: Tester Generic and Versatile for Radiation Effects on Advanced VLSI Circuits, IEEE/ACM Design, Automation, and Test in Europe (DATE 2017), Univ. Booth, Lausanne, SWITZERLAND, 27 au 31 mars 2017
 
 6 Charif A., Zergainoh N.-E., Nicolaidis M., GNOCS: an ultra-fast, highly extensible, cycle-accurate GPU-Based parallel Network-on-Chip simulator, Design, Automation & Test in Europe Conference, Univ.Booth (DATE 2017), Lausanne, SWITZERLAND, 23 au 31 mars 2017
 
 7 Charif A., Coelho A., Zergainoh N.-E., Nicolaidis M., MINI-ESPADA: A Low-Cost Fully Adaptive Routing Mechanism for Networks-on-Chips, IEEE Latin-American Test Symposium (LATS 2017), pp. 1-4, Bogota, COLOMBIA, 13 au 15 mars 2017
 
 8 Bonnoit T., Coelho A., Zergainoh N.-E., Velazco R., SEU Impact in Processor's Control-Unit: Preliminary Results Obtained for LEON3 Soft-Core, 18th IEEE Latin American Test Symposium (LATS 2017), pp. 1-4, Bogota, COLOMBIA, 13 au 15 mars 2017
 
 9 Solinas M., Coelho A., Fraire J., Zergainoh N.-E., Ferreyra P., Velazco R., Preliminary Results of NETFI-2: An Automatic Method for Fault Injection on HDL-Based Designs, 18th IEEE Latin-American Test Symposium (LATS 2017), Bogota, COLOMBIA, 1 mars 2017
 
10 Bonnoit T., Zergainoh N.-E., Nicolaidis M., Velazco R., Low Cost Rollback to Improve Fault-Tolerance in VLSI Circuits, IEEE International Symposium on Circuits and Systems (LASCAS 2017), pp. 1-4, Bariloche, ARGENTINA, 20 au 23 février 2017
 
11 Charif A., Coelho A., Zergainoh N.-E., Nicolaidis M., Detailed and highly parallelizable cycle-accurate network-on-chip simulation on GPGPU, ACM/IEEE Design Automation Conference (ASPDAC 2017), pp. 672-677, Chiba/Tokyo, JAPAN, DOI: 10.1109/ASPDAC.2017.7858401, 16 au 19 janvier 2017
 
12 Charif A., Zergainoh N.-E., Nicolaidis M., A New Approach to Deadlock-Free Fully Adaptive Routing for High-Performance Fault-Tolerant NoCs, IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT'16), Connecticut, UNITED STATES, 19 au 21 septembre 2016
 
13 Coelho A., Solinas M., Laurent R., Fraire J., Mazer E., Zergainoh N.-E., Karaoui S., Velazco R., Evidences of Stochastic Bayesian Machines Robustness Against SEUs and SETs, IEEE European Conference on Radiation and its Effects on Components and Systems (RADECS'16), Bremen, GERMANY, 19 au 23 septembre 2016
 
14 Charif A., Zergainoh N.-E., Nicolaidis M., Addressing transient routing errors in fault-tolerant Networks-on-Chips, 21th IEEE European Test Symposium (ETS'06)), Amsterdam, NETHERLANDS, 23 au 27 mai 2016
 
15 Ramos P., Vargas V., Baylac M., Villa F., Rey S., Clemente J.A., Zergainoh N.-E., Velazco R., Sensitivity to Neutron Radiation of a 45 nm SOI Multi-Core Processor, Radiation and Its Effects on Components and Systems (RADECS’15), Moscow, RUSSIAN FED, DOI: 10.1109/RADECS.2015.7365665 , 14 au 18 septembre 2015
 
16 Charif A., Zergainoh N.-E., Nicolaidis M., MUGEN: A High-Performance Fault-Tolerant Routing Algorithm for Unreliable Networks-on- Chip, 21st IEEE International On-Line Testing Symposium (IOLTS'15), pp. 71-76, Halkidiki, GREECE, DOI: 10.1109/IOLTS.2015.7229835, 6 au 8 juillet 2015
 
17 Vargas V., Ramos P., Velazco R., Méhaut J-F., Zergainoh N.-E., Evaluating SEU fault-injection on parallel applications implemented on multicore processors, IEEE 6th Latin American Symposium on Circuits & Systems (LASCAS'15), pp. 1-4, Montevideo, URUGUAY, DOI: 10.1109/LASCAS.2015.7250449, 25 au 27 février 2015
 
18 Vargas V., Ramos P., Mansour W., Méhaut J-F., Velazco R., Zergainoh N.-E., Preliminary results of SEU Fault Injection on Multicore processors in AMP mode, 20th IEEE International On-Line Testing Symposium (IOLTS’14), pp. 194-197, Platja d'Aro, Girona, SPAIN, DOI: 10.1109/IOLTS.2014.6873694, 7 au 9 juillet 2014
 
19 Chaix F., Zergainoh N.-E., Nicolaidis M., A generic and high-level model of large unreliable NoCs for fault tolerance and performance analysis, 19th IEEE European Test Symposium (ETS'04), pp. 1-2, Paderborn, GERMANY, DOI: 10.1109/ETS.2014.6847827, 26 au 30 mai 2014
 
20 Gang Yi, Dimopoulos M., Benabdenbi M., Anghel L., Zergainoh N.-E., Nicolaidis M., Fault-tolerant adaptive routing under static and run-time, permanent and transient failures for many-core systems-on-chip, IEEE International On-Line Testing symposium (IOLTS'13), pp. 7 - 12 , Chania, CRETE, DOI: 10.1109/IOLTS.2013.6604043, 8 au 10 juillet 2013
 
21 Chaix F., Bizot G. , Nicolaidis M., Zergainoh N.-E., Variability-aware and fault-tolerant self-adaptive applications for many-core chips , IEEE International On-Line Testing Symposium (IOLTS'13), pp. 37-42, Chania, CRETE, DOI: 10.1109/IOLTS.2013.6604048, 8 au 10 juillet 2013
 
22 Bizot G. , Chaix F., Zergainoh N.-E., Nicolaidis M., Variability-Aware and Fault-tolerant Self-Adaptive applications for Many-Core chips, European Test Symposium (ETS'13), pp. 162, Avignon, FRANCE, 27 au 30 mai 2013
 
23 Bizot G. , Avresky D., Chaix F., Zergainoh N.-E., Nicolaidis M., Adaptive Mapping of Parallelized Application (Fork-join DAG) on Multicore System in the Presence of Multiple Failures, IEEE 26th International Parallel and Distributed Processing Symposium Workshops & PhD Forum (IPDPSW'12), Shanghai, CHINA, 21 au 25 mai 2012
 
24 Nicolaidis M., Anghel L., Zergainoh N.-E., Zorian Y., Karnik T., Bowman K., Tschanz J., Lu S.-L., Tokunaga C., Raychowdhury A., Khellah M., Kulkarini J., Vivek De, Avresky D., Design for Test and Reliability in Ultimate CMOS, Design, Automation and Test in Europe (DATE'12), pp. 677-682, Dresden, GERMANY, 12 au 16 mars 2012
 
25 Nicolaidis M., Anghel L., Zergainoh N.-E., Avresky D., Designing Single Chip Massively Parallel Processors Affected by Extreme Failure Rates, Design, Automation & Test in Europe Conference & Exhibition (DATE'12), Dresden, GERMANY, 12 au 16 mars 2012
 
26 Bonnoit T., Nicolaidis M., Zergainoh N.-E., Towards a Tool for Implementing Delay-Free ECC in Embedded Memories, IEEE International Conference on Computer Design (ICCD’11), pp. 441 - 442 , Amherst, Ma, UNITED STATES, DOI: 10.1109/ICCD.2011.6081440 , 9 au 12 octobre 2011
 
27 Bizot G. , Avresky D., Chaix F., Zergainoh N.-E., Nicolaidis M., Self-Recovering Parallel Applications in Multi-Core Systems, 10th IEEE International Symposium on Network Computing and Applications (NCA’11), pp. 51 - 58 , Cambridge, MA, UNITED STATES, DOI: 10.1109/NCA.2011.14 , 25 au 27 août 2011
 
28 Ferran J., Remond E., Ollagnon P.F., Landelle S., Zergainoh N.-E., Nicolaidis M., Fast Standard Cells Statistical Characterization for SSTA Based on Design of Experiment Approach in 45nm MOSFETs Technology, IEEE European Workshop CMOS Variability (VARI'11), Grenoble, FRANCE, 30 au 31 mai 2011
 
29 Yu H., Nicolaidis M., Anghel L., Zergainoh N.-E., Efficient Fault Detection Architecture Design of Latch-Based Low Power DSP/MCU Processor , 16th IEEE European Test Symposium (ETS'11), pp. 93 - 98 , Trondheim, NORWAY, DOI: 10.1109/ETS.2011.20 , 23 au 27 mai 2011
 
30 Chaix F., Bizot G. , Nicolaidis M., Zergainoh N.-E., Variability-aware Task mapping strategies for Many-cores processor chips, Workshop on Design for Reliability and Variability (DRVW’11), Dana Point, CA, UNITED STATES, 4 au 5 mai 2011
 
31 Chaix F., Avresky D., Zergainoh N.-E., Nicolaidis M., A Fault-Tolerant Deadlock-Free Adaptive Routing for On Chip Interconnects, Best IP Award, Design Automation and Test in Europe Conference (DATE’11), pp. 1-4, Grenoble, FRANCE, 14 au 18 mars 2011
 
32 Nicolaidis M., Bonnoit T., Zergainoh N.-E., Eliminating speed penalty in ECC protected memories , Design Automation and Test in Europe Conference (DATE’11), pp. 1-6, Grenoble, FRANCE, 14 au 18 mars 2011
 
33 Chaix F., Zergainoh N.-E., Nicolaidis M., VOCIS: A Versatile Simulation model for On-chip interconnect fault tolerance and performance, IEEE Design, Automation and Test in Europe (DATE'11) Univ. Booth, Grenoble, FRANCE, 14 au 18 mars 2011
 
34 Vivet P., Beigné E., Lebreton H., Zergainoh N.-E., On Line Power Optimization of Data Flow Multi-core Architecture Based on Vdd-Hopping for Local DVFS, 20th IEEE International Workshop d Timing Modeling, Optimization and Simulation (PATMOS'10), Grenoble, FRANCE, 7 septembre au 24 octobre 2010
 
35 Chaix F., Avresky D., Zergainoh N.-E., Nicolaidis M., Fault-Tolerant Deadlock-Free Adaptive Routing for Any Set of Link and Node Failures in Multi-Cores Systems, IEEE International Symposium on Network Computing and Applications (NCA'10), pp. 52-59, Cambridge, Ma., UNITED STATES, DOI: 10.1109/NCA.2010.14 , 15 au 17 juillet 2010
 
36 Atat Y., Zergainoh N.-E., Automatic Code Generation for MPSoC Platform Starting From Simulink/Matlab : New Approach to Bridge the Gap between Algorithm and Architecture Design, 3rd International Conference on Information and Communication Technologies: From Theory to Applications (ICTTA’08), pp. 1-6, Damascus, SYRIAN ARAB REPUBLIC, DOI: 10.1109/ICTTA.2008.4530348 , 7 au 11 avril 2008
 
37 Cho Y., Zergainoh N.-E., Jerraya A. A., Choi K., Buffer Size Reduction through Control-Flow Decomposition, IEEE International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA'07), pp. 183-190, Daegu, KOREA, DOI: 10.1109/RTCSA.2007.25 , 21 au 23 août 2007
 
38 Sahnine C., Zergainoh N.-E., Callonnec D., Pétrot F., Towards a High-Throughput and Low Power Reconfigurable Architecture of Advanced OFDM Modulator for Software-Defined Radio Systems, IEEE International Midwest Symposium on Circuits and Systems (MWSCAS’07), pp. 1205-1208, Montréal, CANADA, DOI: 10.1109/NEWCAS.2007.4488010, 5 au 8 août 2007
 
39 Cho Y., Zergainoh N.-E., Choi K., Jerraya A. A., Low Runtime-Overhead Software Synthesis for Communicating Concurrent Processes, IEEE/IFIP International Workshop on Rapid System Prototyping (RSP’07), pp. 195-201, Porto Alegre, BRAZIL, DOI: 10.1109/RSP.2007.27 , 28 au 30 mai 2007
 
40 Atat Y., Zergainoh N.-E., Simulink-based MPSoC Design: New Approach to Bridge the Gap between Algorithm and Architecture Design, IEEE Computer Society Annual Symposium on VLSI (ISVLSI '07), pp. 9-14, Porto Alegre, BRAZIL, DOI: 10.1109/ISVLSI.2007.90, 9 au 11 mars 2007
 
41 Sahnine C., Zergainoh N.-E., Callonnec D., Pétrot F., Efficient Design Approach and Advanced Architectures for Universal OFDM Systems, PhD research in Microelectronics and Electronics (PRIME’07), pp. 33-36, Bordeaux, FRANCE, DOI: 10.1109/RME.2007.4401804, 1 janvier 2007
 
42 Zergainoh N.-E., Popovici K., Jerraya A. A., Urard P., IP-block-based design environment for high-throughput VLSI dedicated digital signal processing systems, Asia and South Pacific Design Automation Conference (ASP-DAC'05), pp. 612-618, Shanghai, CHINA, 18 au 21 janvier 2005
 
43 Cho Y., Yoo S., Choi K., Zergainoh N.-E., Jerraya A. A., Scheduler implementation in MPSoC Design, Asia South Pacific Design Automation Conference (ASP-DAC'05), pp. 151-156, Shangai, CHINA, DOI: 10.1109/ASPDAC.2005.1466148 , 18 au 21 janvier 2005
 
44 Zergainoh N.-E., Jerraya A. A., Popovici K., Urard P., Matlab based environment for designing DSP systems using IP blocks, The 12th Workshop on Synthesis and System Integration of Mixed Information technologies (SASIMI'04), pp. 296 - 302, Kanazawa, JAPAN, 18 au 19 octobre 2004
 
45 Tambour L., Zergainoh N.-E., Urard P., Michel H., Jerraya A. A., An efficient methodology and semi automated flow for design and validation of complex digital signal processing ASICS macro cells, 14th IEEE International Workshop on Rapid Systems Prototyping (RSP'03), pp. 56-63, San Diego, California, UNITED STATES, DOI: 10.1109/IWRSP.2003.1207030, 9 au 11 juin 2003
 
46 Cho Y., Choi K., Zergainoh N.-E., Lee G., Yoo S., Scheduling and timing analysis of HW/SW on-chip communication in MP SoC design, Design, Automation and Test in Europe (DATE'03), Munich, GERMANY, 3 au 7 mars 2003
 
47 Baghdadi A., Zergainoh N.-E., Lyonnard D., Jerraya A. A., Generic architecture platform for multiprocessor system-on-chip design, International Workshop on Distributed and Parallel Embedded Systems (DIPES'00), pp. 53-63, Paderborn, GERMANY, 1 octobre 2001
 
48 Baghdadi A., Lyonnard D., Zergainoh N.-E., Jerraya A. A., An efficient architecture model for systematic design of application-specific multiprocessor SoC, Design, Automation and Test in Europe Conference (DATE'01), pp. 55-62, Munich, GERMANY, DOI: 10.1109/DATE.2001.915001, 13 au 16 mars 2001
 
49 Baghdadi A., Zergainoh N.-E., Lyonnard D., Jerraya A. A., Generic architecture platform for multiprocessor embedded system-on-chip design, International Workshop on Distributed and Parallel Embedded Systems (DIPES'00), pp. 53-64, Paderborn, GERMANY, 1 octobre 2000
 
50 Hessel F., Coste P., Nicolescu G., Le Marrec Ph., Zergainoh N.-E., Jerraya A. A., Multi-level communication synthesis of heterogeneous multilanguage specification, International Conference on Computer Design (ICCD'00), pp. 525-530, Austin, Texas, UNITED STATES, DOI: 10.1109/ICCD.2000.878332, 17 au 20 septembre 2000
 
51 Hessel F., Coste P., Nicolescu G., Le Marrec Ph., Zergainoh N.-E., Jerraya A. A., Multi-level communication synthesis of heterogeneous multilanguage specifications, International Conference on Computer Design (ICCD'00), Austin, Texas, UNITED STATES, 17 au 20 septembre 2000
 
52 Baghdadi A., Zergainoh N.-E., Cesario W., Roudier T., Jerraya A. A., Design space exploration for hardware/software codesign of multiprocessor systems, 11th International Workshop on Rapid System Prototyping (RSP'00), pp. 8-13, Paris, FRANCE, DOI: 10.1109/IWRSP.2000.854975, 21 au 23 juin 2000
 
53 Mir S., Charlot B., Nicolescu G., Coste P., Parrain F., Zergainoh N.-E., Courtois B., Jerraya A. A., Rencz M., Towards design and validation of mixed-technology SOCs, Great Lakes Symposium on VLSI , pp. 29 - 33, Chicago, Illinois, UNITED STATES, DOI: 10.1145/330855.330950, 2 au 4 mars 2000
 
54 Zergainoh N.-E., Baghdadi A., Tambour L., Lyonnard D., Gauthier L., Jerraya A. A., Framework for system design, validation and fast prototyping of multiprocessor system-on-chip: applied to telecommunication systems, International Workshop on Distributed and Parallel Embedded Systems (DIPES'00), Paderborn, GERMANY, 18 au 19 janvier 2000
 
55 Hessel F., Coste P., Le Marrec Ph., Zergainoh N.-E., Daveau J.- M., Jerraya A. A., Communication interface synthesis for multilanguage specifications, IEEE International Workshop on Rapid System Prototyping (RSP'99), pp. 15-20, Clearwater, Florida , UNITED STATES, DOI: 10.1109/IWRSP.1999.779025, 16 au 18 juin 1999
 
56 Coste P., Hessel F., Le Marrec Ph., Sugar Z., Romdhani A., Suescun R., Zergainoh N.-E., Jerraya A. A., Multilanguage design of heterogeneous systems, Seventh International Workshop on Hardware/Software Codesign (CODES'99), pp. 54-58, Rome, ITALY, DOI: 10.1145/301177.301206, 3 mars 1999
 
57 Zergainoh N.-E., Bouaziz S., Maurin T., Design and implementation of embedded executive for an obstacle detection system, IFAC International Workshop on Intelligent Components for Autonomous and semi-autonomous Vehicles (ICASAV'95), pp. 95-100, Toulouse, FRANCE, 25 au 26 octobre 1995
 
58 Zergainoh N.-E., Bouaziz S., Maurin T., Efficient Implementation of fast Distributed Kernel for heterogeneous multiprocessor systems, International conference on Signal processing Applications & technologies (ICSPAT'95), Boston, Massachusetts, UNITED STATES, 24 au 26 octobre 1995
 
59 Zergainoh N.-E., Bouaziz S., Maurin T., Real-time distributed executive for an obstacle detection system, IEEE Intelligent Vehicles Symposium 1995, Detroit, UNITED STATES, 25 au 26 septembre 1995
 
60 Zergainoh N.-E., Maurin T., Reynaud R., Synchronous protocol for real-time communications in intelligent vehicle, IEEE Intelligent Vehicles Symposium, Paris, FRANCE, 24 au 26 octobre 1994
 
61 Zergainoh N.-E., Maurin T., Sorel Y., Lavarenne Ch., A Real Time Multiprocessor Application Development Environment Design And Implementation, IEEE Workshop on Parallel and Distributed Processing, Malaga, SPAIN, 26 au 28 janvier 1994
 
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8 Chapitres de livre

1 Ramos P., Vargas V., Velazco R., Zergainoh N.-E., Error Rate Prediction of Applications Implemented in Multi-Core and Many-Core Processors, Radiation Effects on Integrated Circuits and Systems for Space Applications, Velazco R., McMorrow D., Estela J. (Eds.) , Ed. Springer , pp. 145-173, Vol. 2, 2019
 
2 Vivet P., Beigné E., Lebreton H., Zergainoh N.-E., On Line Power Optimization of Data Flow Multi-core Architecture Based on Vdd-Hopping for Local DVFS, Integrated Circuit and System Design, Power and Timing Modeling, Optimization, and Simulation, René van Leuken, Gilles Sicard (Eds.) , Ed. Springer , pp. 94-104, Vol. 6448, 2011
 
3 Jerraya A. A., Daveau J.- M., Marchioro G.F., Valderrama C., Romdhani M., Ben Ismail T., Zergainoh N.-E., Hessel F., Coste P., Le Marrec Ph., Baghdadi A., Gauthier L., Hardware/Software Codesign , Design of Systems on Chip, Design and test, Reis Ricardo, Lubaszewski Marcelo, Jess Jochen A.G. (Eds.) , Ed. Springer , pp. 133-158, 2007
 
4 Cho Y., Lee G., Choi K., Yoo S., Zergainoh N.-E., Scheduling and timing analysis of HW/SW on-chip communication in MP SoC design, Embedded Software for SoC, Ed. Kluwer Academic Publishers, pp. 125-136, DOI: hal-00016129 , 2003
 
5 Zergainoh N.-E., Méthodologie et modèles pour la conception digitale, Conception de haut niveau des systèmes monopuces, JERRAYA, A. (Eds.) , Ed. Hermès, pp. chapitre 1 : 19-64, 2002
 
6 Baghdadi A., Zergainoh N.-E., Lyonnard D., Jerraya A. A., Generic architecture platform for multiprocessor system-on-chip design, Architecture and Design of Distributed Embedded Systems, IFIP WG10.3/WG10.4/WG10.5 International Workshop on Distributed and Parallel Embedded Systems (DIPES 2000) October 18–19, 2000, Schloß Eringerfeld, Germany, Kleinjohann, Bernd (Eds.) , Ed. Kluwer Academic Publishers, pp. 53-63, 2001
 
7 Zergainoh N.-E., Baghdadi A., Tambour L., Lyonnard D., Gauthier L., Jerraya A. A., Framework for system design, validation and fast prototyping of multiprocessor SoCs, Architecture and Design of Distributed Embedded Systems Series: IFIP International Federation for Information Processing,, Ed. Kluwer Academic Publishers, pp. ., 2001
 
8 Jerraya A. A., Romdhani A., Le Marrec Ph., Hessel F., Coste P., Valderrama C., Marchioro G.F., Daveau J.- M., Zergainoh N.-E., Multilanguage specification for system design and codesign, System-Level Synthesis, Ed. Kluwer Academic Publishers, pp. Vol. 357, 1999
 
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2 Revues nationales

1 Zergainoh N.-E., Tambour L., Michel H., Jerraya A. A., Delay Correction in RTL Models of DSP SoC obtained by IP-based design approach, Technique et Science Informatiques (TSI), Vol. 24/10, pp. 1227-1257, 2005
 
2 Baghdadi A., Zergainoh N.-E., Cesario W., Jerraya A. A., Architecture design space exploration for hardware/software codesign: system-level performance estimation, Technique et Science Informatiques (TSI), Vol. 21, No. 1, pp. 9-35, DOI: 10.3166/tsi.21.9-35 , janvier 2002
 
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7 Conférences nationales

1 Bonnoit T., Zergainoh N.-E., Nicolaidis M., Robustesse des mémoires embarquées dans une architecture reconfigurable d un modulateur OFDM, GDR SoC-SiP : System-on-Chip & System-in-Package, Cergy, FRANCE, 9 au 11 juin 2010
 
2 Chaix F., Zergainoh N.-E., Nicolaidis M., Routage adaptatif pour MPSoC résistant aux défaillances de noeuds et de liens, GDR SoC-SiP : System-on-Chip & System-in-Package, Cergy, FRANCE, 9 au 11 juin 2010
 
3 Bizot G. , Zergainoh N.-E., Nicolaidis M., Variation-Aware Multilevel Scheduling and Power Management for Multi-core System-on-Chip, GDR SoC-SiP System-on-Chip & System-in-Package, Cergy, FRANCE, 9 au 11 juin 2010
 
4 Atat Y., Zergainoh N.-E., Jerraya A. A., Environnement de Conception, de Validation, et de Prototypage Rapide des Systèmes Multiprocesseurs sur Puce, pour les applications de traitement de signal, 9ème Journées Nationales en Microélectronique, Rennes, FRANCE, 10 au 12 mai 2006
 
5 Atat Y., Zergainoh N.-E., Jerraya A. A., Conception des Systèmes sur puce à partir de Matlab\Simulink, 8ème Journées Nationales en Microélectronique, Paris, FRANCE, 10 au 12 mai 2005
 
6 Baghdadi A., Jerraya A. A., Zergainoh N.-E., Exploration et conception systématique d'architectures multiprocesseurs monopuces dédiées à des applications spécifiques, 3ème Colloque CAO de circuits et systèmes intégrés, Paris, FRANCE, 15 au 17 mai 2002
 
7 Tambour L., Urard P., Ghenassia F., Zergainoh N.-E., Valentin T., Jerraya A. A., Utilisation d'une méthode de correction de retards pour la vérification d'un assemblage de fonctions RTL par rapport à un assemblage de fonctions au niveau fonctionnel, 3ème Colloque CAO de circuits et systèmes intégrés, Paris, FRANCE, 15 au 17 mai 2002
 
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2 Autres communications

1 Ramos P., Vargas V., Baylac M., Zergainoh N.-E., Velazco R., Error-rate prediction of applications implemented in Multi-core and Many-core processors, Radiation Effects on Components Systems (RADECS'2017), Geneva, SWITZERLAND, 2017
 
2 Coelho A., Solinas M., Fraire J., Zergainoh N.-E., Ferreyra P., Velazco R., NETFI-2: An Automatic Method for Fault Injection on HDL-Based Designs, Design, Automation & Test in Europe (DATE 2017), Lausanne, SWITZERLAND, DOI: https://www.date-conference.com/system/files/file/date17/ubooth/119922.pdf, 2017
 
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7 Rapports

1 Yu H., Nicolaidis M., Anghel L., Zergainoh N.-E., Efficient Fault Dectection Architecture Design of Latch-based Low Power DSP/MCU Processor, ISRN: TIMA-RR--2011/01--FR, 1 janvier 2011
 
2 Hessel F., Coste P., Nicolescu G., Le Marrec Ph., Zergainoh N.-E., Jerraya A. A., Communication Synthesis of Multilanguage Specification, ISRN: TIMA-RR--00/06-1--FR, 1 janvier 2000
 
3 Baghdadi A., Zergainoh N.-E., Cesario W., Roudier T., Jerraya A. A., Design Space Exploration for Hardware/Software Codesign of Multiprocessor ArchitecturesMultiprocessor Architectures, ISRN: TIMA-RR--00/02-4--FR, 1 janvier 2000
 
4 Mir S., Charlot B., Nicolescu G., Coste P., Parrain F., Zergainoh N.-E., Courtois B., Jerraya A. A., Rencz M., Towards Design And Validation Of Mixed-Technology SOCs, ISRN: TIMA-RR--00/01-1--FR, 1 janvier 2000
 
5 Baghdadi A., Cesario W., Teruya M.Y., Roudier T., Zergainoh N.-E., Jerraya A. A., Estimation de performance au niveau système : une ouverture à l'exploration pour le codesign, ISRN: TIMA-RR--99-07-2--FR, 1 janvier 1999
 
6 Hessel F., Sugar Z., Suescun R., Zergainoh N.-E., Coste P., Le Marrec Ph., Romdhani M., Jerraya A. A., Multilanguage systems codesign, ISRN: TIMA-RR--99/01-2--FR, 1 janvier 1999
 
7 Jerraya A. A., Romdhani M., Le Marrec Ph., Hessel F., Coste P., Valderrama C., Marchioro G.F., Daveau J.- M., Zergainoh N.-E., Multilanguage specification for system design and codesign, ISRN: TIMA-RR--98/12-1--FR, 1 janvier 1998
 
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