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248 résultats

   21 Revues internationales
    4 Brevets
   18 Conférences invitées
  143 Conférences internationales
   12 Chapitres de livre
    9 Livres & Éditions Ouvrages
    1 Revues nationales
   14 Conférences nationales
    6 Autres communications
   17 Rapports
    2 Logiciels
    1 Thèses

21 Revues internationales

 1 Ayres A., Rozeau O., Borot B., Fesquet L., Batude P., Vinet M., Variance Analysis in 3D Integration: A Statistically Unified Model with Distance Correlations, IEEE Transactions on Electron Devices, Ed. IEEE, Vol. 66, No. 1, pp. 633-640, DOI: 10.1109/TED.2018.2879680, janvier 2019
 
 2 Elissati O., Cherkaoui A., El Hadbi A., Rieubon S., Fesquet L., Multi-phase low-noise digital ring oscillators with sub-gate-delay resolution, AEU - International Journal of Electronics and Communications, Ed. Elsevier, Vol. 84, pp. 74-83, DOI: 10.1016/j.aeue.2017.11.022, 2018
 
 3 El Hadbi A., Cherkaoui A., Simatic J., Elissati O., Fesquet L., An accurate time-to-digital converter based on a self-timed ring oscillator for on-the-fly time measurement, Analog Integrated Circuits and Signal Processing, Ed. Kluwer Academic Publishers, Vol. 97, No. 3, pp. 471-481, DOI: 10.1007/s10470-018-1223-4, décembre 2018
 
 4 Ferreira De Paiva Leite T., Fesquet L., Possamai Bastos R., A body built-in cell for detecting transient faults and dynamically biasing subcircuits of integrated systems, Microelectronics Reliability, Ed. Elsevier, Vol. 88-90, pp. 122-127, septembre 2018
 
 5 Kerstel E., Gardelein A., Barthelemy M., Gilot Y., Le Coarer E., Rodrigo J., Sequiès T., Borne V., Bourdarot G., Burlet J.-Y., Christidis A., Segura J., Boulanger B., Boutou V., Bouzat M., Chabanol M., Fesquet L., Fourati H., Moulin M., Niot J.-M., Possamai Bastos R., Robu B., Rolland E., Toru S., Fink M., Koduru Joshi S., Ursin R., Nanobob: a CubeSat mission concept for quantum communication experiments in an uplink configuration, EPJ Quantum Technology, Ed. Springer , Vol. 5, No. 6, DOI: 10.1140/epjqt/s40507-018-0070-7, juin 2018
 
 6 Possamai Bastos R., Acunha Guimaraes L., Torres F.S., Fesquet L., Architectures of Bulk Built-In Current Sensors for Detection of Transient Faults in Integrated Circuits, Microelectronics journal, Ed. Elsevier, Vol. , 2017
 
 7 Rolloff O., Possamai Bastos R., Fesquet L., Exploiting reliable features of asynchronous circuits for designing low-voltage components in FD-SOI technology, Microelectronics Reliability, Ed. Elsevier, Vol. 55, No. 9-10, pp. 1302-1306, DOI: 10.1016/j.microrel.2015.07.028, septembre-octobre 2015
 
 8 Durand S., Zakaria H., Fesquet L., Marchand N., A Robust and Energy-Efficient DVFS Control Algorithm for GALS-ANoC MPSoC in Advanced Technology under Process Variability Constraints , Advances in Computer Science : an International Journal, Vol. 3, No. 1, pp. 97-105, janvier 2014
 
 9 Qaisar S.-M., Fesquet L., Renaudin M., Adaptive rate filtering a computationally efficient signal processing approach, Signal Processing, Ed. Elsevier, Vol. 94, pp. 620-630 , DOI: 10.1016/j.sigpro.2013.07.019, janvier 2014
 
10 Beyrouthy T., Fesquet L., An asynchronous FPGA block with its tech-mapping algorithm dedicated to security applications, International Journal of Reconfigurable Computing, Ed. Hindawi Publishing Corporation, Vol. 2013, Article ID 517947, pp. 12 pages, DOI: 10.1155/2013/517947, 2013
 
11 Zakaria H., Fesquet L., Designing a Process Variability Robust Energy-Efficient Control for Complex SoCs , IEEE Journal on Emerging and Selected Topics in Circuits and Systems , Ed. IEEE, Vol. 1, No. 2, pp. 160 - 172 , DOI: 10.1109/JETCAS.2011.2159284 , juin 2011
 
12 Bidegaray-Fesquet B., Fesquet L., Non-uniform Filter interpolation in the frequency domain, An International Journal on Sampling Theory in Signal and Image Processing (STSIP), Ed. IEEE, Vol. 10, No. 1-2, pp. 17-35, DOI: http://stsip.org/, janvier 2011
 
13 Fesquet L., Bidegaray-Fesquet B., IIR digital filtering of non-uniformly sampled signals via state representation, International Journal of Signal Processing, Ed. World Academy of Science, Engeneering and Technology (WASET), Vol. 90, No. 10, pp. 2811-2821, DOI: 10.1016/j.sigpro.2010.03.030, janvier 2010
 
14 Qaisar S.-M., Fesquet L., Renaudin M., Adaptative Rate Sampling and Filtering based on level crossing sampling, Eurasip Advances in Signal Processing, Ed. Hindawi Publishing Corporation, Vol. 2009, Article ID 971656, pp. 12 pages, DOI: 10.1155/2009/971656 , 2009
 
15 Hamon J., Fesquet L., Miscopein B., Renaudin M., Constrained Asynchronous Ring Structures for Robust Digital Oscillators, Transactions on Very Large Scale Integration (VLSI) Systems, Ed. IEEE, Vol. 17, No. 7, pp. 907-919, DOI: 10.1109/TVLSI.2008.2011801, janvier 2009
 
16 Qaisar S.-M., Fesquet L., Renaudin M., A Signal Driven Adaptive Resolution Short-Time Fourier Transform, International Journal of Signal Processing, Ed. World Academy of Science, Engeneering and Technology (WASET), Vol. 5, No. 3, pp. 180-188, janvier 2009
 
17 Qaisar S.-M., Fesquet L., Renaudin M., Signal Driven Sampling and Filtering : A Promising Approach for Time Varying Signals Processing, International Journal of Signal Processing, Ed. World Academy of Science, Engeneering and Technology (WASET), Vol. 5, No. 3, pp. 189-197, janvier 2009
 
18 Qaisar S.-M., Fesquet L., Renaudin M., An Adaptive Resolution Computationally Efficient Short-Time Fourier Transform, Research Letters in Signal Processing, Ed. Hindawi Publishing Corporation, Vol. 2008, No. ID 932068, pp. 1-5, DOI: 10.1155/2008/932068, 2008
 
19 Allier E., Fesquet L., Sicard G., Renaudin M., Asynchronous level crossing analog to digital converters, Measurement, Vol. 37 , No. 4, pp. 296-309, DOI: 10.1016/j.measurement.2005.03.002, janvier 2005
 
20 Fesquet L., Es Salhiene M., Renaudin M., Asynchronous technology for energy reduction in embedded systems, Annals of Telecommunications - annales des télécommunications, Ed. Springer , Vol. 59, No. 7-8, pp. 984-997, juillet-août 2004
 
21 Allier E., Sicard G., Fesquet L., Renaudin M., A new type of Asynchronous Analog to Digital Interface, Journal of the International Measurement Confederation, Ed. Elsevier, Vol. 35 , No. 2, janvier 2004
 
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4 Brevets

1 Fesquet L., Hamon J., Cherkaoui A., Générateurs de nombres aléatoires vrais, No. FR 12 51079 , 6 février 2012
 
2 Bidegaray-Fesquet B., Fesquet L., Signal Processing for AsynchronouS Systems (SPASS), No. IDDN.FR.001.080019.000.S.P.2012.000.31235, 1 janvier 2012
 
3 Renaudin M., Sicard G., Fesquet L., Allier E., Method and device for analog-digital conversion, comprises a comparator delivering a pair of control signals to an increment-decrement block for computing new digital value, No. FR2835365, 22 juillet 2005
 
4 Renaudin M., Sicard G., Fesquet L., Allier E., Procédé et dispositif de conversion analogique-numérique, No. FR2835365, 1 août 2003
 
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18 Conférences invitées

 1 Fesquet L., Bidegaray-Fesquet B., Asynchronous Filters, Keynote talk, Event-Based Control, Communication and Signal Processing (EBCCSP'2018), Perpignan, FRANCE, 27 au 29 juin 2018
 
 2 Ferreira De Paiva Leite T., Iga R., Engels S., Possamai Bastos R., Fesquet L., Fine Grain Body-Biasing: A strategy for asynchronous circuits, Invited paper, Application, Design and Technology Conference (ADTC'2018), Grenoble, FRANCE, 12 au 14 juin 2018
 
 3 Fesquet L., Sensing and Sampling for Low-Power Applications, Keynote talk, 3rd International Conference on Advances in Signal, Image and Video Processing (SIGNAL'2018), Nice, FRANCE, 20 au 24 mai 2018
 
 4 Fesquet L., Germain S., Simatic J., Cherkaoui A., Le Pelleter T., Engels S., Event-based processing: a new paradigm for low-power, Keynote talk, 19th IEEE Mediterranean Electrotechnical Conference (MELECON'2018), Marrakesh, MOROCCO, 2 au 7 mai 2018
 
 5 Bonnaud O., Fesquet L., Hebrard L., Strategy for higher education in electronic circuits and systems in the perspective of the up-coming digital society, Keynote talk, Latin American Symposium on Circuits and Systems (LASCAS'2018), Puerto Vallarta, MEXICO, 25 au 28 février 2018
 
 6 Iga R., Ferreira De Paiva Leite T., Possamai Bastos R., Rolloff O., Diallo M., Fesquet L., Layout Strategies for Body Bias Islands in FD-SOI Systems, Séminaire invité, 20th International IP-SoC Conference and Exhibition (IP-SOC 2017), Grenoble, FRANCE, 6 au 7 décembre 2017
 
 7 Fesquet L., Darwish A., Sicard G., Low-power Event-driven Image Sensor, Keynote talk, First International Conference on Advances in Signal, Image and Video Processing (SIGNAL'16), Lisbon, PORTUGAL, 26 au 30 juin 2016
 
 8 Fesquet L., Simatic J., Darwish A., Cherkaoui A., Event-based design for mitigating energy in electronic systems, Keynote talk, OAGM & ARW Joint Workshop on "Computer Vision and Robotics", Wels, AUSTRIA, 11 au 13 mai 2016
 
 9 Al Khatib C., Gana M., Aktouf C., Fesquet L., A new methodology for implementing a distributed clock management system for low-power design, Workshop on High Performance Embedded Systems (HiPEAC'15), Amsterdam, NETHERLANDS, 19 au 21 janvier 2015
 
10 Fesquet L., Le Pelleter T., Darwish A., Beyrouthy T., Bidegaray-Fesquet B., Mitigating the data-deluge by an adequate sampling for low-power systems, 5th International Conference on Computational Harmonic Analysis, pp. 17, Nashville, UNITED STATES, 19 au 23 mai 2014
 
11 Fesquet L., Controling variability and energy by design, CMOS Emerging Technologies, Vancouver, BC, CANADA, 18 au 20 juillet 2012
 
12 Yahya E., Fesquet L., Renaudin M., Asynchronous circuit performance analysis, fundamentals and efficient tools, Invited Tutorial, 18th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC'12), Copenhagen, DENMARK, 7 au 9 mai 2012
 
13 Fesquet L., Thinking and Designing Differently: The Asynchronous Alternative, Dresden Microelectronic Academy, Dresden, GERMANY, 5 au 9 septembre 2011
 
14 Fesquet L., Zakaria H., Controlling Energy and Process Variability in System-on-Chips: needs for control theory, 3rd IEEE Multi-conference on Systems and Control (MSC’09), pp. 302-307, Saint Petersburg, RUSSIAN FED, 8 au 10 juillet 2009
 
15 Fesquet L., Beyrouthy T., A secure asynchronous configurable cell: an embedded programmable logic for smartcards, Workshop on Cryptographic Architectures embedded in reconfigurable devices (CryptArchi’08), Tregastel, FRANCE, 1 au 4 juin 2008
 
16 Borrione D., Liu Z.W., Morin-Allory K., Ostier P., Fesquet L., On-Line Assertion-Based Verification with Proven Correct Monitors, 3rd IEEE International Conference on Information and Communication Technology (ICICT'05), Cairo, EGYPT, 5 au 6 décembre 2005
 
17 Renaudin M., Bouesse G.F., Monnet Y., Fesquet L., Secure asynchronous circuits design and prototyping, 3rd International Workshop on Cryptographic Architectures Embedded in Reconfigurable Devices (CryptArchi’05), Saint-Etienne, FRANCE, 8 au 11 juin 2005
 
18 Thai-Ho Quoc, Rigaud J.B., Fesquet L., Renaudin M., Rolland R., Implementing asynchronous circuits on LUT based FPGAs, 12th International Conference on Field Programmable Logic and Applications (FPL'02), pp. 36-46, Montpellier, FRANCE, 2 au 4 septembre 2002
 
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143 Conférences internationales

  1 Skaf A., Ezzadeen M., Benabdenbi M., Fesquet L., Adjustable Precision Computing Using Redundant Arithmetic, Workshop on Approximate Computing (AxC'2019), Florence, ITALY, 29 mars 2019
 
  2 Turko T., Uhring W., Dadouche F., Fesquet L., An Asynchronous Fixed Priority Arbiter for High Throughput Time Correlated Single Photon Counting Systems, IEEE International Conference on Electronics Circuits and Systems (ICECS'2018), Bordeaux, FRANCE, 9 au 12 décembre 2018
 
  3 Elissati O., El Hadbi A., Cherkaoui A., Rieubon S., Fesquet L., Low Phase-Noise CMOS Quadrature Oscillator based on (Nx4)-stage Self-Timed Ring, Conference on Design of Circuits and Integrated Systems (DCIS'2018), Lyon, FRANCE, 14 au 16 novembre 2018
 
  4 Ferreira De Paiva Leite T., Fesquet L., Possamai Bastos R., A body built-in cell for detecting transient faults and dynamically biasing subcircuits of integrated systems, European Symposium on Reliability of Electron Devices, Failure Physics and Analysis (ESREF'2018), Aalborg, DENMARK, 1 au 5 octobre 2018
 
  5 Bonnaud O., Fesquet L., The practice in microelectronics: a mandatory complement of the online courses in the context of digital society, Symposium on Microelectronics Technology and Devices (SBMICRO'2018), Bento Gonçalves, BRAZIL, 27 au 31 août 2018
 
  6 Frisch R., Faix M., Mazer E., Fesquet L., Cognitive stochastic machine based on Bayesian inference: a behavioral analysis, IEEE International Conference Series on Cognitive Informatics and Cognitive Computing (ICCI*CC'2018), Berkeley, UNITED STATES, 15 au 18 juillet 2018
 
  7 Bonnaud O., Fesquet L., Innovation for education on Internet of things, International Conference on Advanced Technology Innovation (ICATI'2018), Krabi, THAILAND, 27 au 30 juin 2018
 
  8 Iga R., Possamai Bastos R., Ferreira De Paiva Leite T., Rolloff O., Mamadou D., Fesquet L., Level Shifter Architecture for Dynamically Biasing Ultra-Low Voltage Subcircuits of Integrated Systems, IEEE International Symposium on Circuits and Systems (ISCAS'2018), Florence, ITALY, 27 au 30 mai 2018
 
  9 Fesquet L., Bidegaray-Fesquet B., Infinite Impulse Response Filters for Nonuniform Data, International Conference on Advances in Signal, Image and Video Processing (SIGNAL'2018), Nice, FRANCE, 20 au 24 mai 2018
 
 10 Germain S., Engels S., Fesquet L., Shaping Electromagnetic Emissions of Event-Driven Circuits Thanks to Genetic Algorithms, International Conference on Advances in Signal, Image and Video Processing (SIGNAL'2018), Nice, FRANCE, 20 au 24 mai 2018
 
 11 Germain S., Engels S., Fesquet L., A Design Flow for Shaping Electromagnetic Emissions in Micropipeline Circuits, IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC'2018), Wien, AUSTRIA, 13 au 16 mai 2018
 
 12 Gimenez G., Cherkaoui A., Cogniard G., Fesquet L., Static Timing Analysis of Asynchronous Bundled-data Circuits, IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC'2018), Wien, AUSTRIA, 13 au 16 mai 2018
 
 13 Cherkaoui A., Coustans M., Fesquet L., Terrier C., Salgado S., Eberhardt T., Kayal M., Subthreshold Logic for Low-Area and Energy Efficient True Random Number, 21st IEEE Symposium on Low-Power and High-Speed Chips and Systems (COOL Chips'2018), Yokohama, JAPAN, 18 au 20 avril 2018
 
 14 Possamai Bastos R., Ferreira De Paiva Leite T., Fesquet L., Acunha Guimaraes L., Non-Intrusive Testing Technique for Detection of Trojans in Asynchronous Circuits, Design, Automation and Test in Europe (DATE'2018), Dresden, GERMANY, 19 au 23 mars 2018
 
 15 Bertrand Fra., Simatic J., Cherkaoui A., Maure A., Fesquet L., CAR: on the highway towards desynchronization, 24th IEEE International Conference on Electronics, Circuits and Systems (ICECS 2017), Batumi, GEORGIA, 5 au 8 décembre 2017
 
 16 Frisch R., Laurent R., Faix M., Girin L., Fesquet L., Lux A., Droulez J., Bessière P., Mazer E., A Bayesian stochastic machine for sound source localization, IEEE International Conference on Rebooting Computing (ICRC 2017), pp. 1-8, Washington DC, UNITED STATES, 7 au 9 novembre 2017
 
 17 Coustans M., Terrier C., Eberhardt T., Salgado S., Cherkaoui A., Fesquet L., A Subthreshold 30pJ/bit Self-timed Ring Based True Random Number Generator for Internet of Everything, IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (IEEE S3S), Washington DC, UNITED STATES, 16 au 19 octobre 2017
 
 18 Kalsing A., Fesquet L., Aktouf C., An Innovative Methodology to Check Consistency Between HDL and UPF Descriptions, Forum on Specification & Design Languages (FDL 2017), Verona, ITALY, 18 au 20 septembre 2017
 
 19 Ayres A., Rozeau O., Borot B., Fesquet L., Cibrario G., Vinet M., Back-end Limitations in Advanced Nodes and Alternatives, International Conference on Simulation of Semiconductor Processes and Devices (SISPAD'2017), Kamakura, JAPAN, 7 au 9 septembre 2017
 
 20 El Hadbi A., Cherkaoui A., Elissati O., Fesquet L., High Precision Time Measurement using Self-Timed Ring Oscillator based TDC, European Frequency and Time Forum & International Frequency Control Symposium (EFTF 2017), Besançon, FRANCE, 10 au 13 juillet 2017
 
 21 Acunha Guimaraes L., Possamai Bastos R., Fesquet L., Detection of Layout-Level Trojans by Monitoring Substrate with Preexisting Built-in Sensors, IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2017), pp. 290-295, Bochum, GERMANY, DOI: 10.1109/ISVLSI.2017.58, 3 au 5 juillet 2017
 
 22 Gimenez G., Cherkaoui A., Frisch R., Fesquet L., Self-timed Ring based True Random Number Generator: Threat model and countermeasures, IEEE 2nd International Verification and Security Workshop (IVSW 2017), pp. 31-38, Thessaloniki, GREECE, DOI: 10.1109/IVSW.2017.8031541, 3 au 5 juillet 2017
 
 23 El Hadbi A., Cherkaoui A., Elissati O., Simatic J., Fesquet L., On-the-fly and sub-gate-delay resolution TDC based on self-timed ring: A proof of concept, 15th IEEE International New Circuits and Systems Conference (NEWCAS 2017), pp. 305-308, Strasbourg, FRANCE, DOI: 10.1109/NEWCAS.2017.8010166, 25 au 28 juin 2017
 
 24 Acunha Guimaraes L., Possamai Bastos R., Fesquet L., Detection of Layout-Level Trojans by Injecting Current Into Substrate and Digitally Monitoring Built-In Sensors, Design Automation Conference (DAC 2017), Austin, TX, UNITED STATES, 18 au 22 juin 2017
 
 25 Bonnaud O., Bsiesy Ah., Fesquet L., Pradarelli B., IDEFI-FINMINA: a French educative project for the awareness, innovation and multidisciplinarity in microelectronics, 27th European Association for Education in Electrical and Information Engineering Annual Conference (EAEEIE'2017), Grenoble, FRANCE, 7 au 9 juin 2017
 
 26 Skaf A., Simatic J., Fesquet L., Seeking Low-power Synchronous/Asynchronous Systems: A FIR Implementation Case Study, IEEE International Symposium on Circuits and Systems (ISCAS 2017), pp. 1-4, Baltimore, MD, UNITED STATES, DOI: 10.1109/ISCAS.2017.8050379, 28 au 31 mai 2017
 
 27 Germain S., Engels S., Fesquet L., Event-Based Design Strategy for Circuit Electromagnetic Compatibility, 3rd International Conference on Event-Based Control, Communication and Signal Processing (EBCCSP 2017), pp. 1-7, Funchal, PORTUGAL, DOI: 10.1109/EBCCSP.2017.8022808, 24 au 26 mai 2017
 
 28 Darwish A., Abbass H., Fesquet L., Sicard G., Event-driven Image Sensor Application: Event-driven Image Segmentation, 3rd International Conference on Event Based Control, Communication and Signal Processing (EBCCSP 2017), pp. 1-6, Funchal, PORTUGAL, DOI: 10.1109/EBCCSP.2017.8022820, 24 au 26 mai 2017
 
 29 Fesquet L., Simatic J., Darwish A., Cherkaoui A., From events to data-driven processing, 3rd International Conference on Event-Based Control, Communication and Signal Processing (EBCCSP 2017), Funchal, PORTUGAL, 24 au 26 mai 2017
 
 30 Qaisar S.-M., Simatic J., Fesquet L., High Level Synthesis of an Event-Driven Windowing Process, 3rd International Conference on Event-Based Control, Communication and Signal Processing (EBCCSP 2017), pp. 1-8, Funchal, PORTUGAL, DOI: 10.1109/EBCCSP.2017.8022807, 24 au 26 mai 2017
 
 31 Simatic J., Cherkaoui A., Bertrand Fra., Possamai Bastos R., Fesquet L., A practical framework for specification, verification and design of self-timed pipelines, 23rd IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC 2017), San Diego, Ca, UNITED STATES, 21 au 24 mai 2017
 
 32 Bonnaud O., Fesquet L., Innovative practice in the French microelectronics education targeting the industrial needs, IEEE International Conference on Microelectronic Systems Education (MSE 2017), pp. 15-18, Banff, CANADA, DOI: 10.1109/MSE.2017.7945075, 11 au 12 mai 2017
 
 33 Ferreira De Paiva Leite T., Possamai Bastos R., Iga R., Fesquet L., Comparison of Low-Voltage Scaling in Synchronous and Asynchronous FD-SOI Circuits, 26th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS'16), Bremen, GERMANY, 21 au 23 septembre 2016
 
 34 Ayres A., Rozeau O., Borot B., Fesquet L., Vinet M., Delay partitioning helps reducing variability in 3DVLSI, 42nd European Solid-State Circuits Conference (ESSCIRC'16), Lausanne, SWITZERLAND, 12 au 15 septembre 2016
 
 35 Bonnaud O., Fesquet L., MOOC and Practices in electrical and information engineering: complementary approaches, 15th International Conference on Information Technology Based Higher Education and Training (ITHET'16), Istambul, TURKEY, 8 au 10 septembre 2016
 
 36 Bonnaud O., Fesquet L., Innovation in Higher Education: specificity of the microelectronics field, 31st Symposium on Microelectronics Technology and Devices (SBMicro'2016), Belo Horizonte, BRAZIL, 29 août au 3 septembre 2016
 
 37 Simatic J., Cherkaoui A., Possamai Bastos R., Fesquet L., New asynchronous protocols for enhancing area and throughput in bundle-data pipelines, 29th Symposium on Integrated Circuits and Systems Design (SBCCI'16), Belo Horizonte, BRAZIL, 29 août au 3 septembre 2016
 
 38 Beyrouthy T., Rushdy A., Salman M., Qaisar S.-M., Fesquet L., Asynchronous Implementation of an Event-Driven Adaptive Filter, 2nd International Conference on Event-Based Control, Communication and Signal Processing (EBCCSP'16) - Work-in-Progress, Krakow, POLAND, 13 au 15 juin 2016
 
 39 Simatic J., Possamai Bastos R., Fesquet L., High-Level Synthesis for Event-based Systems, 2nd International Conference on Event-Based Control, Communication and Signal Processing (EBCCSP'16), Krakow, POLAND, 13 au 15 juin 2016
 
 40 Bidegaray-Fesquet B., Fesquet L., Levels, peaks, slopes... which sampling for which purpose?, 2nd International Conference on Event-Based Control, Communication and Signal Processing (EBCCSP'16), Krakow, POLAND, 13 au 15 juin 2016
 
 41 Bonnaud O., Fesquet L., Practice in microelectronics education as a mandatory supplement to the future digital-based pedagogy: strategy of the French national network, 11th European Workshop on Microelectronics Education (EWME'16), pp. 1-6, Southampton, ENGLAND, DOI: 10.1109/EWME.2016.7496460, 11 au 13 mai 2016
 
 42 Acunha Guimaraes L., Possamai Bastos R., Ferreira De Paiva Leite T., Fesquet L., Simple Tri-State Logic Trojans Able to Upset Properties of Ring Oscillators, 11th International Conference on Design &Technology of Integrated Systems in Nanoscale Era (DTIS'16), pp. 1-6, Istanbul, TURKEY, DOI: 10.1109/DTIS.2016.7483811, 12 au 14 avril 2016
 
 43 Simatic J., Possamai Bastos R., Fesquet L., AHLS_DESYNC: A Desynchronization Tool For High-Level Synthesis of Asynchronous Circuits, Design, Automation and Test in Europe (DATE'16) - University Booth, Dresden, GERMANY, 14 au 18 mars 2016
 
 44 Darwish A., Rocha L., Fesquet L., Sicard G., Design of a Fully Asynchronous Image Sensor Reading, Conference on Design of Circuits and Integrated Systems (DCIS'15), Estoril, PORTUGAL, 25 au 27 novembre 2015
 
 45 Al Khatib C., Aupetit C., Chevalier C., Aktouf C., Sicard G., Fesquet L., A Generic Clock Controller for Low Power Systems: Experimentation on an AXI Bus, IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC'15) , Daejeon, KOREA, 5 au 7 octobre 2015
 
 46 Rolloff O., Possamai Bastos R., Fesquet L., Exploiting reliable features of asynchronous circuits for designing low-voltage components in FD-SOI technology, 26th European Symposium on Reliability of Electron Devices, Failure Physics and Analysis (ESREF'15), Toulouse, FRANCE, 5 au 9 octobre 2015
 
 47 Ayres A., Rozeau O., Borot B., Fesquet L., Cibrario G., Batude P., Vinet M., Guidelines on 3D VLSI design regarding the intermediate BEOL process influence, IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), pp. 1-2, Sonoma Valley, CA, UNITED STATES, DOI: 10.1109/S3S.2015.7333540, 5 au 8 octobre 2015
 
 48 Arslan C., Poujaud J., Fesquet L., A method to automatically determine the Level-Crossing thresholds in non-uniform sampling and Processing, 1st IEEE International Conference on Event-Based Control, Communication and Signal Processing (EBCCSP'15), Krakow, POLAND, 17 au 19 juin 2015
 
 49 Beyrouthy T., Fesquet L., Rolland B., Data Sampling and Processing: Uniform vs. Non-Uniform Schemes, 1st IEEE International Conference on Event-Based Control, Communication and Signal Processing (EBCCSP'15), Krakow, POLAND, 17 au 19 juin 2015
 
 50 Darwish A., Fesquet L., Sicard G., RTL Simulation of an Asynchronous Reading Architecture for an Event-driven Image Sensor, 1st IEEE International Conference on Event-Based Control, Communication and Signal Processing (EBCCSP'15), Krakow, POLAND, 17 au 19 juin 2015
 
 51 Bonnaud O., Fesquet L., Communicating and Smart Objects: multidisciplinary topics for the innovative education in microelectronics and its applications, 14th International Conference on Information Technology Based Higher Education and Training (ITHET'15), pp. 1-5, Lisbon, PORTUGAL, DOI: 10.1109/ITHET.2015.7217961, 11 au 13 juin 2015
 
 52 Simatic J., Fesquet L., Bidegaray-Fesquet B., Correctly Sizing FIR Filter Architecture in the Framework of Non-uniform Sampling, 11th International Conference on Sampling Theory and Applications (SampTA'15) , pp. 269-273, Washington, DC, UNITED STATES, DOI: 10.1109/SAMPTA.2015.7148894 , 25 au 29 mai 2015
 
 53 Fesquet L., Darwish A., Sicard G., Sampling circuits for 1D and 2D sensors for low-power purpose, 11th International Conference on Sampling Theory and Applications (SampTA'15) , pp. 430-434, Washington, DC, UNITED STATES, DOI: 10.1109/SAMPTA.2015.7148927, 25 au 29 mai 2015
 
 54 Bonnaud O., Fesquet L., Towards multidisciplinarity for microelectronics education: a strategy of the French national network, International Conference on Microelectronic Systems Education (MSE'15), pp. 1-4, Pittsburgh, PA, UNITED STATES, DOI: 10.1109/MSE.2015.7160004, 20 au 21 mai 2015
 
 55 Cherkaoui A., Fesquet L., Fischer V., Aubert A., A Self-timed Ring based True Random Number Generator with Monitoring and Entropy Assessment, University Booth at DATE 2015, pp. session UB02.1, Grenoble, FRANCE, 10 au 12 mars 2015
 
 56 Al Khatib C., Aupetit C., Chagoya A., Chevalier C., Sicard G., Fesquet L., Distributed Asynchronous Controllers for Clock Management in Low Power Systems, 21st IEEE International Conference on Electronics Circuits and Systems (ICECS'14), pp. 379-382, Marseille, FRANCE, DOI: 10.1109/ICECS.2014.7050001 , 7 au 10 décembre 2014
 
 57 Bonnaud O., Nouet P., Fesquet L., Tayeb M.-B, FINMINA: a French national project to promote Innovation in Higher Education in Microelectronics and Nanotechnologies, International Conference on Information Technology Based Higher Education and Training (ITHET'14), pp. 1-8, York, ENGLAND, 11 au 13 septembre 2014
 
 58 Bonnaud O., Fesquet L., A Prospective on Education of New Generations of devices in the FDSOI and FinFET Technologies: from the technological process to the Circuit Design Specifications, 29th Symposium on Microeletronics Technology and Devices (SBMicro'14), pp. 1-4, Aracaju, Sergipe, BRAZIL, DOI: 10.1109/SBMicro.2014.6940081, 1 au 5 septembre 2014
 
 59 Roa Osorio G., Le Pelleter T., Bonvilain A., Chagoya A., Fesquet L., Designing ultra-low power systems with non-uniform sampling and event-driven logic, 27th Symposium on Integrated Circuits and Systems Design (SBCCI'14), pp. 1-6, Aracaju, Sergipe, BRAZIL, DOI: 10.1145/2660540.2660973, 1 au 5 septembre 2014
 
 60 Darwish A., Fesquet L., Sicard G., 1-level Crossing Sampling Scheme for Low Data Rate Image Sensors, 12th IEEE International New Circuits and Systems Conference (NEWCAS'14), pp. 289-292, Trois-Rivières, CANADA, DOI: 10.1109/NEWCAS.2014.6934039, 22 au 25 juin 2014
 
 61 Fesquet L., Cherkaoui A., Elissati O., Self-timed rings as low-phase noise programmable oscillators, 12th IEEE International New Circuits and Systems Conference (NEWCAS'14), pp. 409 - 412 , Trois-Rivières, CANADA, DOI: 10.1109/NEWCAS.2014.6934069, 22 au 25 juin 2014
 
 62 Bonnaud O., Salaün A-C, Bsiesy Ah., Fesquet L., Improvement of doctoral studies in Electrical and Information Engineering through the High level courses in Europe, 25th EAEEIE Annual Conference, Cesme, Izmir, TURKEY, 30 mai au 1 juin 2014
 
 63 Bonnaud O., Fesquet L., Trends in Nanoelectronic Education: From FDSOI and FinFET Technologies to Circuit Design Specifications, The 10th European Workshop on Microelectronics Education (EWME 2014), pp. 106 - 111 , Tallinn, ESTONIA, DOI: 10.1109/EWME.2014.6877406, 14 au 16 mai 2014
 
 64 Faix M., Mazer E., Fesquet L., An asynchronous CMOS probabilistic computer Idea, 20th International Symposium on Asynchronous Circuits and Systems (ASYNC'14), Postdam, GERMANY, 12 au 14 mai 2014
 
 65 Darwish A., Sicard G., Fesquet L., Low data rate architecture for smart image sensor , Image Sensors and Imaging Systems, pp. 9022-9025, San Francisco, California, UNITED STATES, 5 au 6 février 2014
 
 66 Bonnaud O., Fesquet L., The new strategy based on Innovative Projects in Microelectronics and Nanotechnologies, Symposium on Microelectronics Technology and Devices (SBMicro'13), pp. 1-7, Curitiba, BRAZIL, DOI: 10.1109/SBMicro.2013.6676183, 2 au 6 septembre 2013
 
 67 Cherkaoui A., Fischer V., Aubert A., Fesquet L., A Very High Speed True Random Number Generator with Entropy Assessment, Workshop on Cryptographic Hardware and Embedded Systems (CHES'13), pp. 179-196, Santa Barbara, Ca, UNITED STATES, 18 au 22 août 2013
 
 68 Sliwinski P., Berezowski K., Wachel P., Sicard G., Fesquet L., Empirical recovery of input nonlinearity in distributed element models, International Workshop on Adaptation and Learning in Control and Signal Processing (ALCOSP'13), pp. 617-622, Caen, FRANCE, DOI: 10.3182/20130703-3-FR-4038.00092, 3 au 5 juillet 2013
 
 69 Le Pelleter T., Beyrouthy T., Rolland B., Bonvilain A., Fesquet L., Non-uniform sampling pattern recognition based on atomic decomposition, International Conference on Sampling Theory and Applications (SampTA'13), Bremen, GERMANY, 1 au 5 juillet 2013
 
 70 Bonnaud O., Fesquet L., Innovating projects as a pedagogical strategy for the French network for education in microelectronics and nanotechnologies, International Conference on Microelectronic Systems Education (MSE'13), pp. 5-8, Austin, Texas, UNITED STATES, DOI: 10.1109/MSE.2013.6566690, 2 au 3 juin 2013
 
 71 Cherkaoui A., Fischer V., Aubert A., Fesquet L., A Self-timed Ring Based True Random Number Generator, 19th International Symposium on Asynchronous Circuits and Systems (ASYNC'13), pp. 99-106, Santa Monica, UNITED STATES, 19 au 22 mai 2013
 
 72 Yahya E., Fesquet L., Ismail Y., Renaudin M., Statistical Static Timing Analysis of Conditional Asynchronous Circuits Using Model-Based Simulation, 19th International Symposium on Asynchronous Circuits and Systems (ASYNC'13), pp. 67-74, Santa Monica, UNITED STATES, 19 au 22 mai 2013
 
 73 Le Pelleter T., Beyrouthy T., Leroy Y., Bonvilain A., Rolland R., Fesquet L., Low-power signal processing platform based on non-uniform sampling and event-driven circuitry, Design, Automation and Test in Europe (DATE'13), Grenoble, FRANCE, 18 au 22 mars 2013
 
 74 Paugnat F., Fesquet L., Morin-Allory K., Model of a Simple yet effective Operational Amplifier, International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD'12), pp. 165-168, Seville, SPAIN, DOI: 10.1109/SMACD.2012.6339443 , 19 au 21 septembre 2012
 
 75 Excoffon E., Papillon F., Fesquet L., Bsiesy Ah., Bonnaud O., New pedagogical experiment leading to awareness in nanosciences and nanotechnologies for young generations at secondary school , International Conference on Information Technology Based Higher Education and Training (ITHET'12), pp. 1 - 4 , Istanbul, TURKEY, DOI: 10.1109/ITHET.2012.6246049, 21 au 23 juin 2012
 
 76 Cherkaoui A., Fischer V., Fesquet L., Aubert A., A New Robust True Random Numbers Generator Using Self-Timed Rings, Workshop on Cryptographic architectures embedded in reconfigurable devices (Cryptarchi'12), Marcoux, FRANCE, 19 au 22 juin 2012
 
 77 Cherkaoui A., Fesquet L., Fischer V., Aubert A., Self-Timed Rings as Entropy Sources, 18th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC'12), Copenhagen, DENMARK, 7 au 9 mai 2012
 
 78 Cherkaoui A., Fischer V., Aubert A., Fesquet L., Comparison of Self-Timed Ring and Inverter Ring Oscillators as Entropy Sources in FPGAs, Design Automation and Test in Europe (DATE'12), pp. 1-6, Dresden, GERMANY, 12 au 16 mars 2012
 
 79 Ouchet F., Morin-Allory K., Fesquet L., C-elements for hardened self-timed circuits, 21st International Workshop Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation (PATMOS'11), pp. 247-256, Madrid, SPAIN, DOI: 10.1007/978-3-642-24154-3_25, 26 au 29 septembre 2011
 
 80 Porcher A., Morin-Allory K., Fesquet L., Does Asynchronous technology bring robustness in synchronous circuit monitoring?, Forum on specification & Design Languages (FDL’11), Oldenburg, GERMANY, 13 au 15 septembre 2011
 
 81 Porcher A., Morin-Allory K., Fesquet L., Synthesis of Quasi Delay Insensitive Monitors, 7th Conference on PhD Research in Microelectronics and Electronics (PRIME’11), pp. 225 - 228 , Trento, ITALY, DOI: 10.1109/PRIME.2011.5966274 , 3 au 7 juillet 2011
 
 82 Alsayeg K., Fesquet L., Sicard G., Renaudin M., A modular synthesis method for low-power QDI state machines , 9th IEEE International NEWCAS Conference, pp. 185 - 188 , Bordeaux, FRANCE, DOI: 10.1109/NEWCAS.2011.5981286 , 26 au 29 juin 2011
 
 83 Paugnat F., Morin-Allory K., Fesquet L., A refinement process for top-down mixed-signal designs thanks to SystemC-AMS , IEEE 9th International New Circuits and Systems Conference (NEWCAS'11), pp. 378 - 381 , Bordeaux, FRANCE, DOI: 10.1109/NEWCAS.2011.5981249 , 26 au 29 juin 2011
 
 84 Hamon J., Fesquet L., Configurable Self-Timed Ring Oscillators, 9th IEEE International NEWCAS Conference, pp. 249 - 252 , Bordeaux, FRANCE, DOI: 10.1109/NEWCAS.2011.5981302 , 26 au 29 juin 2011
 
 85 Zakaria H., Fesquet L., Process variability robust energy-efficient control for nano-scaled complex SoCs , Faible Tension Faible Consommation (FTFC’11), pp. 95 - 98 , Marrakech, MOROCCO, DOI: 10.1109/FTFC.2011.5948928 , 30 mai au 1 juin 2011
 
 86 Elissati O., Rieubon S., Fesquet L., Ring Oscillators : The Asynchronous Alternative, Faible Tension Faible Consommation (FTFC’11), pp. 27-30, Marrakech, MOROCCO, DOI: 10.1109/FTFC.2011.5948910 , 30 mai au 1 juin 2011
 
 87 Beyrouthy T., Fesquet L., An event-driven FIR filter: Design and implementation , 22nd IEEE International Symposium on Rapid System Prototyping (RSP'11), pp. 59 - 65 , Karlsruhe, GERMANY, DOI: 10.1109/RSP.2011.5929976 , 24 au 27 mai 2011
 
 88 Beyrouthy T., Fesquet L., Greitans M., Shavelis R., Rolland-Girod R., An Asynchronous FIR Filter Architecture coupled to a Level-Crossing ADC, 9th International Conference on Sampling Theory and Applications (SampTA'11), pp. Fr2S12.2 - P0190, Singapore, SINGAPORE, 2 au 6 mai 2011
 
 89 Greitans M., Shavelis R., Fesquet L., Beyrouthy T., Combined Peak and Level-Crossing Sampling Scheme, 9th International Conference on Sampling Theory and Applications (SampTA'11), pp. Fr2S12.1 - P0158, Singapore, SINGAPORE, 2 au 6 mai 2011
 
 90 Bidegaray-Fesquet B., Fesquet L., Non-Uniform Filter Design in the Log-Scale, 9th International Conference on Sampling Theory and Applications (SampTA'11), Singapore, SINGAPORE, 2 au 6 mai 2011
 
 91 Yan C., Ouchet F., Fesquet L., Morin-Allory K., Formal Verification of C-element Circuits, IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC’11), pp. 55 - 64 , Ithaca (NY), UNITED STATES, DOI: 10.1109/ASYNC.2011.14 , 27 au 29 avril 2011
 
 92 Elissati O., Yahya E., Fesquet L., Rieubon S., A novel High-Speed Multi-Phase Oscillator on Asynchronous Rings, IEEE International Conference on Microelectronics (ICM’10), pp. 204-207, Cairo, EGYPT, DOI: 10.1109/ICM.2010.5696117, 19 au 22 décembre 2010
 
 93 Elissati O., Yahya E., Rieubon S., Fesquet L., A High-Speed High-Resolution Low-Phase Noise Oscillator Using Self-Timed Rings, 18th IEEE/IFIP International Conference on VLSI and System-on-Chip (VLSI-SoC'10), pp. 173-178, Madrid, SPAIN, DOI: 10.1109/VLSISOC.2010.5642600, 27 au 29 septembre 2010
 
 94 Elissati O., Yahya E., Rieubon S., Fesquet L., Optimizing and Comparing CMOS Implementations of the C-element in 65nm technology: Self-Timed Ring Case, International Workshop on Power And Timing Modeling, Optimization and Simulation (PATMOS'10), Grenoble, FRANCE, 7 au 10 septembre 2010
 
 95 Fesquet L., Sicard G., Bidegaray-Fesquet B., Targeting ultra-low power consumption with non-uniform sampling and filtering, IEEE International Symposium on Circuits and Systems (ISCAS’10), pp. 3585 - 3588 , Paris, FRANCE, DOI: 10.1109/ISCAS.2010.5537804 , 30 mai au 2 juin 2010
 
 96 Zakaria H., Durand S., Marchand N., Fesquet L., Integrated Asynchronous Regulation for Nanometric Technologies, 1st IEEE European workshop on CMOS Variability (VARI'10), pp. 86-91 , Montpellier, FRANCE, 26 au 27 mai 2010
 
 97 Ouchet F., Morin-Allory K., Fesquet L., Delay Insensitivity Does Not Mean Slope Insensitivity!, IEEE Symposium on Asynchronous Circuits and Systems (ASYNC'10), pp. 176 - 184 , Grenoble, FRANCE, DOI: 10.1109/ASYNC.2010.27 , 3 au 6 mai 2010
 
 98 Porcher A., Morin-Allory K., Fesquet L., Synthesis of asynchronous monitors for critical electronic systems, IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS’10), pp. 329 - 334 , Vienna, AUSTRIA, DOI: 10.1109/DDECS.2010.5491756 , 14 au 16 avril 2010
 
 99 Yahya E., Fesquet L., Asynchronous Design: A Promising Paradigm for Electronic Circuits and Systems, IEEE International Conference on Electronics and Systems (ICECS’09), pp. 339 - 342 , Hammamet, TUNISIA, DOI: 10.1109/ICECS.2009.5411009 , 13 au 16 décembre 2009
 
100 Guilley S., Chaudhuri S., Sauvage L., Danger J.-L., Beyrouthy T., Fesquet L., Updates on the Potential of Clock-Less Logics to Strengthen Cryptographic Circuits against Side-Channel Attacks, IEEE International Conference on Electronics and Systems (ICECS’09), pp. 351 - 354 , Hammamet, TUNISIA, DOI: 10.1109/ICECS.2009.5411008 , 13 au 16 décembre 2009
 
101 Alsayeg K., Morin-Allory K., Fesquet L., RAT-based formal verification of QDI asynchronous controllers, Forum on specifications and Design Languages (FDL’09), pp. 1-6, Nice Sophia-Antipolis, FRANCE, 22 au 24 septembre 2009
 
102 Alsayeg K., Fesquet L., Sicard G., Rios D., Renaudin M., Optimizing speed and consumption of QDI controllers using direct mapping synthesis, Joint 7th International IEEE Northeast Workshop on Circuits and Systems and TAISA Conference (NEWCAS-TAISA’09), pp. 151-154, Toulouse, FRANCE, 28 juin au 1 juillet 2009
 
103 Elissati O., Yahya E., Fesquet L., Rieubon S., Oscillation Period and Power Consumption in Configurable Self-Timed Rings Oscillators, Joint 7th International IEEE Northeast Workshop on Circuits and Systems and TAISA Conference (NEWCAS-TAISA’09), pp. 131-134, Toulouse, FRANCE, DOI: 10.1109/NEWCAS.2009.5290439 , 28 juin au 1 juillet 2009
 
104 Beyrouthy T., Fesquet L., DPA robust S-BOX implementation on a secure asynchronous FPGA, 7th International Workshop on Cryptographic Architectures Embedded in Reconfigurable Devices (Cryptarchi'09), Prague, CZECH REPUBLIC, 24 au 27 juin 2009
 
105 Yahya E., Elissati O., Zakaria H., Fesquet L., Renaudin M., Programmable/Stoppable Oscillator Based on Self-Timed Rings, 15th IEEE Symposium on Asynchronous Circuits and Systems (ASYNC '09) , pp. 3-12, Chapel Hill, NC , UNITED STATES, DOI: 10.1109/ASYNC.2009.12, 17 au 20 mai 2009
 
106 Bidegaray-Fesquet B., Fesquet L., A fully nonuniform approach to FIR filtering, Sampling Theory and Applications (SampTA’09), pp. 259-263, Marseille, FRANCE, 12 au 18 mai 2009
 
107 Qaisar S.-M., Fesquet L., Renaudin M., Effective Resolution of an Adaptive Rate ADC, 8th International Conference on Sampling Theory and Applications (SampTA’09), pp. 1-4, Marseille, FRANCE, 12 au 18 mai 2009
 
108 Beyrouthy T., Fesquet L., A secure asynchronous FPGA for an embedded system, PhD Forum DATE, Nice, FRANCE, 2 au 24 avril 2009
 
109 Hamon J., Miscopein B., Schwoerer J., Fesquet L., Renaudin M., Self-Timed Implementation of an Impulse Radio Synchronisation Acquisition Algorithm, Conference on Design and Architectures for Signal and Image Processing (DASIP’08), pp. 61-68, Bruxelles, BELGIUM, 24 au 26 novembre 2008
 
110 Beyrouthy T., Fesquet L., Razafindraibe A., Chaudhuri S., Guilley S., Hoogvorst P., Danger J.-L., Renaudin M., A Secure Programmable Architecture with a Dedicated Tech-mapping Algorithm: Application to a Crypto-Processor, 23rd International Conference on Design of Circuits and Integrated Systems (DCIS’08), Grenoble, FRANCE, 12 au 14 novembre 2008
 
111 Alsayeg K., Fesquet L., Sicard G., Rios D., Renaudin M., Synthesis of asynchronous QDI FSM based on optimized sequencers, 34th European Conference on Solid-States Circuits (ESSCIRC’08), Edinburgh, SCOTLAND, 16 septembre 2008
 
112 Qaisar S.-M., Fesquet L., Renaudin M., An improved quality filtering technique for time varying signals based on the level crossing sampling, International Conference of Signals and Electronic Systems (ICSES’08), pp. 355-358, Krakow, POLAND, 14 au 17 septembre 2008
 
113 Qaisar S.-M., Fesquet L., Renaudin M., An Improved Quality Adaptative Rate Filtering Technique Based on the Level Crossing Sampling, Computer Vision, Image and Signal Processing (CVISP’08), pp. 79-84, Prague, CZECH REPUBLIC, DOI: 10.1109/ICSES.2008.4673436, 25 au 27 juillet 2008
 
114 Qaisar S.-M., Fesquet L., Renaudin M., Computationally Efficient Adaptive Rate Sampling and Adaptive Resolution Analysis, Computer Vision, Image and Signal Processing (CVISP’08), pp. 85-90, Prague, CZECH REPUBLIC, 25 au 27 juillet 2008
 
115 Hamon J., Fesquet L., Miscopein B., Renaudin M., High-level time-accurate model for the design of self-timed ring oscillators, 14th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC’08), pp. 29-38, Newcastle upon Tyne, UNITED KINGDOM, 7 au 11 avril 2008
 
116 Beyrouthy T., Razafindraibe A., Fesquet L., Renaudin M., Hoogvorst P., Guilley S., Chaudhuri S., Danger J.-L., A novel asynchronous e-FPGA architecture for security applications, International Conference on Field-Programmable Technology (ICFPT'07), pp. 369-372, Kokurakita, Kitakyushu, JAPAN, 12 au 14 décembre 2007
 
117 Morin-Allory K., Fesquet L., Borrione D., Asynchronous online monitoring of logical and temporal assertions, 10th Forum on Specification and Design Languages (FDL'07), Barcelona, SPAIN, 18 au 20 septembre 2007
 
118 Qaisar S.-M., Fesquet L., Renaudin M., Computationally Efficient Adaptive Rate Sampling and Filtering, 15th European Signal Processing Conference (EUSIPCO’07), pp. 2139-2143, Poznan, POLAND, 3 au 7 septembre 2007
 
119 Hoogvorst P., Guilley S., Razafindraibe A., Beyrouthy T., Fesquet L., A Reconfigurable Cell for a Multi-Style Asynchronous FPGA, Reconfigurable Communication-centric SoC (RecoSoC’07), pp. 15-22, Montpellier, FRANCE, 18 au 20 juin 2007
 
120 Qaisar S.-M., Fesquet L., Renaudin M., Adaptive Rate Sampling and Filtering for Low Power Embedded Systems, Sampling Theory and Applications (SampTA’07), Thessaloniki, GREECE, 1 au 5 juin 2007
 
121 Qaisar S.-M., Fesquet L., Renaudin M., Adaptive Rate Filtering for a Signal Driven Sampling Scheme, 32nd IEEE International Conference on Acoustics, Speech, and Signal Processing (ICASSP’07), pp. III-1465 - III-1468 , Honolulu, Hawaï, UNITED STATES, DOI: 10.1109/ICASSP.2007.367124 , 15 au 20 avril 2007
 
122 Fesquet L., Folco B., Steiner M., Renaudin M., State-holding in Look-Up Tables: application to asynchronous logic, 14th IFIP International Conference on Very Larage Scale Integration (VLSI-SoC’06), pp. 12-18, Nice, FRANCE, 16 au 18 octobre 2006
 
123 Qaisar S.-M., Fesquet L., Renaudin M., Spectral analysis of a signal driven sampling scheme, 14th European Signal Processing Conference (EUSIPCO’06), pp. 1-5, Florence, ITALY, 4 au 8 septembre 2006
 
124 Morin-Allory K., Fesquet L., Borrione D., Asynchronous Assertion Monitors for multi-Clock Domain System Verification, 17th IEEE Symposium on Rapid System Prototyping (RSP'06), pp. 98- 102, Chania, GREECE, DOI: 10.1109/RSP.2006.9 , 14 au 16 juin 2006
 
125 Morin-Allory K., Fesquet L., Borrione D., Asynchronous on-line monitoring of PSL assertions, 17th IEEE Symposium on Rapid System Prototyping (RSP'06), pp. 98-102, Chania, GREECE, DOI: 10.1109/RSP.2006.9, 14 au 16 juin 2006
 
126 Quartana J., Fesquet L., Renaudin M., Modular Asynchronous Network-on-Chip: Application to GALS Systems Rapid Prototyping, 15th IFIP International Conference on Very Large Scale Integration Systems (VLSI-SoC'05), pp. 397-402, Perth, AUSTRALIA, 17 au 19 octobre 2005
 
127 Folco B., Bregier V., Fesquet L., Renaudin M., Technology Mapping for Area Optimized Quasi Delay Insensitive Circuits, 15th IFIP International Conference on Very Large Scale Integration Systems (VLSI-SoC'05), Perth, AUSTRALIA, 17 au 19 octobre 2005
 
128 Borrione D., Liu M., Ostier P., Fesquet L., PSL-based online monitoring of digital systems, Forum on specification and Design Languages (FDL'05), pp. 465-478, Lausanne, SWITZERLAND, 27 au 30 septembre 2005
 
129 Fesquet L., Renaudin M., A programmable logic architecture for prototyping clockless circuits, 15th International Conference on Field Programmable Logic & Applications (FPL'05), pp. 293- 298, Tampere, FINLAND, DOI: 10.1109/FPL.2005.1515737, 24 au 26 août 2005
 
130 Fesquet L., Quartana J., Renaudin M., Renane S., Baixas A., GALS systems prototyping using multiclock fpgas and asynchronous network-on-chips, International Conference on Field Programmable Logic and Applications (FPL'05), pp. 299-304, Tampere, FINLAND, DOI: 10.1109/FPL.2005.1515738, 24 au 26 août 2005
 
131 Aeschlimann F., Allier E., Fesquet L., Renaudin M., Spectral analysis of level crossing sampling scheme, International Workshop on Sampling theory and application (SAMPTA'05), Samsun, TURKEY, 10 au 15 juillet 2005
 
132 Fesquet L., Quartana J., Renaudin M., Asynchronous Systems on Programmable Logic, Reconfigurable Communication-centric SoCs (ReCoSoC'05), pp. 105-112, Montpellier, FRANCE, 27 au 29 juin 2005
 
133 Huot N., Dubreuil H., Fesquet L., Renaudin M., FPGA architecture for multi-style asynchronous logic, Design Automation and Test in Europe Conference and Exhibition (DATE'05), pp. 32-33, Munich, GERMANY, DOI: 10.1109/DATE.2005.159 , 7 au 11 mars 2005
 
134 Huot N., Dubreuil H., Fesquet L., Renaudin M., FPGA architecture for multi-style asynchronous logic [full-adder example], Design, Automation and Test in Europe (DATE'05), pp. 32 - 33 , Munich, GERMANY, DOI: 10.1109/DATE.2005.15, 7 au 11 mars 2005
 
135 Bregier V., Folco B., Fesquet L., Renaudin M., Modeling and synthesis of multi-rail multi-protocol QDI circuits, Thirteenth International Workshop on Logic and Synthesis, Temecula Creek (IWLS'04), Temecula, California, UNITED STATES, 2 au 4 juin 2004
 
136 Aeschlimann F., Allier E., Fesquet L., Renaudin M., Asynchronous FIR filters: towards a new digital processing chain, 10th International Symposium on Asynchronous Circuits and Systems (ASYNC'04) , pp. 198-206, Hersonissos-Heraklion, Crete, GREECE, DOI: 10.1109/ASYNC.2004.1299302, 19 au 23 avril 2004
 
137 Sicard G., Renaudin M., Allier E., Fesquet L., Asynchronous ADCs: Design Methodology and Case study, 8th International Workshop on ADC modelling and testing (IWADC'03), pp. 29-32, Perugia, ITALY, 8 au 10 septembre 2003
 
138 Allier E., Sicard G., Fesquet L., Renaudin M., A new class of asynchronous A/D converters based on time quantization, Ninth International Symposium on Asynchronous Circuits and Systems (ASYNC'03), pp. 196-205, Vancouver, CANADA, DOI: 10.1109/ASYNC.2003.1199179, 12 au 15 mai 2003
 
139 Fesquet L., Dinh Duc Anh Vu, Renaudin M., Synthesis of QDI asynchronous circuits from DTL-style petri-net, 11th IEEE/ACM International Workshop on Logic & Synthesis (IWLS'02), New Orleans, Louisiana, UNITED STATES, 4 au 7 juin 2002
 
140 Rigaud J.B., Quartana J., Fesquet L., Renaudin M., High-level modeling and design of asynchronous arbiters for on-chip communication systems, Conference and Exhibition Design, Automation and Test in Europe (DATE'02), pp. 1530-1591, Paris, FRANCE, DOI: 10.1109/DATE.2002.998447, 4 au 8 mars 2002
 
141 Es Salhiene M., Fesquet L., Renaudin M., Dynamic voltage scheduling for real time asynchronous systems, 12th International Workshop on Integrated Circuit Design, Power and Timing Modeling, Optimization and Simulation (PATMOS'02), pp. 390-399, Sevilla, SPAIN, 1 janvier 2002
 
142 Allier E., Fesquet L., Renaudin M., Sicard G., Low-power asynchronous A/D conversion, 12th International Workshop on Integrated Circuit Design, Power and Timing Modeling, Optimization and Simulation (PATMOS'02), pp. 81-91, Sevilla, SPAIN, 1 janvier 2002
 
143 Fesquet L., Renaudin M., Rigaud J.B., Quartana J., Modeling and design of asynchronous priority arbiters for on-chip communication systems, IFIP International Conference On Very Large Scale Integration (VLSI-SOC'01), pp. 313-324, Montpellier, FRANCE, 3 au 5 décembre 2001
 
remonter

12 Chapitres de livre

 1 Kalsing A., Fesquet L., Aktouf C., A Methodology for Automated Consistency Checking Between Different Power-Aware Descriptions, Languages, Design Methods, and Tools for Electronic System Design, Daniel Große, Sara Vinco, Hiren Patel (Eds.) , Ed. Springer , pp. 107-127, Vol. 530, 2018
 
 2 Fesquet L., Bidegaray-Fesquet B., Digital Filtering with non-uniformly sampled data: from the algorithm to the implementation, Event-Based Control and Signal Processing, Marek Miskowicz (Eds.) , Ed. CRC Press, pp. , 2015
 
 3 Elissati O., Rieubon S., Yahya E., Fesquet L., Self-Timed Rings: A Promising Solution for Generating High-Speed High Resolution Low-Phase Noise Clocks, VLSI-SoC: Forward-Looking Trends in IC and Systems Design 18th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2010, Madrid, Spain, September 27-29, 2010, Revised Selected Papers, Ayala, Jose L.; Atienza Alonso, David; Reis, Ricardo (Eds.) , Ed. Springer , pp. 22-42, DOI: http://www.springer.com/computer/hardware/book/978-3-642-32769-8, 2012
 
 4 Zakaria H., Yahya E., Fesquet L., Self Adaption in SoCs, Autonomic Networking-on-Chip (Bio-inspired Specification, Development, and Verification), Phan Cong-Vinh (Eds.) , Ed. CRC Press, pp. 287p, DOI: http://www.crcpress.com/product/isbn/9781439829110;jsessionid=a20u7iABlgZrlao+61snZg**, 2011
 
 5 Elissati O., Yahya E., Fesquet L., Rieubon S., Optimizing and Comparing CMOS Implementations of the C-element in 65nm technology: Self-Timed Ring Case, Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation, 20th International Workshop, PATMOS 2010, Grenoble, France, September 7-10, 2010, van Leuken, Rene; Sicard, Gilles (Eds.) , Ed. Springer , pp. 137–149, DOI: http://www.springer.com/computer/communication+networks/book/978-3-642-17751-4?changeHeader, 2010
 
 6 Chaudhuri S., Guilley S., Hoogvorst P., Danger J.-L., Beyrouthy T., Razafindraibe A., Fesquet L., Renaudin M., Physical Design of FPGA Interconnect to Prevent Information Leakage, Reconfigurable Computing: Architecture, Tools, and Applications, Woods, R.; Compton, K.; Bourganis, C.; Diniz, P.C. (Eds.) , Ed. Springer , pp. 87-98, DOI: http://www.springerlink.com/content/j1863l117145px3v/, 2008
 
 7 Morin-Allory K., Fesquet L., Roustan B., Borrione D., Asynchronous online monitoring of logical and temporal assertions, Embedded Systems Specification and Design Languages, Villar Eugenio (Eds.) , Ed. Springer , pp. 278 p, 2008
 
 8 Quartana J., Fesquet L., Renaudin M., Modular asynchronous Network-on-Chip: application to GALS systems rapid prototyping, VLSI-SOC: From Systems to Chips, (selected contributions from VLSI-SoC 2005), Ed. Springer , pp. 195-207, DOI: DOI 10.1007/978-0-387-73661-7_13 , 2007
 
 9 Folco B., Bregier V., Fesquet L., Renaudin M., Technology mapping for area optimized quasi delay insensitive circuits, VLSI-SOC: From Systems to Silicon, Reis, Ricardo; Osseiran, Adam; Pfleiderer, Hans-Joerg (Eds.) , Ed. Springer , pp. 55-69, Vol. 240, DOI: DOI 10.1007/978-0-387-73661-7_5, 2007
 
10 Borrione D., Liu M., Ostier P., Fesquet L., PSL-based online monitoring of digital systems, Advances in Design and Specification Languages for SoCs (revised selected contributions from FDL'05), Vachoux A (Eds.) , Ed. Springer , pp. 5-22, 2006
 
11 Slimani K., Fragoso J., Fesquet L., Renaudin M., Low Power Asynchronous Processors, Low-Power Electronics Design, Ed. CRC Press, pp. Chapter 22; Volume: 1, 2004
 
12 Rigaud J.B., Quartana J., Fesquet L., Renaudin M., Modeling and design of asynchronous priority arbiters for on-chip, SOC Design Methodologies Series: IFIP International Federation for Information Processing, Ed. Kluwer Academic Publishers, pp. 313-324, 2002
 
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9 Livres & Éditions Ouvrages

1 Fesquet L., Torresani B. (Eds.) Sampling Theory in Signal and Image Processing, Special Issue on 8th International Conference on Sampling Theory and Applications (SampTA'09, May 18-22, 2009 in Marseille), pp. Vol. 10, N°1-2, Ed. Sampling Publishing ISSN: 1530-6429, 2011
 
2 Kaiser A., Brillouet M., Fesquet L., Cristoloveanu S. (Eds.) IEEE European Solid-State Circuits Conference (ESSCIRC), Ed. IEEE, 2005
 
3 Fesquet L. (Eds.) Modélisation et synthèse des systèmes matériels, Ed. , 2004
 
4 Fesquet L. (Eds.) Le paquetage VITAL, Ed. , 2004
 
5 Fesquet L. (Eds.) Les bases de la conception analogique intégrée, ENSERG / ENSPG Option , Ed. , 2004
 
6 Fesquet L. (Eds.) TD de modélisation et synthèse des systèmes matériels, ENSERG , Ed. , 2004
 
7 Fesquet L., Rolland R., Mancini S. (Eds.) TP d'architecture d'un SoC, Ed. , 2004
 
8 Baixas A., Mancini S., Fesquet L., Rolland R. (Eds.) Pratique d'un SOPC : application au filtrage numérique, Ed. , 2004
 
9 Fesquet L. (Eds.) Les fonctions analogiques intégrées , Ed. , 2001
 
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1 Revues nationales

1 Fesquet L., Morin-Allory K., Rolland-Girod R., Un projet de microélectronique numérique original : Contrôle autonome d'un micro-drone par caméras externes, J3eA – Journal sur l’enseignement des sciences et technologies de l’information et des systèmes, Ed. EDP Sciences, France, Vol. 14, No. 2009, pp. 9, DOI: 10.1051/j3ea/2015021 , août 2015
 
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14 Conférences nationales

 1 Rolloff O., Iga R., Ferreira De Paiva Leite T., Possamai Bastos R., Fesquet L., Body Bias Control Cells based on Negative- and Positive-Level Shifter Architectures in Technology FD-SOI 28 nm, Journées Nationales du Réseau Doctoral en Micro-nanoélectronique (JNRDM 2017), Strasbourg, FRANCE, 6 au 8 novembre 2017
 
 2 El Hadbi A., Cherkaoui A., Elissati O., Fesquet L., Nouveau dispositif ultra-précis de mesure du temps basé sur un oscillateur auto-séquencé, Colloque GdR SoC-SiP, Talence, FRANCE, 14 au 16 juin 2017
 
 3 Rolloff O., Ferreira De Paiva Leite T., Possamai Bastos R., Fesquet L., Analysis of granularity for automatic biasing control in FDSOI technology with low-voltage supply, Journées Nationales du Réseau Doctoral en Micro-Nanoélectronique (JNRDM'16), Toulouse, FRANCE, 11 au 13 mai 2016
 
 4 Ferreira De Paiva Leite T., Possamai Bastos R., Fesquet L., QDI asynchronous circuits for low power applications: a comparative study in technology FD-SOI 28 nm, Journées Nationales du Réseau Doctoral en Micro-Nanoélectronique (JNRDM'16), Toulouse, FRANCE, 11 au 13 mai 2016
 
 5 Acunha Guimaraes L., Possamai Bastos R., Fesquet L., A New Proposition on Hardware Trojan Activation, Journées Nationales du Réseau Doctoral en Micro-nanoélectronique (JNRDM'15), Bordeaux, FRANCE, 5 au 7 mai 2015
 
 6 Simatic J., Possamai Bastos R., Fesquet L., Flot de conception pour l'ultra-faible consommation : échantillonage non-uniforme et électronique asynchrone, Journées Nationales du Réseau Doctoral en Micro-nanoélectronique (JNRDM'15), Bordeaux, FRANCE, 5 au 7 mai 2015
 
 7 Fesquet L., Morin-Allory K., Rolland-Girod R., Contrôle autonome d'un nano-drone par caméra externe, Journées pédagogiques du CNFM (JPCNFM), Saint-Malo, FRANCE, 19 au 21 novembre 2014
 
 8 Morin-Allory K., Fesquet L., Vérification formelle, 12èmes Journées Pédagogiques de la Coordination Nationale pour la Formation en Micro et nanoélectronique (JPCNFM’12), Saint-Malo, FRANCE, 28 au 29 novembre 2012
 
 9 Le Pelleter T., Bonvilain A., Fesquet L., Méthode à faible coût de calcul et robuste pour la détection d’un motif dans un signal, Journées Nationales du Réseau Doctoral en Microélectronique (JNRDM'12), Marseille, FRANCE, 18 au 20 juin 2012
 
10 Cherkaoui A., Fischer V., Aubert A., Fesquet L., Self-Timed Rings as Sources of Entropy, 6ème colloque du GDR SOC-SIP du CNRS, Paris, FRANCE, 13 au 15 juin 2012
 
11 Anghel L., Fesquet L., Morin-Allory K., Initiation à la conception de VLSI numériques, 10èmes Journées Pédagogiques CNFM (JPCNFM'08), Saint-Malo, FRANCE, 26 au 28 novembre 2008
 
12 Beyrouthy T., Razafindraibe A., Fesquet L., Renaudin M., Secure Asynchronous FPGA for Embedded Systems (SAFE), Colloque Journées GDR SOC-SIP'07, Paris, FRANCE, 13 au 15 juin 2007
 
13 Sicard G., Renaudin M., Allier E., Fesquet L., Conversion analogique-numérique faible consommation : conception asynchrone et echantillonnage irrégulier, 4ème Colloque sur le Traitement Analogique de l'Information, du Signal, et ses Applications (TAISA'03), pp. 53-56 , Louvain-La-Neuve, BELGIUM, 25 au 26 septembre 2003
 
14 Slimani K., Sirianni A., Fesquet L., Remond Y., Sicard G., Renaudin M., Estimation et optimisation de la consommation d'énergie des circuits asynchrones, 4èmes journées d'études Faible Tension, Faible Consommation (FTFC'03), pp. 59-64, Paris, FRANCE, 15 au 16 mai 2003
 
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6 Autres communications

1 Paugnat F., Bousquet L., Fesquet L., Analog Design Abstraction Levels and SystemC AMS Models of Computation, SystemC-AMS Day 2011: Industry Adoption of the SystemC AMS Standard, Dresden, GERMANY, 2011
 
2 Paugnat F., Bousquet L., Morin-Allory K., Fesquet L., A Performance Comparison Between the SystemC-AMS Models of Computation, edaWorkshop 2011, pp. 13-18, Dresden, GERMANY, 2011
 
3 Leblond N., Porcher A., Fesquet L., Tiempo Asynchronous Design Flow Tutorial - Modeling and Debug, Design Automation Conference (DAC’11), San Diego, CA, UNITED STATES, 2011
 
4 Alsayeg K., Fesquet L., Sicard G., Rios D., Renaudin M., Direct mapping of sequential QDI controllers, Ph D Forum on Design, Automation and Test In Europe (DATE'09), Nice, FRANCE, 2009
 
5 Hamon J., Miscopein B., Schwoerer J., Fesquet L., Renaudin M., Implémentation en logique asynchrone d’un algorithme de synchronisation de signaux radio impulsionnelle, 7ème journées d'études Faible Tension Faible Consommation, (FTFC’08), Louvain-la-Neuve, BELGIUM, 2008
 
6 Zakaria H., Fesquet L., Durand S., Albea-Sanchez C., Thonnard Y., Canudas de Wit C., Marchand N., Integrated Asynchronous Regulation for Nanometric Technologies: Application to an Embedded Parallel System, MINATEC CROSSROADS'08, Grenoble, FRANCE, 2008
 
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17 Rapports

 1 Fesquet L., Renaudin M., A PROGRAMMABLE LOGIC ARCHITECTURE FOR PROTOTYPING CLOCKLESS CIRCUITS , ISRN: TIMA-RR--06/02-16--FR, 1 janvier 2005
 
 2 Quartana J., Fesquet L., Renaudin M., Asynchronous Systems on Programmable Logic, ISRN: TIMA-RR--06/02-12--FR, 1 janvier 2005
 
 3 Allier E., Renaudin M., Aeschlimann F., Fesquet L., Etude Spectrale de l'’Échantillonnage par Traversée de Niveaux, ISRN: TIMA-RR--06/02-11--FR, 1 janvier 2005
 
 4 Dubreuil H., Renaudin M., Huot N., Fesquet L., FPGA architecture for multi-style asynchronous logic, ISRN: TIMA-RR--06/02-10--FR, 1 janvier 2005
 
 5 Renane S., Fesquet L., Quartana J., Baixas A., Renaudin M., GALS Systems Prototyping using Multiclock FPGAs , ISRN: TIMA-RR--06/02-15--FR, 1 janvier 2005
 
 6 Quartana J., Renaudin M., Fesquet L., Modular Asynchronous Network-on-Chip: Application to GALS Systems Rapid Prototyping, ISRN: TIMA-RR--06/02-14--FR, 1 janvier 2005
 
 7 Aeschlimann F., Fesquet L., Allier E., Renaudin M., Spectral Analysis of Level-Crossing Sampling Scheme, ISRN: TIMA-RR--06/02-13--FR, 1 janvier 2005
 
 8 Folco B., Fesquet L., Bregier V., Renaudin M., Technology Mapping for Area Optimized Quasi Delay Insensitive Circuits, ISRN: TIMA-RR--06/02-03--FR, 1 janvier 2005
 
 9 Allier E., Renaudin M., Fesquet L., Sicard G., A 6-bit Low-Power Asynchronous Analog-to-Digital Converter, ISRN: TIMA-RR--02/03-06--FR, 1 janvier 2002
 
10 Quartana J., Renaudin M., Rigaud J.B., Fesquet L., High-Level Modeling and Design of Asynchronous Arbiters for On-Chip Communication Systems, ISRN: TIMA-RR--02/03-3--FR, 1 janvier 2002
 
11 Rigaud J.B., Fesquet L., Quartana J., Renaudin M., High-Level Modeling and Design of Asynchronous Arbiters. Poster presentation, ISRN: TIMA-RR--02/03-4--FR, 1 janvier 2002
 
12 Fesquet L., Bouesse G.F., Renaudin M., QDI Circuits to Improve Smartcard Security, ISRN: TIMA-RR--02/03/10--FR, 1 janvier 2002
 
13 Dinh Duc Anh Vu, Rezzag A., Fragoso J., Renaudin M., Rigaud J.B., Sirianni A., Fesquet L., TAST: TIMA Asynchronous Synthesis Tools, ISRN: TIMA-RR--02/03-08--FR, 1 janvier 2002
 
14 Fesquet L., Es Salhiene M., Renaudin M., Towards a Low Power RTOS for Asynchronous Processors, ISRN: TIMA-RR--02/03/07--FR, 1 janvier 2002
 
15 Fesquet L., Lhuillery F., Es Salhiene M., Ho Q. T., Renaudin M., Démonstration de prototypes d'objets communicants en technologie asynchrone, ISRN: TIMA--RR-01/10-14--FR, 1 janvier 2001
 
16 Fesquet L., Lhuillery F., Es Salhiene M., Ho Q. T., Renaudin M., La technologie asynchrone pour la conception d'objets communicants : une revue. Asynchronisme de la puce au système , ISRN: TIMA--RR-01/10-11--FR, 1 janvier 2001
 
17 Quartana J., Renaudin M., Rigaud J.B., Fesquet L., Modeling and design of asynchronous priority arbiters for on-chip communication systems, ISRN: TIMA--RR-01/10-10--FR, 1 janvier 2001
 
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2 Logiciels

1 Gimenez G., Simatic J., Fesquet L., Static Timing Analysis of Bundled-Data Circuits, SOFTWARE, 11 mars 2019
 
2 Borrione D., Ferro L., Fesquet L., Morin-Allory K., Oddos Y., Pierre L., Logiciel, Logiciel, 9 mai 2009
 
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1 Thèses

1 Fesquet L., Asynchronous integrated systems and non-uniformly sampled signal processing, HDR, 31 mars 2008
 
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