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57 résultats

   5 Revues internationales
   3 Conférences invitées
  33 Conférences internationales
   6 Chapitres de livre
   1 Revues nationales
   3 Conférences nationales
   3 Autres communications
   1 Rapports
   1 Logiciels
   1 Thèses

5 Revues internationales

1 Plassan G., Morin-Allory K., Borrione D., Mining Missing Assumptions from Counter-Examples, Transactions on Embedded Computing Systems (TECS), Ed. ACM, NY, USA, Vol. 18, No. 1, DOI: 10.1145/3288759, janvier 2019
 
2 Javaheri N., Morin-Allory K., Borrione D., Synthesis of Regular Expressions Revisited: from PSL SEREs to Hardware, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Ed. IEEE, Vol. 36, No. 5, pp. 869-882, DOI: 10.1109/TCAD.2016.2600241 , mai 2017
 
3 Morin-Allory K., Javaheri N., Borrione D., Efficient and Correct by Construction Assertion-Based Synthesis, Transactions on Very Large Scale Integration (VLSI) Systems, Ed. IEEE, Vol. 23, No. 12, pp. 2890-290, DOI: 10.1109/TVLSI.2014.2386212, décembre 2015
 
4 Morin-Allory K., Boulé M., Borrione D., Zilic Z., Validating Assertion Language Rewrite Rules and Semantics With Automated Theorem Provers, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Ed. IEEE, Vol. 29, No. 9, pp. 1436 - 1448 , DOI: 10.1109/TCAD.2010.2049150 , janvier 2010
 
5 Morin-Allory K., Gascard E., Borrione D., Synthesis of property monitors for online fault detection, Journal of Circuits, Systems, and Computers (JCSC) , Ed. World Scientific Publishing, Vol. 16, No. 6, pp. 943 - 960 , DOI: 10.1142/S0218126607004088, janvier 2007
 
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3 Conférences invitées

1 Borrione D., Morin-Allory K., Liu M., Oddos Y., Morin-Allory K., Javaheri N., Verification and Synthesis of Digital Systems from Assertions, Ecole d'hiver Francophone sur les Technologies de Conception des Systèmes embarqués Hétérogènes (FETCH'16), Villards de Lans, FRANCE, 1 janvier 2016
 
2 Borrione D., Javaheri N., Morin-Allory K., Porcher A., Automatic Prototyping of declarative properties on FPGA, Electronic System Level Synthesis Conference (ESLsyn'13), Austin, Texas, UNITED STATES, 2 au 6 juin 2013
 
3 Borrione D., Liu Z.W., Morin-Allory K., Ostier P., Fesquet L., On-Line Assertion-Based Verification with Proven Correct Monitors, 3rd IEEE International Conference on Information and Communication Technology (ICICT'05), Cairo, EGYPT, 5 au 6 décembre 2005
 
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33 Conférences internationales

 1 Plassan G., Morin-Allory K., Borrione D., Extraction of missing formal assumptions in under-constrained designs, 15th ACM-IEEE International Conference on Formal Methods and Models for System Design (MEMOCODE 2017), pp. 94-103, Vienna, AUSTRIA, DOI: 10.1145/3127041.3127046, 29 septembre au 2 octobre 2017
 
 2 Plassan G., Peter H.J., Morin-Allory K., Rahim F., Sarwary S., Borrione D., Conclusively Verifying Clock-Domain Crossings in Very Large Hardware Designs, IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC'16) , pp. 1-6, Tallinn, ESTONIA, 26 au 28 septembre 2016
 
 3 Kebaili M., Morin-Allory K., Brignone J.C., Borrione D., Enabler-Based Synchronizer Model for Clock Domain Crossing static Verification, Forum on specification & Design Languages (FDL'15), Barcelona, SPAIN, 14 au 16 septembre 2015
 
 4 Javaheri N., Morin-Allory K., Borrione D., Revisiting Regular Expressions in SyntHorus2: from PSL SEREs to Hardware, Forum on specification & Design Languages (FDL'15), Barcelona, SPAIN, 14 au 16 septembre 2015
 
 5 Morin-Allory K., Javaheri N., Borrione D., Fast Prototyping from Assertions: a Pragmatic Approach, 11th ACM-IEEE International Conference on Formal Methods and Models for Codesign (MEMOCODE'13), Portland , Oregon, UNITED STATES, 18 au 20 octobre 2013
 
 6 Morin-Allory K., Javaheri N., Borrione D., SyntHorus-2: Automatic Prototyping from PSL, IFIP/IEEE International Conference On Very Large Scale Integration (VLSI-SoC'13), pp. 75-80, Istanbul, TURKEY, 7 au 9 octobre 2013
 
 7 Paugnat F., Fesquet L., Morin-Allory K., Model of a Simple yet effective Operational Amplifier, International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD'12), pp. 165-168, Seville, SPAIN, DOI: 10.1109/SMACD.2012.6339443 , 19 au 21 septembre 2012
 
 8 Ouchet F., Morin-Allory K., Fesquet L., C-elements for hardened self-timed circuits, 21st International Workshop Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation (PATMOS'11), pp. 247-256, Madrid, SPAIN, DOI: 10.1007/978-3-642-24154-3_25, 26 au 29 septembre 2011
 
 9 Porcher A., Morin-Allory K., Fesquet L., Does Asynchronous technology bring robustness in synchronous circuit monitoring?, Forum on specification & Design Languages (FDL’11), Oldenburg, GERMANY, 13 au 15 septembre 2011
 
10 Porcher A., Morin-Allory K., Fesquet L., Synthesis of Quasi Delay Insensitive Monitors, 7th Conference on PhD Research in Microelectronics and Electronics (PRIME’11), pp. 225 - 228 , Trento, ITALY, DOI: 10.1109/PRIME.2011.5966274 , 3 au 7 juillet 2011
 
11 Paugnat F., Morin-Allory K., Fesquet L., A refinement process for top-down mixed-signal designs thanks to SystemC-AMS , IEEE 9th International New Circuits and Systems Conference (NEWCAS'11), pp. 378 - 381 , Bordeaux, FRANCE, DOI: 10.1109/NEWCAS.2011.5981249 , 26 au 29 juin 2011
 
12 Yan C., Ouchet F., Fesquet L., Morin-Allory K., Formal Verification of C-element Circuits, IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC’11), pp. 55 - 64 , Ithaca (NY), UNITED STATES, DOI: 10.1109/ASYNC.2011.14 , 27 au 29 avril 2011
 
13 Ouchet F., Morin-Allory K., Fesquet L., Delay Insensitivity Does Not Mean Slope Insensitivity!, IEEE Symposium on Asynchronous Circuits and Systems (ASYNC'10), pp. 176 - 184 , Grenoble, FRANCE, DOI: 10.1109/ASYNC.2010.27 , 3 au 6 mai 2010
 
14 Porcher A., Morin-Allory K., Fesquet L., Synthesis of asynchronous monitors for critical electronic systems, IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS’10), pp. 329 - 334 , Vienna, AUSTRIA, DOI: 10.1109/DDECS.2010.5491756 , 14 au 16 avril 2010
 
15 Oddos Y., Morin-Allory K., Borrione D., Synthorus: Highly Efficient Automatic Synthesis from PSL to HDL, International Conference On Very Large Scale Integration (VLSI-SoC'09), Florianopolis, BRAZIL, 12 au 14 octobre 2009
 
16 Alsayeg K., Morin-Allory K., Fesquet L., RAT-based formal verification of QDI asynchronous controllers, Forum on specifications and Design Languages (FDL’09), pp. 1-6, Nice Sophia-Antipolis, FRANCE, 22 au 24 septembre 2009
 
17 Oddos Y., Boulé M., Morin-Allory K., Borrione D., Zilic Z., MYGEN: Automata-based On-line Test Generator for Assertion-based Verification, 19th Great Lakes Symposium on VLSI (GLSVLSI'09), pp. 75-80, Boston, MA., UNITED STATES, DOI: 10.1145/1531542.1531563, 10 au 12 mai 2009
 
18 Ouchet F., Borrione D., Morin-Allory K., Pierre L., High-level symbolic simulation for automatic model extraction, IEEE Symposium on Design and Diagnostics of Electronic Systems (DDECS’09), pp. 218-221, Liberec, CZECH REPUBLIC, DOI: 10.1109/DDECS.2009.5012132, 15 au 17 avril 2009
 
19 Oddos Y., Morin-Allory K., Borrione D., Assertion-Based Verification and On-line Testing in Horus, IEEE International Design and Test Workshop (IDT'08), pp. 249 – 255 , Monastir, TUNISIA, 20 au 21 décembre 2008
 
20 Morin-Allory K., Boulé M., Borrione D., Zilic Z., Proving and Disproving Assertion Rewrite Rules by Automated Theorem Proving, Proc. of IEEE International High Level Design Validation and Test Workshop (HLDVT'08), pp. 56-63, Lake Tahoe, Nevada, UNITED STATES, DOI: 10.1109/HLDVT.2008.4695875, 19 au 21 novembre 2008
 
21 Oddos Y., Morin-Allory K., Borrione D., Assertion-Based Design with Horus, International Conference on Formal Methods and Models for Codesign (MEMOCODE'08), pp. 75-76, Anaheim, CA, UNITED STATES, DOI: 10.1109/MEMCOD.2008.4547691 , 5 au 7 juin 2008
 
22 Morin-Allory K., Fesquet L., Borrione D., Asynchronous online monitoring of logical and temporal assertions, 10th Forum on Specification and Design Languages (FDL'07), Barcelona, SPAIN, 18 au 20 septembre 2007
 
23 Oddos Y., Morin-Allory K., Borrione D., Prototyping Generators for On-line Test Vector Generation Based on PSL Properties, IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems (DDECS’07), pp. 1-6, Krakow, POLAND, DOI: 10.1109/DDECS.2007.4295317, 11 au 13 avril 2007
 
24 Oddos Y., Morin-Allory K., Borrione D., On-line test vector generation from temporal regular expressions, Intensive Workshop on Service Oriented Computing (IWSOC'06), pp. 135-140, Cairo, EGYPT, 16 au 17 décembre 2006
 
25 Oddos Y., Morin-Allory K., Borrione D., On-line test vector generation from temporal constraints written in PSL, Proc. 14th IFIP International Conference on Very Larage Scale Integration (VLSI-SoC’06), pp. 397-402, Nice, FRANCE, 16 au 18 octobre 2006
 
26 Morin-Allory K., Borrione D., On-line monitoring of properties built on regular expressions, Forum on Specification and Design Languages (FDL'06), pp. 249-254 , Darmstadt, GERMANY, 19 au 22 septembre 2006
 
27 Morin-Allory K., Borrione D., Automatic generation of a provable circuit model: from VHDL to PVS, 8ème International Mathematica Symposium (IMS'06), pp. 12, Avignon, FRANCE, 21 au 23 juin 2006
 
28 Quinton P., Risset T., Morin-Allory K., Cachera D., Designing parallel programs and integrated circuits, 8ème International Mathematica Symposium (IMS'06), pp. 1-13, Avignon, FRANCE, 19 au 23 juin 2006
 
29 Morin-Allory K., Fesquet L., Borrione D., Asynchronous Assertion Monitors for multi-Clock Domain System Verification, 17th IEEE Symposium on Rapid System Prototyping (RSP'06), pp. 98- 102, Chania, GREECE, DOI: 10.1109/RSP.2006.9 , 14 au 16 juin 2006
 
30 Morin-Allory K., Fesquet L., Borrione D., Asynchronous on-line monitoring of PSL assertions, 17th IEEE Symposium on Rapid System Prototyping (RSP'06), pp. 98-102, Chania, GREECE, DOI: 10.1109/RSP.2006.9, 14 au 16 juin 2006
 
31 Borrione D., Morin-Allory K., Proven correct monitors from PSL specifications, Conference on Design, automation and test in Europe (DATE'06), Munich, GERMANY, 6 au 10 mars 2006
 
32 Morin-Allory K., Borrione D., A proof of correctness for the construction of property monitors, Tenth IEEE International High-Level Design Validation and Test Workshop (HLDVT'05), pp. 237-244, Napa, CA, UNITED STATES, DOI: 10.1109/HLDVT.2005.1568843, 30 novembre au 2 décembre 2005
 
33 Morin-Allory K., Cachera D., Proving Parameterized Systems: the use of pseudo-pipelines in polyhedral logic, 13th Working Conference in Correct Hardware Design and Verification Methods: IFIP WG 10.5 Advanced Research (CHARME'05), Saarbrücken, GERMANY, DOI: 10.1007/11560548_35, 3 au 6 octobre 2005
 
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6 Chapitres de livre

1 Plassan G., Peter H.J., Morin-Allory K., Sarwary S., Borrione D., Improving the Efficiency of Formal Verification: The Case of Clock-Domain Crossings, VLSI-SoC: System-on-Chip in the Nanoscale Era – Design, Verification and Reliability, revised selected contributions from 24th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2016, Hollstein T., Raik J., Kostin S., Tšertov A., O'Connor I., Reis R (Eds.) , Ed. Springer , pp. 108-129, Vol. 508, DOI: 10.1007/978-3-319-67104-8, 2017
 
2 Borrione D., Morin-Allory K., Oddos Y., Property-Based Dynamic Verification and Test, Design Technology for Heterogeneous Embedded Systems, G. Nicolescu, I. O'Connor, C. Piguet (Eds.) , Ed. Springer , pp. 157-176, DOI: DOI:10.1007/978-94-007-1125-9_8, 2012
 
3 Oddos Y., Morin-Allory K., Borrione D., From Assertion-based Verification to Assertion-based Synthesis, VLSI-SOC: Technologies for Systems Integration" (revised selected contributions from VLSI-SOC'09), J. Becker, M. Johann & R. Reis (Eds.) , Ed. Springer , pp. , Vol. AICT N° 360, 2011
 
4 Morin-Allory K., Fesquet L., Roustan B., Borrione D., Asynchronous online monitoring of logical and temporal assertions, Embedded Systems Specification and Design Languages, Villar Eugenio (Eds.) , Ed. Springer , pp. 278 p, 2008
 
5 Morin-Allory K., Borrione D., On-line monitoring of properties built on regular expressions sequences, Advances in Design and Specification Languages for Embedded Systems (Selected Contributions from FDL'06), Sorin A. Huss (Eds.) , Ed. Springer , pp. 197-207, DOI: doi 10.1007/978-1-4020-6149-3_12, 2007
 
6 Morin-Allory K., Cachera D., Proving Parameterized Systems: the use of pseudo-pipelines in polyhedral logic, Correct Hardware Design and Verification Methods, Ed. Springer , pp. 376-379, Vol. 3725, DOI: 10.1007/11560548_35, 2005
 
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1 Revues nationales

1 Fesquet L., Morin-Allory K., Rolland-Girod R., Un projet de microélectronique numérique original : Contrôle autonome d'un micro-drone par caméras externes, J3eA – Journal sur l’enseignement des sciences et technologies de l’information et des systèmes, Ed. EDP Sciences, France, Vol. 14, No. 2009, pp. 9, DOI: 10.1051/j3ea/2015021 , août 2015
 
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3 Conférences nationales

1 Fesquet L., Morin-Allory K., Rolland-Girod R., Contrôle autonome d'un nano-drone par caméra externe, Journées pédagogiques du CNFM (JPCNFM), Saint-Malo, FRANCE, 19 au 21 novembre 2014
 
2 Morin-Allory K., Fesquet L., Vérification formelle, 12èmes Journées Pédagogiques de la Coordination Nationale pour la Formation en Micro et nanoélectronique (JPCNFM’12), Saint-Malo, FRANCE, 28 au 29 novembre 2012
 
3 Anghel L., Fesquet L., Morin-Allory K., Initiation à la conception de VLSI numériques, 10èmes Journées Pédagogiques CNFM (JPCNFM'08), Saint-Malo, FRANCE, 26 au 28 novembre 2008
 
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3 Autres communications

1 Bel Hadj Amor Z., Borrione D., Javaheri N., Morin-Allory K., Pierre L., Design Understanding - At What Abstraction Level is the Pain Most Intense?, Workshop on Design Automation for Understanding Hardware Designs (DUHDe Friday Workshop DATE 2015), Grenoble, FRANCE, 2015
 
2 Morin-Allory K., Javaheri N., Borrione D., Design Understanding with Fast Prototyping from Assertions, Workshop on Design Automation for Understanding Hardware Designs (Friday Workshop DATE'14), Dresden, GERMANY, 2014
 
3 Paugnat F., Bousquet L., Morin-Allory K., Fesquet L., A Performance Comparison Between the SystemC-AMS Models of Computation, edaWorkshop 2011, pp. 13-18, Dresden, GERMANY, 2011
 
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1 Rapports

1 Cachera D., Morin-Allory K., Proving Parameterized Systems: the use of a widening operator and pseudo-pipelines in polyhedral logic, ISRN: TIMA-RR--05/04-01--FR, 1 janvier 2005
 
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1 Logiciels

1 Borrione D., Ferro L., Fesquet L., Morin-Allory K., Oddos Y., Pierre L., Logiciel, Logiciel, 9 mai 2009
 
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1 Thèses

1 Morin-Allory K., Assertions and hardware design, HDR, 15 novembre 2018
 
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