Publications

Publications

Recherche

Recherche

Auteur
hors TIMA
Équipe :

Mot clé
Type de publications
Tous
Sélectionne/déselectionne tous les types de publications
Journal art.
International National Tous
 Brevets  Conférences invitées
Conference art.
International National Tous
Chapitres de livre  Livres & Éditions Ouvrages
 Autres communications
 Logiciels  Thèses
 
 année
 

184 résultats

  17 Revues internationales
   9 Conférences invitées
  98 Conférences internationales
  27 Chapitres de livre
   6 Livres & Éditions Ouvrages
   3 Revues nationales
   5 Conférences nationales
   5 Autres communications
  13 Rapports
   1 Logiciels

17 Revues internationales

 1 Plassan G., Morin-Allory K., Borrione D., Mining Missing Assumptions from Counter-Examples, Transactions on Embedded Computing Systems (TECS), Ed. ACM, NY, USA, Vol. 18, No. 1, DOI: 10.1145/3288759, janvier 2019
 
 2 Javaheri N., Morin-Allory K., Borrione D., Synthesis of Regular Expressions Revisited: from PSL SEREs to Hardware, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Ed. IEEE, Vol. 36, No. 5, pp. 869-882, DOI: 10.1109/TCAD.2016.2600241 , mai 2017
 
 3 Morin-Allory K., Javaheri N., Borrione D., Efficient and Correct by Construction Assertion-Based Synthesis, Transactions on Very Large Scale Integration (VLSI) Systems, Ed. IEEE, Vol. 23, No. 12, pp. 2890-290, DOI: 10.1109/TVLSI.2014.2386212, décembre 2015
 
 4 Morin-Allory K., Boulé M., Borrione D., Zilic Z., Validating Assertion Language Rewrite Rules and Semantics With Automated Theorem Provers, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Ed. IEEE, Vol. 29, No. 9, pp. 1436 - 1448 , DOI: 10.1109/TCAD.2010.2049150 , janvier 2010
 
 5 Borrione D., Helmy A., Pierre L., Schmaltz J., A Formal Approach to the Verification of Networks on Chip, EURASIP Journal on Embedded Systems, Ed. Hindawi Publishing Corporation, Vol. 2009, No. Article ID 548324, pp. 14, DOI: 10.1155/2009/548324, 2009
 
 6 Schmaltz J., Borrione D., A functional formalization of on chip communications, Formal Aspects of Computing, Ed. Springer , Vol. 20, No. 3, pp. 241-258, DOI: 10.1007/s00165-007-0049-0, janvier 2008
 
 7 Morin-Allory K., Gascard E., Borrione D., Synthesis of property monitors for online fault detection, Journal of Circuits, Systems, and Computers (JCSC) , Ed. World Scientific Publishing, Vol. 16, No. 6, pp. 943 - 960 , DOI: 10.1142/S0218126607004088, janvier 2007
 
 8 Borrione D., Dusina J., Pierre L., A compositional model for the functional verification of high-level synthesis results, Transactions on Very Large Scale Integration (VLSI) Systems, Ed. IEEE, Vol. 8, No. 5, pp. 526-30, DOI: 10.1109/92.894157, octobre 2000
 
 9 Mermet J., Marwedel P., Ramming F.-J., Newton C., Borrione D., Le Faou C., Three decades of hardware description languages in Europe, Journal of Electrical Engineering and Information Science, Vol. 3, No. 6, pp. 700-723, décembre 1998
 
10 Wahba A., Borrione D., A method for automatic design error location and correction in combinational logic circuits, Journal of Electronic Testing: Theory and Applications, Ed. Springer , Vol. 8, No. 2, pp. 113-127, avril 1996
 
11 Borrione D., Eveking H., Formal verification of hardware designs, Journal of the Brazilian Computer Society, Ed. Springer , Vol. , No. Special Issue on Electronic Design Automation, novembre 1995
 
12 Borrione D., Salem A., Denotational semantics of a synchronous VHDL subset, Formal Methods in System Design, Vol. 7, No. 1-2, pp. 53-71, août 1995
 
13 Borrione D., Piloty R., CONLAN: a short review and critical comparison with VHDL, IEEE Design & Test, Ed. IEEE, Vol. 9, No. 3, septembre 1992
 
14 Borrione D., Piloty R., Hill F., Lieberherr K.-J., Moorby P., Three decades of HDLs. II. Conlan through Verilog, IEEE Design and Test of Computers, Ed. IEEE, Vol. 9, No. 3, pp. 54-63, DOI: 10.1109/54.156158, septembre 1992
 
15 Borrione D., Pierre L., Salem A., Formal verification of VHDL descriptions in the PREVAIL environment, IEEE Design and Test of Computers, Ed. IEEE, Vol. 9, No. 2, pp. 42-56, DOI: 10.1109/54.143145, juin 1992
 
16 Borrione D., Camurati P., Prinetto P., Paillet J.-L., Functional approaches applied to microprogrammed architectures, Interntional Journal of Computer Aided VLSI Design, Vol. 2, No. 4, pp. 339-358, avril 1990
 
17 Borrione D., Piloty R., The Conlan project: concepts, implementations, and applications, Computer, Ed. IEEE, Vol. 18, No. 2, pp. 81-92, février 1985
 
remonter

9 Conférences invitées

1 Borrione D., Automatic Synthesis of Verification IP's from Assertions: Beyond Observers, 19th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS'16), Košice, SLOVENIA, 20 au 22 avril 2016
 
2 Borrione D., Morin-Allory K., Liu M., Oddos Y., Morin-Allory K., Javaheri N., Verification and Synthesis of Digital Systems from Assertions, Ecole d'hiver Francophone sur les Technologies de Conception des Systèmes embarqués Hétérogènes (FETCH'16), Villards de Lans, FRANCE, 1 janvier 2016
 
3 Borrione D., Javaheri N., Morin-Allory K., Porcher A., Automatic Prototyping of declarative properties on FPGA, Electronic System Level Synthesis Conference (ESLsyn'13), Austin, Texas, UNITED STATES, 2 au 6 juin 2013
 
4 Borrione D., Assertion Based Test, Forum on specification & Design Languages (FDL'08), Stuttgart, GERMANY, 23 au 25 septembre 2008
 
5 Borrione D., HORUS: proven correct support for on-line property verification, Ecole d'Hiver Francophone sur les Technologies de Conception des systèmes embarqués Hétérogènes (FETCH'08), Montebello, Québec, CANADA, 7 au 9 janvier 2008
 
6 Borrione D., Liu Z.W., Morin-Allory K., Ostier P., Fesquet L., On-Line Assertion-Based Verification with Proven Correct Monitors, 3rd IEEE International Conference on Information and Communication Technology (ICICT'05), Cairo, EGYPT, 5 au 6 décembre 2005
 
7 Borrione D., Formal Verification, Invited Tutorial, MEDEA+ Design Automation Conference, Stresa, ITALY, 23 au 25 octobre 2002
 
8 Borrione D., On the development of hardware description languages, Invited Talk, Wissenschaftliches Kolloquium of the Braunschweigische Wissenschaftliche Gesellschaft, Braunschweig, GERMANY, 18 mai 2001
 
9 Borrione D., Utilisation des méthodes formelles pour la vérification des systèmes intégrés digitaux, AFADL'2000, Grenoble, FRANCE, 26 au 28 janvier 2000
 
remonter

98 Conférences internationales

 1 Plassan G., Morin-Allory K., Borrione D., Extraction of missing formal assumptions in under-constrained designs, 15th ACM-IEEE International Conference on Formal Methods and Models for System Design (MEMOCODE 2017), pp. 94-103, Vienna, AUSTRIA, DOI: 10.1145/3127041.3127046, 29 septembre au 2 octobre 2017
 
 2 Plassan G., Peter H.J., Morin-Allory K., Rahim F., Sarwary S., Borrione D., Conclusively Verifying Clock-Domain Crossings in Very Large Hardware Designs, IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC'16) , pp. 1-6, Tallinn, ESTONIA, 26 au 28 septembre 2016
 
 3 Kebaili M., Morin-Allory K., Brignone J.C., Borrione D., Enabler-Based Synchronizer Model for Clock Domain Crossing static Verification, Forum on specification & Design Languages (FDL'15), Barcelona, SPAIN, 14 au 16 septembre 2015
 
 4 Javaheri N., Morin-Allory K., Borrione D., Revisiting Regular Expressions in SyntHorus2: from PSL SEREs to Hardware, Forum on specification & Design Languages (FDL'15), Barcelona, SPAIN, 14 au 16 septembre 2015
 
 5 Bel Hadj Amor Z., Pierre L., Borrione D., A Tool for the Automatic TLM-to-RTL Conversion of Embedded Systems Requirements for a Seamless Verification Flow, International Conference on Very Large Scale Integration (VLSI-SoC'14), pp. 1-6, Playa del Carmen, Mexico, MEXICO, DOI: 10.1109/VLSI-SoC.2014.7004196, 6 au 8 octobre 2014
 
 6 Bel Hadj Amor Z., Pierre L., Borrione D., System-on-Chip Verification: TLM-to-RTL Assertions Transformation, 10th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME'14), pp. 1-4, Grenoble, FRANCE, DOI: 10.1109/PRIME.2014.6872713, 30 juin au 3 juillet 2014
 
 7 Morin-Allory K., Javaheri N., Borrione D., Fast Prototyping from Assertions: a Pragmatic Approach, 11th ACM-IEEE International Conference on Formal Methods and Models for Codesign (MEMOCODE'13), Portland , Oregon, UNITED STATES, 18 au 20 octobre 2013
 
 8 Morin-Allory K., Javaheri N., Borrione D., SyntHorus-2: Automatic Prototyping from PSL, IFIP/IEEE International Conference On Very Large Scale Integration (VLSI-SoC'13), pp. 75-80, Istanbul, TURKEY, 7 au 9 octobre 2013
 
 9 Oddos Y., Morin-Allory K., Borrione D., Synthorus: Highly Efficient Automatic Synthesis from PSL to HDL, International Conference On Very Large Scale Integration (VLSI-SoC'09), Florianopolis, BRAZIL, 12 au 14 octobre 2009
 
10 Oddos Y., Boulé M., Morin-Allory K., Borrione D., Zilic Z., MYGEN: Automata-based On-line Test Generator for Assertion-based Verification, 19th Great Lakes Symposium on VLSI (GLSVLSI'09), pp. 75-80, Boston, MA., UNITED STATES, DOI: 10.1145/1531542.1531563, 10 au 12 mai 2009
 
11 Ouchet F., Borrione D., Morin-Allory K., Pierre L., High-level symbolic simulation for automatic model extraction, IEEE Symposium on Design and Diagnostics of Electronic Systems (DDECS’09), pp. 218-221, Liberec, CZECH REPUBLIC, DOI: 10.1109/DDECS.2009.5012132, 15 au 17 avril 2009
 
12 Oddos Y., Morin-Allory K., Borrione D., Assertion-Based Verification and On-line Testing in Horus, IEEE International Design and Test Workshop (IDT'08), pp. 249 – 255 , Monastir, TUNISIA, 20 au 21 décembre 2008
 
13 Morin-Allory K., Boulé M., Borrione D., Zilic Z., Proving and Disproving Assertion Rewrite Rules by Automated Theorem Proving, Proc. of IEEE International High Level Design Validation and Test Workshop (HLDVT'08), pp. 56-63, Lake Tahoe, Nevada, UNITED STATES, DOI: 10.1109/HLDVT.2008.4695875, 19 au 21 novembre 2008
 
14 Borrione D., Helmy A., Pierre L., Schmaltz J., Executable Formal Specification and Validation of NoC Communication Infrastructures, Proc. of 21st Symposium on Integrated Circuits and Systems Design (SBCCI’08), pp. 176-181, Gramado, BRAZIL, DOI: 10.1145/1404371.1404421, 1 au 4 septembre 2008
 
15 Oddos Y., Morin-Allory K., Borrione D., Assertion-Based Design with Horus, International Conference on Formal Methods and Models for Codesign (MEMOCODE'08), pp. 75-76, Anaheim, CA, UNITED STATES, DOI: 10.1109/MEMCOD.2008.4547691 , 5 au 7 juin 2008
 
16 Morin-Allory K., Fesquet L., Borrione D., Asynchronous online monitoring of logical and temporal assertions, 10th Forum on Specification and Design Languages (FDL'07), Barcelona, SPAIN, 18 au 20 septembre 2007
 
17 Borrione D., Helmy A., Pierre L., Schmaltz J., A Generic Model for Formally Verifying NoC Communication Architectures: A Case Study, ACM/IEEE International Symposium on Networks-on-Chips (NOCS'2007), pp. 127-136, Princeton, NJ, UNITED STATES, DOI: 10.1109/NOCS.2007.1, 7 au 9 mai 2007
 
18 Oddos Y., Morin-Allory K., Borrione D., Prototyping Generators for On-line Test Vector Generation Based on PSL Properties, IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems (DDECS’07), pp. 1-6, Krakow, POLAND, DOI: 10.1109/DDECS.2007.4295317, 11 au 13 avril 2007
 
19 Oddos Y., Morin-Allory K., Borrione D., On-line test vector generation from temporal regular expressions, Intensive Workshop on Service Oriented Computing (IWSOC'06), pp. 135-140, Cairo, EGYPT, 16 au 17 décembre 2006
 
20 Oddos Y., Morin-Allory K., Borrione D., On-line test vector generation from temporal constraints written in PSL, Proc. 14th IFIP International Conference on Very Larage Scale Integration (VLSI-SoC’06), pp. 397-402, Nice, FRANCE, 16 au 18 octobre 2006
 
21 Borrione D., Helmy A., Pierre L., ACL2-based verification of the communications in the hermes network on chip, International Workshop on Symbolic Methods and Applications to Circuit Design (SMACD'06), pp. 1-6, Firenze, ITALY, 12 au 13 octobre 2006
 
22 Morin-Allory K., Borrione D., On-line monitoring of properties built on regular expressions, Forum on Specification and Design Languages (FDL'06), pp. 249-254 , Darmstadt, GERMANY, 19 au 22 septembre 2006
 
23 Schmaltz J., Borrione D., Towards a formal theory of communication architecture in the ACL2 logic, 6th International Workshop on the ACL2 Theorem Prover and its Applications (ACL2'06), pp. 47-56, Seattle, WA, UNITED STATES, 15 au 16 août 2006
 
24 Morin-Allory K., Borrione D., Automatic generation of a provable circuit model: from VHDL to PVS, 8ème International Mathematica Symposium (IMS'06), pp. 12, Avignon, FRANCE, 21 au 23 juin 2006
 
25 Morin-Allory K., Fesquet L., Borrione D., Asynchronous Assertion Monitors for multi-Clock Domain System Verification, 17th IEEE Symposium on Rapid System Prototyping (RSP'06), pp. 98- 102, Chania, GREECE, DOI: 10.1109/RSP.2006.9 , 14 au 16 juin 2006
 
26 Morin-Allory K., Fesquet L., Borrione D., Asynchronous on-line monitoring of PSL assertions, 17th IEEE Symposium on Rapid System Prototyping (RSP'06), pp. 98-102, Chania, GREECE, DOI: 10.1109/RSP.2006.9, 14 au 16 juin 2006
 
27 Schmaltz J., Borrione D., Formalizing on chip communication in a functional style, Trustworthy Software Workshop, pp. 25, Saarbrücken, GERMANY, 15 au 18 mai 2006
 
28 Borrione D., Morin-Allory K., Proven correct monitors from PSL specifications, Conference on Design, automation and test in Europe (DATE'06), Munich, GERMANY, 6 au 10 mars 2006
 
29 Morin-Allory K., Borrione D., A proof of correctness for the construction of property monitors, Tenth IEEE International High-Level Design Validation and Test Workshop (HLDVT'05), pp. 237-244, Napa, CA, UNITED STATES, DOI: 10.1109/HLDVT.2005.1568843, 30 novembre au 2 décembre 2005
 
30 Borrione D., Liu M., Ostier P., Fesquet L., PSL-based online monitoring of digital systems, Forum on specification and Design Languages (FDL'05), pp. 465-478, Lausanne, SWITZERLAND, 27 au 30 septembre 2005
 
31 Schmaltz J., Borrione D., A Generic Network on Chip Model, 18th International Conference on Theorem Proving in Higher Order Logics (TPHOLs'05), pp. 310, Oxford, UNITED KINGDOM, DOI: 10.1007/11541868_20, 22 au 25 août 2005
 
32 Al Sammane G., Borrione D., Chevallier R., Verification of behavioral descriptions by combining symbolic simulation and automatic reasoning, 15th ACM Great Lakes symposium on VLSI, Chicago, Illinois, UNITED STATES, DOI: 10.1145/1057661, 17 au 19 avril 2005
 
33 Schmaltz J., Borrione D., A functional specification and validation model for networks on chip in the ACL2 logic, 5th International Workshop on the ACL2 Theorem Prover and its Applications (ACL2'04), pp. 1-18, Austin, Texas, UNITED STATES, 18 au 19 novembre 2004
 
34 Toma D., Borrione D., Verification of a cryptographic circuit: SHA-1 using ACL2, 5th International Workshop on the ACL2 Theorem Prover and its Applications (ACL2'04), pp. 1-19, Austin, Texas, UNITED STATES, 18 au 19 septembre 2004
 
35 Al Sammane G., Schmaltz J., Toma D., Ostier P., Borrione D., TheoSim: combining symbolic simulation and theorem proving for hardware verification, IEEE 17th Symposium on Integrated Circuits and Systems Design (SBCCI'04) , pp. 60-65, Pernambuco, BRAZIL, 7 au 11 septembre 2004
 
36 Toma D., Perez A, Borrione D., Bergeret E., Design of a proven correct SHA circuit, International Conference on Electrical, Electronic and Computer Engineering (ICEEC'04), Cairo, EGYPT, 5 au 7 septembre 2004
 
37 Al Sammane G., Schmaltz J., Borrione D., Formal design and verification of on chip networking, IEEE International Conference on Information and Communication Technologies: From Theory to Applications (ICTTA'04), pp. 657-658, Damascus, SYRIAN ARAB REPUBLIC, DOI: 10.1109/ICTTA.2004.1307937, 19 au 23 avril 2004
 
38 Borrione D., Boubekeur M., Mounier L., Sirianni A., Renaudin M., Validation of asynchronous circuit specifications using IF/CADP, 12th IFIP International Conference on Very Large Scale Integration (VLSI'03), Darmstadt, GERMANY, 1 au 3 décembre 2003
 
39 Boubekeur M., Renaudin M., Borrione D., Mounier L., Sirianni A., Modeling CHP descriptions in Labeled Transitions Systems for an efficient formal validation of asynchronous circuit specifications, Forum on specification and Design Languages (FDL'03), Frankfurt, GERMANY, 23 au 26 septembre 2003
 
40 Borrione D., Toma D., SHA formalization, International Workshop on the ACL2 Theorem Prover and Its Applications (ACL2'03), pp. 1-5, Boulder, UNITED STATES, 13 au 14 juillet 2003
 
41 Borrione D., Schmaltz J., Verification of a parameterized bus architecture using ACL2, International Workshop on the ACL2 Theorem Proverand Its Applications (ACL2'03), Boulder, Colorado, UNITED STATES, 13 au 14 juillet 2003
 
42 Dumitrescu E., Borrione D., Symbolic simulation as a simplifying strategy for SoC verification, 3rd IEEE International Workshop on System on Chip for Real Time Applications, pp. 378-383, Calgary, Alberta, CANADA, DOI: 10.1109/IWSOC.2003.1213066, 30 juin au 2 juillet 2003
 
43 Borrione D., Schmaltz J., Formalization and verification of the AMBA AHB communication architecture using the ACL2 theorem prover, 6th International Workshop on Design and Diagnostics of Electronic Circuits and Systems (DDECS'03), Poznan, POLAND, 14 au 16 avril 2003
 
44 Al Sammane G., Borrione D., Formal validation of high level specification of data path digital circuits by symbolic simulation, The 6th IEEE International Workshop on Design and Diagnostics of Electronics Circuits and Systems (DDECS'03), Poznan, POLAND, 14 au 16 avril 2003
 
45 Al Sammane G., Borrione D., Design and Verification of Digital Circuits in Mathematica: Symbolic simulation of VHDL descriptions, Mathematica Developer Conference, Champaign, IL, UNITED STATES, 1 avril 2003
 
46 Borrione D., Boubekeur M., Dumitrescu E., Renaudin M., Rigaud J.B., Sirianni A., An approach to the introduction of formal validation in an asynchronous circuit design flow, 36th Hawaii International Conference on Systems Sciences (HICSS'03), pp. 1-10 , Big Island, HI, UNITED STATES, DOI: 10.1109/HICSS.2003.1174811, 6 au 9 janvier 2003
 
47 Vidal J., Deharbe D., Borrione D., Improving static ordering of BDDs for reachability analysis, 11th IEEE/ACM International Workshop on Logic & Synthesis (IWLS'02), New Orleans, UNITED STATES, 4 au 7 juin 2002
 
48 Georgelin P., Ostier P., Borrione D., A framework for VHDL combining theorem proving and symbolic simulation, Third International Workshop on the ACL2 Theorem Prover and its Applications (ACL2'02), pp. 1-15, Grenoble, FRANCE, 8 au 9 avril 2002
 
49 Boubekeur M., Renaudin M., Sirianni A., Borrione D., Dumitrescu E., Rigaud J.B., Introducing formal validation in an asynchronous circuit design flow, The Fourth International Workshop on Designing Correct Circuits (DCC'02), Grenoble, FRANCE, 6 au 7 avril 2002
 
50 Reda S., Wahba A., Salem A., Borrione D., Ghonaimy M., On the use of don't cares during symbolic reachability analysis, The IEEE International Symposium on Circuits and Systems (ISCAS'01), pp. 121-124, Sydney, AUSTRALIA, DOI: 10.1109/ISCAS.2001.922000, 6 au 9 mai 2001
 
51 Rodrigues V.M., Borrione D., Georgelin P., Reasoning about VHDL components with ACL2, Workshop on Formal Methods (WMF'00), João Pessoa, Paraíba, BRAZIL, 2 au 4 octobre 2000
 
52 Moraes-Rogrigues V., Borrione D., Georgelin P., An ACL2 model of VHDL for symbolic simulation and formal verification, 13th Symposium on Integrated Circuits and Systems Design (SBCCI'00), pp. 269-274, Manaus, BRAZIL, DOI: 10.1109/SBCCI.2000.876041, 18 au 24 septembre 2000
 
53 Borrione D., Georgelin P., Rodrigues V.M., Symbolic simulation and verification of VHDL with ACL2, International HDL Conference (HDLCON'00), San Jose, CA, UNITED STATES, 8 au 10 mars 2000
 
54 Ubar R., Borrione D., Design error diagnosis in digital circuits without error model, Tenth International Conference on Very Large Scale Integration (VLSI'99), pp. 281-292, Lisbon, PORTUGAL, 1 au 4 décembre 1999
 
55 Borrione D., Georgelin P., Formal verification of VHDL using VHDL-like ACL2 models, Forum on Design Languages (FDL'99), Lyon, FRANCE, 30 août au 3 septembre 1999
 
56 Borrione D., Dusina J., Pierre L., Formalization of finite state machines with data path for the verification of high-level synthesis, XI Brazilian Symposium on Integrated Circuit Design (SBCCI'98), pp. 99-102, Rio de Janeiro, BRAZIL, DOI: 10.1109/SBCCI.1998.715419, 30 septembre au 2 octobre 1998
 
57 Ubar R., Borrione D., Generation of tests for the localization of single gate design errors in combinational circuits using the stuck-at fault model, XI Brazilian Symposium on Integrated Circuit Design (SBCCI'98), pp. 51-54, Rio de Janeiro, BRAZIL, DOI: 10.1109/SBCCI.1998.715409, 30 septembre au 2 octobre 1998
 
58 Dusina J., Borrione D., Jerraya A. A., Formal Verification of the Allocation Step in High Level Synthesis, Forum on Design Languages (FDL'98), Lausanne, SWITZERLAND, 6 au 11 septembre 1998
 
59 Ubar R., Borrione D., Localization of single gate design errors in combinational circuits by diagnostic information about stuck-at faults, Design and Diagnostics of Electronic Circuits and Systems Workshop (DDECS'98), Szczyrk, POLAND, 2 au 4 septembre 1998
 
60 Borrione D., Vestman F., Bouamama H., An approach to Verilog-VHDL interoperability for synchronous designs, International Conference on Correct Hardware and Verification Methods (CHARME'97), pp. 65-87, Montreal, CANADA, 16 au 18 octobre 1997
 
61 Dusina J., Borrione D., Formalisation and validation of the Std_Logic_1164 and Numeric_Std {VHDL} packages using the Nqthm theorem prover, 2nd Workshop on Libraries, Component Modeling and Quality Assurance, Toledo, SPAIN, 23 au 25 avril 1997
 
62 Wahba A., Borrione D., Connection error location and correction in combinational circuits, European Design and Test Conference (ED & TC'97) , pp. 235-241, Paris, FRANCE, DOI: 10.1109/EDTC.1997.582365, 17 au 20 mars 1997
 
63 Dusina J., Borrione D., Jerraya A. A., Correct reuse of complex design units during high level synthesis: verification issues, 1st IEEE International High Level Design Validation and Test Workshop (HLDVT'96), Oakland, Ca., UNITED STATES, 8 au 10 novembre 1996
 
64 Borrione D., Bouamama H., Deharbe H., Le Faou C., Wahba A., HDL-based integration of formal methods and CAD tools in the PREVAIL environment, First International Conference on Formal Methods in Computer Aided Design (FMCAD '96), pp. 450-467, Palo Alto, CA, UNITED STATES, 6 au 8 novembre 1996
 
65 Wahba A., Borrione D., Automatic diagnosis may replace simulation for correcting simple design errors, European Design Automation Conference with EURO VHDL '96 and Exhibition (EURO DAC '96), pp. 476-481, Geneva, SWITZERLAND, DOI: 10.1109/EURDAC.1996.558246, 16 au 20 septembre 1996
 
66 Borrione D., Research on VHDL in France, Italy and Switzerland, Spring VIUF Conference, Santa Clara, California, UNITED STATES, 1 février 1996
 
67 Borrione D., Bouamama H., Suescun R., Validation of the Numeric_Bit package using the NQTHM theorem prover, 3rd Asia Pacific Conference on Hardware Description Languages (APCHDL'96), Bengalore, INDIA, 8 au 10 janvier 1996
 
68 Wahba A., Borrione D., Design error diagnosis in sequential circuits, Correct Hardware Design and Verification Methods Conference (CHARME '95), pp. 171-188, Frankfurt/Main, GERMANY, 2 au 4 octobre 1995
 
69 Deharbe H., Borrione D., Semantics of a verification-oriented subset of VHDL, Correct Hardware Design and Verification Methods Conference (CHARME '95), pp. 293-310, Frankfurt/Main, GERMANY, 2 au 4 octobre 1995
 
70 Bayol C., Soulas B., Corno F., Prinetto P., Borrione D., A process algebra interpretation of a verification oriented overlanguage of VHDL, IEEE EURO DAC '94 with EURO VHDL '94 , pp. 506-511, Grenoble, FRANCE, 19 au 23 septembre 1994
 
71 Claesen L., Borrione D., Eveking H., Milne G., Paillet J.-L., Prinetto P., CHARME: towards formal design and verification for provably correct VLSI hardware, Advanced Research Workshop on Correct Hardware Design Methodologies, pp. 3-25, Turin, ITALY, 12 au 14 juin 1992
 
72 Borrione D., Pierre L., Salem A., PREVAIL: a proof environment for VHDL descriptions, Advanced Research Workshop on Correct Hardware Design Methodologies, pp. 163-186, Turin, ITALY, 12 au 14 juin 1992
 
73 Salem A., Borrione D., Formal semantics of VHDL timing constructs, Second European Conference on VHDL Methods, pp. 276-281, Stockholm, FRANCE, 8 au 11 septembre 1991
 
74 Borrione D., Deharbe H., Eveking H., Horeth S., Application of a BDD-package to the verification of HDL descriptions, Advanced Research Workshop on Correct Hardware Design Methodologies, pp. 385-400, Turin, ITALY, 12 au 14 juin 1991
 
75 Salem A., Borrione D., Formal reasoning about signal attributes in VHDL, VHDL Forum for CAD in Europe, Marseille, FRANCE, 24 au 26 avril 1991
 
76 Borrione D., Collavizza H., Le Faou C., muSPEED : a framework for specifying and verifying microprocessors, Internatiolan Workshop on Formal Methods in VLSI Design, Miami, UNITED STATES, 9 au 11 janvier 1991
 
77 Collavizza H., Borrione D., Specifying the micro-program parallelism for microprocessors of the Von Neumann style, Workshop on Designing Correct Circuits, Oxford, ENGLAND, 26 au 28 septembre 1990
 
78 Borrione D., Pierre L., Salem A., Formal verification of VHDL descriptions in Boyer-Moore: first results, First European Working Conference on VHDL methods, Marseille, FRANCE, 4 au 7 septembre 1990
 
79 Salem A., Borrione D., Automatic proof of bit-level VHDL descriptions with TACHE, VHDL Forum for CAD in Europe, Grassau, GERMANY, 1 au 4 mai 1990
 
80 Borrione D., Camurati P., Paillet J.-L., Prinetto P., Formal verification of microprogrammed architectures, International Conference on Computer Aided Design and Computer Graphics (CAD & CG'89), pp. 562-7, Beijing, CHINA, 5 au 9 novembre 1989
 
81 Borrione D., Prinetto P., Zero-defect designs, why and how: formal verification vs. automated synthesis, IFIP 11th World Computer Congress on Information Processing 89, pp. 233-240, San Francisco, CA, UNITED STATES, 28 août au 1 septembre 1989
 
82 Borrione D., Camurati P., Paillet J.-L., Prinetto P., A functional approach to formal hardware verification: the MTI experience, IEEE International Conference on Computer Design (ICCD'88), Rye Brook, N.Y., UNITED STATES, 3 au 5 octobre 1988
 
83 Borrione D., Paillet J.-L., Pierre L., Formal verification of CASCADE descriptions, International Working Conference on the fusion of hardware design and verification, Glasgow, Scotland, ENGLAND, 16 juillet 1988
 
84 Borrione D., Digital circuits specification language, 2nd International Conference on Computer Applications in Production and Engineering (CAPE'86), pp. 555-574 , Copenhagen, NETHERLANDS, 20 au 23 mai 1986
 
85 Borrione D., Le Faou C., Overview of the CASCADE Multilevel Hardware Description Language and its Mixed-Mode Simulation Mechanisms, 7th International Conference on Computer Hardware Description Languages and their Applications (CHDL'85), pp. 239-260, Tokyo, JAPAN, 1 août 1985
 
86 Borrione D., Prinetto P., TPDL: a Temporal Profile Description Language, Workshop on Hardware Design Verification, Darmstadt, GERMANY, 26 au 27 novembre 1984
 
87 Battistoni G., Borrione D., Mermet J., Prinetto P., A time profile description language for system , International Conference on Computer Aided Design (CAD'84), pp. 99 p., Nice, FRANCE, 19 au 21 juin 1984
 
88 Borrione D., Humbert M., Le Faou C., Hierarchical mixed-mode simulation mechanisms in the CASCADE project, International Conference on Very Large Scale Integration (VLSI-SOC'83), pp. 119-129, Trondheim, NORWAY, 1 janvier 1983
 
89 Piloty R., Borrione D., The CONLAN project: status and future plans, ACM IEEE Nineteenth Design Automation Conference Proceedings., pp. 202-12, Las Vegas, Nevada, UNITED STATES, DOI: 10.1109/DAC.1982.1585501, 14 au 16 juin 1982
 
90 Borrione D., The worker model of evaluation for computer hardware description languages, Fifth International Conference on Computer Hardware Description Languages and Their Applications, pp. 3-21, Kaiserslautern, GERMANY, 7 au 9 septembre 1981
 
91 Piloty R., Barbacci M., Borrione D., Dietmeyer D., Hill F., Skelly P., An overview of CONLAN: a formal construction method for hardware description languages, Information Processing 80, pp. 199-204, Tokyo, JAPAN, 6 au 8 octobre 1980
 
92 Piloty R., Barbacci M., Borrione D., Dietmeyer D., Hill F., Skelly P., CONLAN-a formal construction method for hardware description languages: basic principles, AFIPS Conference Proceedings. 1980 National Computer Conference., pp. 209-17, Anaheim, California, UNITED STATES, 19 au 22 mai 1980
 
93 Piloty R., Barbacci M., Borrione D., Dietmeyer D., Hill F., Skelly P., CONLAN-a formal construction method for hardware description languages: language application, AFIPS Conference on National Computer Conference , pp. 229-236, Anaheim, California, UNITED STATES, 19 au 22 mai 1980
 
94 Piloty R., Barbacci M., Borrione D., Dietmeyer D., Hill F., Skelly P., CONLAN-a formal construction method for hardware description languages: language derivation, AFIPS Conference Proceedings. 1980 National Computer Conference., pp. 219-27, Anaheim, California, UNITED STATES, 19 au 22 mai 1980
 
95 Borrione D., Grabowiecki J.F., Informal introduction to LASSO: a Language for Asynchronous System Specification and simulation, European Conference on Applied Information Technology of the International Federation for Information Processing (Euro IFIP'79), Londres, ENGLAND, 25 au 28 septembre 1979
 
96 Borrione D., Le Faou C., Teaching construction and use of CAD tools for electronic and logic systems to computer science students, International conference and exhibition on computer aided design education (CAD'77), Middlesbrough, ENGLAND, 13 au 15 juillet 1977
 
97 Borrione D., LASCAR: a language for simulation of computer architecture, International Symposium on Computer Hardware Description Languages and their Applications, pp. 143-152, New York, N.Y., UNITED STATES, 3 au 5 septembre 1975
 
98 Borrione D., System analysis by typology, International Symposium on Operating Systems, pp. 30-55, Rocquencourt, FRANCE, 23 au 25 avril 1974
 
remonter

27 Chapitres de livre

 1 Plassan G., Peter H.J., Morin-Allory K., Sarwary S., Borrione D., Improving the Efficiency of Formal Verification: The Case of Clock-Domain Crossings, VLSI-SoC: System-on-Chip in the Nanoscale Era – Design, Verification and Reliability, revised selected contributions from 24th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2016, Hollstein T., Raik J., Kostin S., Tšertov A., O'Connor I., Reis R (Eds.) , Ed. Springer , pp. 108-129, Vol. 508, DOI: 10.1007/978-3-319-67104-8, 2017
 
 2 Borrione D., Morin-Allory K., Oddos Y., Property-Based Dynamic Verification and Test, Design Technology for Heterogeneous Embedded Systems, G. Nicolescu, I. O'Connor, C. Piguet (Eds.) , Ed. Springer , pp. 157-176, DOI: DOI:10.1007/978-94-007-1125-9_8, 2012
 
 3 Oddos Y., Morin-Allory K., Borrione D., From Assertion-based Verification to Assertion-based Synthesis, VLSI-SOC: Technologies for Systems Integration" (revised selected contributions from VLSI-SOC'09), J. Becker, M. Johann & R. Reis (Eds.) , Ed. Springer , pp. , Vol. AICT N° 360, 2011
 
 4 Borrione D., Helmy A., Pierre L., Schmaltz J., Formal Verification of Communications in Networks-on-Chip, Networks-on-Chips: Theory and Practice, F. Gebali, H. Elmiligi and M. Watheq El-Kharashi (Eds.) , Ed. taylor & francis group, pp. 250 p., 2009
 
 5 Morin-Allory K., Fesquet L., Roustan B., Borrione D., Asynchronous online monitoring of logical and temporal assertions, Embedded Systems Specification and Design Languages, Villar Eugenio (Eds.) , Ed. Springer , pp. 278 p, 2008
 
 6 Morin-Allory K., Borrione D., On-line monitoring of properties built on regular expressions sequences, Advances in Design and Specification Languages for Embedded Systems (Selected Contributions from FDL'06), Sorin A. Huss (Eds.) , Ed. Springer , pp. 197-207, DOI: doi 10.1007/978-1-4020-6149-3_12, 2007
 
 7 Borrione D., Liu M., Ostier P., Fesquet L., PSL-based online monitoring of digital systems, Advances in Design and Specification Languages for SoCs (revised selected contributions from FDL'05), Vachoux A (Eds.) , Ed. Springer , pp. 5-22, 2006
 
 8 Borrione D., Boubekeur M., Mounier L., Renaudin M., Sirianni A., Validation of Asynchronous Circuit Specifications Using IF/CADP, VLSI-SOC: From Systems to Chips, Manfred Glesner, Ricardo Reis, Leandro Indrusiak, Vincent Mooney and Hans Eveking (Eds.) , Ed. Springer , pp. 85-100, DOI: 10.1007/0-387-33403-3, 2006
 
 9 Schmaltz J., Borrione D., A Generic Network on Chip Model, Theorem Proving in Higher Order Logics, 18th International Conference, TPHOLs 2005, Oxford, UK, August 22-25, 2005, Proceedings, Hurd Joe, Melham Tom (Eds.) , Ed. Springer , pp. 310-325, Vol. 3603, 2005
 
10 Al Sammane G., Borrione D., Toma D., Combining several paradigms for circuit validation and verification, Construction and Analysis of Safe, Secure, and Interoperable Smart Devices. International Workshop, CASSIS 2004.Revised Selected Papers., Barthe, G.; Burdy, L.; Huisman, M.; Lanet, J.-L.; Muntean, T. (Eds.) , Ed. Springer , pp. 229-249, Vol. 3362, DOI: 10.1007/b105030, 2005
 
11 Toma D., Borrione D., Formal Verification of a SHA-1 Circuit Core Using ACL2, Theorem Proving in Higher Order Logics: 18th International Conference, TPHOLs 2005. , Ed. Springer , pp. 326, DOI: 10.1007/11541868_21, 2005
 
12 Boubekeur M., Borrione D., Mounier L., Sirianni A., Renaudin M., Modeling CHP descriptions in labeled transitions systems for an efficient formal validation of asynchronous circuit specification, Languages for System Specification, Selected Contributions on UML, SystemC, System Verilog, Mixed-Signal Systems and Property Specifications from FDL'03, Christoph Grimm (Eds.) , Ed. Kluwer Academic Publishers, pp. , 2004
 
13 Schmaltz J., Borrione D., A functional approach to the formal specification of networks on chip, Formal Methods in Computer Aided Design, 5th International Conference, FMCAD 2004, Hu Alan J., Martin Andrew K. (Eds.) , Ed. Springer , pp. 52-66, Vol. 3312, DOI: 10.1007/b102264, 2004
 
14 Al Sammane G., Toma D., Schmaltz J., Ostier P., Borrione D., Constrained Symbolic Simulation with Mathematica and ACL2, Correct Hardware Design and Verification Methods, 12th IFIP WG 10.5 Advanced Research Working Conference, CHARME 2003, L'Aquila, Italy, October 21-24, 2003, Proceedings, Geist Daniel, Tronci Enrico (Eds.) , Ed. Springer , pp. 150-157, Vol. 2860, DOI: 10.1007/978-3-540-39724-3_14, 2003
 
15 Borrione D., La simulation et les méthodes de vérification formelle, Conception de haut niveau des systèmes monopuces (Traité EGEM, Série électronique et micro-électronique), Ed. Hermès, pp. chapitre 5: 139-174, 2002
 
16 Borrione D., Georgelin P., Rodrigues V.M., Symbolic Simulation and Verification of VHDL with ACL2, System-on-Chip Methodologies and Design Languages, Jean Mermet (Eds.) , Ed. Kluwer Academic Publishers, pp. , 2001
 
17 Borrione D., Georgelin P., Formal verification of VHDL using VHDL-like ACL2 models, Electronic Chips & Systems Design Languages, Ed. Kluwer Academic Publishers, pp. Partie III: chapitre 23, 2001
 
18 Borrione D., Georgelin P., Rodrigues V.M., Using macros to mimic VHDL in ACL2, Computer-Aided Reasoning: ACL2 Case Studies, Ed. Kluwer Academic Publishers, pp. 162-185, 2000
 
19 Deharbe D., Borrione D., Symbolic Model Checking with Past and Future Temporal Modalities: Fundamentals and Algorithms, Model Generation in Electronic Design, Bergé J.M., Levia O., Rouillard J. (Eds.) , Ed. Springer , pp. 105-126, 1995
 
20 Borrione D., CASCADE, Fundamentals and Standards in Hardware Description Languages, Jean Mermet (Eds.) , Ed. Kluwer Academic Publishers, pp. 413-430, 1993
 
21 Borrione D., Piloty R., CONLAN: presentation of basic principles, applications and relation to VHDL, Fundamentals and Standards in Hardware Description Languages, Jean Mermet (Eds.) , Ed. Kluwer Academic Publishers, pp. 39-78, 1993
 
22 Borrione D., Eveking H., Pierre L., Formal proofs from HDL descriptions, Fundamentals and Standards in Hardware Description Languages, Jean Mermet (Eds.) , Ed. Kluwer Academic Publishers, pp. 155-194, 1993
 
23 Salem A., Borrione D., Formal Semantics of VHDL Timing Constructs, VHDL for Simulation, Synthesis and Formal Proofs of Hardware, J. Mermet (Eds.) , Ed. Kluwer Academic Publishers, pp. 195-206, 1992
 
24 Borrione D., Pierre L., Salem A., Formal Verification of VHDL Description in Boyer-Moore: First results, VHDL for Simulation, Synthesis and Formal Proofs of Hardware, Ed. Kluwer Academic Publishers, pp. 227-244, 1992
 
25 Borrione D., Salem A., Proving an on-line multiplier with OBJ3 and TACHE: a practical experience, Formal VLSI Correctness Verification, L. Claesen (Eds.) , Ed. North Holland, pp. , 1990
 
26 Borrione D., Le Faou C., Implementation Techniques for Multi-level Hardware Description Languages, Hardware Description Languages, R.W. Hartenstein (Eds.) , Ed. Elsevier, pp. , Vol. 7, 1987
 
27 Borrione D., Piloty R., The CONLAN Project: Concepts, Implementations and Applications, Hardware Description Languages, R.W. Hartenstein (Eds.) , Ed. Elsevier, pp. , Vol. 7, 1987
 
remonter

6 Livres & Éditions Ouvrages

1 Borrione D. (Eds.) Advances in Design Methods from Modeling Languages for Embedded Systems and SoC's, Selected Contributions on Specification, Design, and Verification from FDL 2009, Lecture Notes in Electrical Engineering, Vol.63, pp. 246 p., Ed. Springer , 2010
 
2 Borrione D., Paul W. (Eds.) Correct Hardware Design and Verification Methods, Lecture Notes in Computer Science , Vol. 3725 , pp. 412 p., Ed. Springer , 2005
 
3 Borrione D., Ernst R. (Eds.) Design Automation and Test in Europe - DATE'99, Ed. IEEE, 1999
 
4 Borrione D., Waxman R. (Eds.) Computer Hardware Description Languages and their Applications, Ed. North Holland, 1991
 
5 Borrione D. (Eds.) From H.D.L. Description to Guaranteed Correct Circuit Designs, Ed. North Holland, 1986
 
6 Barbacci M., Borrione D., Dietmeyer D., Hill F., Piloty R., Skelly P. (Eds.) CONLAN Project, Lectures Notes in Computer Science (LNCS), n°151, pp. 171 p., Ed. Springer , 1983
 
remonter

3 Revues nationales

1 Rodrigues V.M., Borrione D., Georgelin P., Using the ACL2 theorem prover to reason about VHDL components, Revista de Informatica Teorica e Aplicada, Ed. Instituto de Informática da Universidade Federal do Rio Grande do Sul, Vol. 7, No. 1, septembre 2000
 
2 Ubar R., Borrione D., Single gate design error diagnosis in combinational circuits, Proceedings of the Estonian Academy of Sciences Engineering, Vol. 5, No. 1, pp. 3-21, mars 1999
 
3 Borrione D., Paillet J.-L., Pierre L., Collavizza H., Functional modelling and testing of digital circuits, Technique et Science Informatiques (TSI), Vol. 8, No. 6, pp. 523-544, juin 1989
 
remonter

5 Conférences nationales

1 Borrione D., Paillet J.-L., Pierre L., Modélisation et Vérification Formelle des Circuits Digitaux: un état des recherches actuelles, Internationale Conférence "Identification, Modelling and Simulation", Paris, FRANCE, 1 juin 1987
 
2 Borrione D., Paillet J.-L., Preuve formelle et simulation à partir d'une description en CASCADE: Techniques complémentaires pour la validation de circuits, Internationale Conférence "Identification, Modelling, and Simulation", Paris, FRANCE, 1 juin 1987
 
3 Borrione D., Formation à la C.F.A.O. à l'E.N.S.I.M.A.G., MICAD-FORMATION 83, Paris, FRANCE, 16 au 19 mai 1983
 
4 Borrione D., Définition de langages de description de systèmes (CONLAN), Congrès AFCET Informatique 1982 "Architecture des Machines et Systèmes Informatiques", Lille, FRANCE, 17 au 19 novembre 1982
 
5 Borrione D., Bressy Y., Grabowiecki J.F., Mermet J., Méthodes et langages pour la modélisation et l'aide à la conception des systèmes logiques, Congrès AFCET, pp. 569-580, Versailles, FRANCE, 1 novembre 1977
 
remonter

5 Autres communications

1 Bel Hadj Amor Z., Borrione D., Javaheri N., Morin-Allory K., Pierre L., Design Understanding - At What Abstraction Level is the Pain Most Intense?, Workshop on Design Automation for Understanding Hardware Designs (DUHDe Friday Workshop DATE 2015), Grenoble, FRANCE, 2015
 
2 Morin-Allory K., Javaheri N., Borrione D., Design Understanding with Fast Prototyping from Assertions, Workshop on Design Automation for Understanding Hardware Designs (Friday Workshop DATE'14), Dresden, GERMANY, 2014
 
3 Borrione D., Fast Prototyping from Assertions, Ecole d'hiver Francophone sur les Technologies de Conception des Systèmes embarqués Hétérogènes (FETCH'14), Ottawa, CANADA, 2014
 
4 Claesen L., Borrione D., Eveking H., Paillet J.-L., Prinetto P., Turning the formal verification of VLSI hardware into reality, ESPRIT Conference 1991, Bruxelles, BELGIUM, 1991
 
5 Borrione D., VHDL activities in France, and the ECIP2 project, VHDL Users Workshop, Washington, DC, UNITED STATES, 1989
 
remonter

13 Rapports

 1 Schmaltz J., Borrione D., Towards a Formal Theory of On Chip Communications, ISRN: TIMA-RR--06/09-01--FR, 1 janvier 2006
 
 2 Schmaltz J., Borrione D., A Generic Network on Chip Model, ISRN: TIMA-RR--05/03-06--FR, 1 janvier 2005
 
 3 Schmaltz J., Borrione D., Al Sammane G., Design and Formal Verification of Networks On Chip, ISRN: TIMA-RR--05/12-01--FR, 1 janvier 2005
 
 4 Schmaltz J., Borrione D., A functionnal approach to the formal specification of networks on chip, ISRN: TIMA-RR--04/04-01--FR, 1 janvier 2004
 
 5 Toma D., Al Sammane G., Borrione D., Combining several paradigms for circuit validation and verification , ISRN: TIMA-RR--04/07-01--FR, 1 janvier 2004
 
 6 Borrione D., Dumitrescu E., Rigaud J.B., Boubekeur M., Renaudin M., Sirianni A., An approach to the introduction of formal validation in an asynchronous circuit design flow, ISRN: TIMA-RR--03/10-01--FR, 1 janvier 2003
 
 7 Al Sammane G., Schmaltz J., Borrione D., Toma D., Ostier P., A Shortened Form of Constrained Symbolic Simulation with Mathematica and ACL2, ISRN: TIMA--RR-03/10-05--FR, 1 janvier 2003
 
 8 Toma D., Ostier P., Al Sammane G., Schmaltz J., Borrione D., Constrained Symbolic Simulation with Mathematica and ACL2, ISRN: TIMA-RR--03/07-03--FR, 1 janvier 2003
 
 9 Schmaltz J., Borrione D., Formalization and verification of the AMBA AHB communication architecture using the ACL2 theorem prover, ISRN: TIMA-RR--03/03-01--FR, 1 janvier 2003
 
10 Schmaltz J., Borrione D., Formalization and verification of the MBA AHB communication architecture using the ACL2 theorem prover, ISRN: TIMA--RR-03/10-02--FR, 1 janvier 2003
 
11 Borrione D., Mounier L., Sirianni A., Boubekeur M., Renaudin M., Modeling CHP descriptions in Labeled Transitions Systems for an efficient formal validation of asynchronous circuit specifications, ISRN: TIMA--RR-03/10-04--FR, 1 janvier 2003
 
12 Borrione D., Toma D., SHA Formalization, ISRN: TIMA-RR--03/10-06--FR, 1 janvier 2003
 
13 Schmaltz J., Borrione D., Verification of a parameterized bus architecture using ACL2, ISRN: TIMA--RR-03/10-03--FR, 1 janvier 2003
 
remonter

1 Logiciels

1 Borrione D., Ferro L., Fesquet L., Morin-Allory K., Oddos Y., Pierre L., Logiciel, Logiciel, 9 mai 2009
 
remonter