Publications

Publications

Recherche

Recherche

Auteur
hors TIMA
Équipe :

Mot clé
Type de publications
Tous
Sélectionne/déselectionne tous les types de publications
Journal art.
International National Tous
 Brevets  Conférences invitées
Conference art.
International National Tous
Chapitres de livre  Livres & Éditions Ouvrages
 Autres communications
 Logiciels  Thèses
 
 année
 

61 résultats

   5 Revues internationales
  35 Conférences internationales
   6 Chapitres de livre
   1 Revues nationales
   4 Conférences nationales
   5 Autres communications
   1 Rapports
   4 Logiciels

5 Revues internationales

1 Pierre L., Auxiliary Variables in Temporal Specifications: Semantic and Practical Analysis for System-Level Requirements, Transactions on Design Automation of Electronic Systems (TODAES), Ed. ACM, NY, USA, Vol. 21, No. 2, pp. Article n°20, DOI: 10.1145/2811260, janvier 2016
 
2 Borrione D., Helmy A., Pierre L., Schmaltz J., A Formal Approach to the Verification of Networks on Chip, EURASIP Journal on Embedded Systems, Ed. Hindawi Publishing Corporation, Vol. 2009, No. Article ID 548324, pp. 14, DOI: 10.1155/2009/548324, 2009
 
3 Pierre L., Ferro L., A Tractable and Fast Method for Monitoring SystemC TLM Specifications , IEEE Transactions on Computers, Ed. IEEE, Vol. Vol. 57, No. 10, pp. 1346-1356, DOI: : http://doi.ieeecomputersociety.org/10.1109/TC.2008.74, janvier 2008
 
4 Borrione D., Dusina J., Pierre L., A compositional model for the functional verification of high-level synthesis results, Transactions on Very Large Scale Integration (VLSI) Systems, Ed. IEEE, Vol. 8, No. 5, pp. 526-30, DOI: 10.1109/92.894157, octobre 2000
 
5 Borrione D., Pierre L., Salem A., Formal verification of VHDL descriptions in the PREVAIL environment, IEEE Design and Test of Computers, Ed. IEEE, Vol. 9, No. 2, pp. 42-56, DOI: 10.1109/54.143145, juin 1992
 
remonter

35 Conférences internationales

 1 Brignon E., Pierre L., Assertion-Based Verification through Binary Instrumentation, Design, Automation and Test in Europe (DATE'2019), Florence, ITALY, 25 au 29 mars 2019
 
 2 Chabot M., Pierre L., Nabais-Moreno A., Automated Testing for Cyber-physical Systems: From Scenarios to Executable Tests, Forum on specification & Design Languages (FDL'2018), Munich, GERMANY, 10 au 12 septembre 2018
 
 3 Pierre L., Chabot M., Assertion-Based Verification for SoC Models and Identification of Key Events, Euromicro Conference on Digital System Design (DSD 2017), Vienna, AUSTRIA, 30 août au 1 septembre 2017
 
 4 Chabot M., Pierre L., Nabais-Moreno A., A Requirement Driven Testing Method for Multi-disciplinary System Design, ACM/IEEE International Conference on Model Driven Engineering Languages and Systems (MODELS'2016), Saint-Malo, FRANCE, 2 au 23 octobre 2016
 
 5 Chabot M., Mazet K., Pierre L., Automatic and Configurable Instrumentation of C Programs with Temporal Assertion Checkers, 13th ACM-IEEE International Conference on Formal Methods and Models for System Design (MEMOCODE’2015), Austin, Texas, UNITED STATES, 21 au 23 septembre 2015
 
 6 Pierre L., Towards a Toolchain for Assertion-Driven Test Sequence Generation, Forum on specification & Design Languages (FDL’2015), Barcelona, SPAIN, 14 au 16 septembre 2015
 
 7 Bel Hadj Amor Z., Pierre L., Borrione D., A Tool for the Automatic TLM-to-RTL Conversion of Embedded Systems Requirements for a Seamless Verification Flow, International Conference on Very Large Scale Integration (VLSI-SoC'14), pp. 1-6, Playa del Carmen, Mexico, MEXICO, DOI: 10.1109/VLSI-SoC.2014.7004196, 6 au 8 octobre 2014
 
 8 Chabot M., Pierre L., A Customizable Monitoring Infrastructure for Hardware/Software Embedded Systems, Proc. 26th IFIP International Conference on Testing Software and Systems (ICTSS'2014), pp. 173-179, Madrid, SPAIN, DOI: 10.1007/978-3-662-44857-1_12, 23 au 25 septembre 2014
 
 9 Bel Hadj Amor Z., Pierre L., Borrione D., System-on-Chip Verification: TLM-to-RTL Assertions Transformation, 10th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME'14), pp. 1-4, Grenoble, FRANCE, DOI: 10.1109/PRIME.2014.6872713, 30 juin au 3 juillet 2014
 
10 Pierre L., Bel Hadj Amor Z., Automatic Refinement of Requirements for Verification throughout the SoC Design Flow, International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS'13), pp. 1-10, Montreal, CANADA, DOI: 10.1109/CODES-ISSS.2013.6659016 , 29 septembre au 4 octobre 2013
 
11 Pierre L., Pancher F., Suescun R., Quévremont J., On the Effectiveness of Assertion-Based Verification in an Industrial Context, 18th International Workshop on Formal Methods for Industrial Critical Systems (FMICS'13), pp. 78-93 , Madrid, SPAIN, DOI: 10.1007/978-3-642-41010-9_6, 23 au 24 septembre 2013
 
12 Pierre L., A Formal Framework for Testing with Assertion Checkers in Mixed-Signal Simulation, IEEE International Conference on Electronics, Circuits, and Systems (ICECS'2012), pp. 284 - 287 , Seville, SPAIN, DOI: 10.1109/ICECS.2012.6463745, 9 au 12 décembre 2012
 
13 Pierre L., Ferro L., Bel Hadj Amor Z., Bourgon P., Quévremont J., Integrating PSL Properties into SystemC Transactional Modeling - Application to the Verification of a Modem SoC, IEEE International Symposium on Industrial Embedded Systems (SIES'2012), Karlsruhe, GERMANY, 20 au 22 juin 2012
 
14 Tsiligiannis G., Pierre L., A Mixed Verification Strategy Tailored for Networks on Chip, Sixth IEEE/ACM International Symposium on Networks on Chip (NoCS'12), pp. 161 - 168 , Copenhagen, DENMARK, DOI: 10.1109/NOCS.2012.26 , 9 au 11 mai 2012
 
15 Pierre L., Damri L., Improvement of Assertion-Based Verification through the Generation of Proper Test Sequences, Forum on specification & Design Languages (FDL'11), pp. 1-8, Oldenburg, GERMANY, 13 septembre 2011
 
16 Ferro L., Pierre L., Bel Hadj Amor Z., Lachaize J., Lefftz V., Runtime Verification of Typical Requirements for a Space Critical SoC Platform, 16th International Workshop on Formal Methods for Industrial Critical Systems (FMICS’11), pp. 21-36, Trento, ITALY, DOI: 10.1007/978-3-642-24431-5_4, 29 au 30 août 2011
 
17 Clavel R., Pierre L., Leveugle R., Towards Robustness Analysis using PVS, Conference on Interactive Theorem Proving (ITP’11), pp. 71-86, Nijmegen, NETHERLANDS, DOI: 10.1007/978-3-642-22863-6_8, 22 au 25 août 2011
 
18 Pierre L., Ferro L., Enhancing the assertion-based verification of TLM designs with reentrancy, 8th IEEE/ACM International Conference Formal Methods and Models for Codesign (MEMOCODE'10), pp. 103 - 112 , Grenoble, FRANCE, DOI: 10.1109/MEMCOD.2010.5558642 , 26 au 28 juillet 2010
 
19 Lefftz V., Bertrand J., Cassé H., Clienti C., Coussy P., Maillet-Contoz L., Mercier P., Moreau P., Pierre L., Vaumorin E., A Design Flow for Critical Embedded Systems, IEEE Symposium on Industrial Embedded Systems (SIES’10), pp. 229 - 233, Trento, ITALY, DOI: 10.1109/SIES.2010.5551393 , 7 au 9 juillet 2010
 
20 Helmy A., Pierre L., Jantsch A., Theorem proving techniques for the formal verification of NoC communications with non-minimal adaptive routing, Symposium on Design and Diagnostics of Electronic Systems (DDECS'10), pp. 221 - 224 , Vienna , AUSTRIA, DOI: 10.1109/DDECS.2010.5491781 , 14 au 16 avril 2010
 
21 Ferro L., Pierre L., Formal Semantics for PSL Modeling Layer and Application to the Verification of Transactional Models , Design, Automation and Test in Europe (DATE'10), pp. 1207-1212, Dresden , GERMANY, 9 au 11 mars 2010
 
22 Baarir S., Braunstein C., Clavel R., Encrenaz E., Ilié J.-M., Leveugle R., Mounier I., Pierre L., Poitrenaud D., Complementary formal approaches for dependability analysis, International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'09), pp. 331-339, Chicago, Illinois, UNITED STATES, DOI: 10.1109/DFT.2009.21, 7 au 9 octobre 2009
 
23 Ferro L., Pierre L., ISIS: Runtime Verification of TLM Platforms, Forum on specification & Design Languages (FDL'09), pp. 1-6, Nice Sophia-Antipolis, FRANCE, 22 au 24 septembre 2009
 
24 Pierre L., Clavel R., Leveugle R., ACL2 for the Verification of Fault-Tolerance Properties: First Results, International Workshop on The ACL2 Theorem Prover and Its Applications, pp. 90-99, Boston, MA., UNITED STATES, 11 au 12 mai 2009
 
25 Ouchet F., Borrione D., Morin-Allory K., Pierre L., High-level symbolic simulation for automatic model extraction, IEEE Symposium on Design and Diagnostics of Electronic Systems (DDECS’09), pp. 218-221, Liberec, CZECH REPUBLIC, DOI: 10.1109/DDECS.2009.5012132, 15 au 17 avril 2009
 
26 Leveugle R., Pierre L., Maistri P., Clavel R., Soft Error Effect and Register Criticality Evaluations: Past, Present and Future, Workshop on Silicon Errors in Logic - System Effects (SELSE’09), pp. 15-20 , Stanford, Ca., UNITED STATES, 24 au 25 mars 2009
 
27 Ferro L., Pierre L., Ledru Y., Du Bousquet L., Generation of Test Programs for the Assertion-Based Verification of TLM Models, IEEE International Design and Test Workshop (IDT'08), pp. 237-242, Monastir, TUNISIA, 20 au 21 décembre 2008
 
28 Borrione D., Helmy A., Pierre L., Schmaltz J., Executable Formal Specification and Validation of NoC Communication Infrastructures, Proc. of 21st Symposium on Integrated Circuits and Systems Design (SBCCI’08), pp. 176-181, Gramado, BRAZIL, DOI: 10.1145/1404371.1404421, 1 au 4 septembre 2008
 
29 Borrione D., Helmy A., Pierre L., Schmaltz J., A Generic Model for Formally Verifying NoC Communication Architectures: A Case Study, ACM/IEEE International Symposium on Networks-on-Chips (NOCS'2007), pp. 127-136, Princeton, NJ, UNITED STATES, DOI: 10.1109/NOCS.2007.1, 7 au 9 mai 2007
 
30 Borrione D., Helmy A., Pierre L., ACL2-based verification of the communications in the hermes network on chip, International Workshop on Symbolic Methods and Applications to Circuit Design (SMACD'06), pp. 1-6, Firenze, ITALY, 12 au 13 octobre 2006
 
31 Georgelin P., Pierre L., Nguyen T., A formal approach for the specification of communications in distributed systems, ISCA 13th International Conference on Parallel and Distributed Computing Systems (PDCS'00), Las Vegas, Nevada, UNITED STATES, 8 au 10 août 2000
 
32 Borrione D., Dusina J., Pierre L., Formalization of finite state machines with data path for the verification of high-level synthesis, XI Brazilian Symposium on Integrated Circuit Design (SBCCI'98), pp. 99-102, Rio de Janeiro, BRAZIL, DOI: 10.1109/SBCCI.1998.715419, 30 septembre au 2 octobre 1998
 
33 Borrione D., Pierre L., Salem A., PREVAIL: a proof environment for VHDL descriptions, Advanced Research Workshop on Correct Hardware Design Methodologies, pp. 163-186, Turin, ITALY, 12 au 14 juin 1992
 
34 Borrione D., Pierre L., Salem A., Formal verification of VHDL descriptions in Boyer-Moore: first results, First European Working Conference on VHDL methods, Marseille, FRANCE, 4 au 7 septembre 1990
 
35 Borrione D., Paillet J.-L., Pierre L., Formal verification of CASCADE descriptions, International Working Conference on the fusion of hardware design and verification, Glasgow, Scotland, ENGLAND, 16 juillet 1988
 
remonter

6 Chapitres de livre

1 Pierre L., Ferro L., Dynamic Verification of SystemC Transactional Models, Model-Based Testing for Embedded Systems , Justyna Zander, Ina Schieferdecker, Pieter J. Mosterman (Eds.) , Ed. CRC Press, pp. Chapter 22, DOI: http://www.crcpress.com/product/isbn/9781439818459, 2011
 
2 Ferro L., Pierre L., ISIS: Runtime Verification of TLM Platforms, Advances in Design Methods from Modeling Languages for Embedded Systems and SoC's (Selected Contributions from FDL'09), Ed. Springer , pp. 213-226, 2010
 
3 Borrione D., Helmy A., Pierre L., Schmaltz J., Formal Verification of Communications in Networks-on-Chip, Networks-on-Chips: Theory and Practice, F. Gebali, H. Elmiligi and M. Watheq El-Kharashi (Eds.) , Ed. taylor & francis group, pp. 250 p., 2009
 
4 Pierre L., VHDL, Software Specification Methods - An overview using a case study, M. Frappier and H. Habrias (Eds.) , Ed. International Scientific and Technical Encyclopedia (ISTE), pp. chapter 10 - pp.179-196, 2006
 
5 Borrione D., Eveking H., Pierre L., Formal proofs from HDL descriptions, Fundamentals and Standards in Hardware Description Languages, Jean Mermet (Eds.) , Ed. Kluwer Academic Publishers, pp. 155-194, 1993
 
6 Borrione D., Pierre L., Salem A., Formal Verification of VHDL Description in Boyer-Moore: First results, VHDL for Simulation, Synthesis and Formal Proofs of Hardware, Ed. Kluwer Academic Publishers, pp. 227-244, 1992
 
remonter

1 Revues nationales

1 Borrione D., Paillet J.-L., Pierre L., Collavizza H., Functional modelling and testing of digital circuits, Technique et Science Informatiques (TSI), Vol. 8, No. 6, pp. 523-544, juin 1989
 
remonter

4 Conférences nationales

1 Pierre L., Chabot M., Customization of the Runtime Verification of Hardware Software Virtual Platforms in ISIS, Forum on specification & Design Languages (FDL'2014), Munich, GERMANY, 14 au 16 octobre 2014
 
2 Helmy A., Pierre L., Formal Verification of the Communications in Networks on Chips, 2ème Colloque du GdR SoC-SiP, Paris, FRANCE, 4 au 6 juin 2008
 
3 Clavel R., Pierre L., Leveugle R., Premiers résultats sur l'utilisation d'ACL2 pour l'évaluation de la conséquence des erreurs logiques, 2ème Colloque du GdR SoC-SiP, Paris, FRANCE, 4 au 6 juin 2008
 
4 Borrione D., Paillet J.-L., Pierre L., Modélisation et Vérification Formelle des Circuits Digitaux: un état des recherches actuelles, Internationale Conférence "Identification, Modelling and Simulation", Paris, FRANCE, 1 juin 1987
 
remonter

5 Autres communications

1 Bel Hadj Amor Z., Borrione D., Javaheri N., Morin-Allory K., Pierre L., Design Understanding - At What Abstraction Level is the Pain Most Intense?, Workshop on Design Automation for Understanding Hardware Designs (DUHDe Friday Workshop DATE 2015), Grenoble, FRANCE, 2015
 
2 Pierre L., Runtime Verification of Embedded Systems Requirements throughout the Design Flow, Ecole d'hiver Francophone sur les Technologies de Conception des Systèmes embarqués Hétérogènes (FETCH'2015), Louvain-La-Neuve , BELGIUM, 2015
 
3 Pierre L., Outils de démonstration automatique et preuve de circuits électroniques, Forum Méthodes Formelles "Preuve de modèle, preuve de programme" (Aerospace Valley - Minalogic), Toulouse, FRANCE, 2014
 
4 Pierre L., Assertion-Based Verification for the validation and safety analysis of hardware/software systems on chip, TORRENTS Working day (RTRA Sciences et Technologies pour l'Aéronautique et l'Espace), Toulouse, FRANCE, 2013
 
5 Pierre L., Runtime verification of functional requirements for SoC models: integration of PSL in SystemC TLM, Ecole d'hiver Francophone sur les Technologies de Conception des Systèmes embarqués Hétérogènes, Leysin, SWITZERLAND, 2013
 
remonter

1 Rapports

1 Pierre L., A Model for Assertion-Based Verification of TLM Designs, ISRN: TIMA-RR--07/09-01--FR, 1 janvier 2007
 
remonter

4 Logiciels

1 Pierre L., Mazet K., Zian-Cherif A., OSIRIS version 1, Logiciel, 18 mars 2015
 
2 Ferro L., Pierre L., Chabot., Bel Hadj Amor Z., ISIS version 2.1.1, Logiciel, 1 mars 2015
 
3 Ferro L., Pierre L., Logiciel, Logiciel, 14 décembre 2010
 
4 Borrione D., Ferro L., Fesquet L., Morin-Allory K., Oddos Y., Pierre L., Logiciel, Logiciel, 9 mai 2009
 
remonter