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37 résultats

   2 Revues internationales
   1 Brevets
   4 Conférences invitées
  23 Conférences internationales
   2 Conférences nationales
   2 Autres communications
   2 Logiciels
   1 Thèses

2 Revues internationales

1 Portolan M., Automated Testing Flow: the Present and the Future, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Ed. IEEE, Vol. , DOI: 10.1109/TCAD.2019.2961328, décembre 2019
 
2 Portolan M., Leveugle R., A highly flexible hardened RTL processor core based on LEON2, IEEE Transactions on Nuclear Science, Ed. IEEE, Vol. 53, Part 1, No. 4, pp. 2069 - 2075, DOI: 10.1109/TNS.2006.876508, août 2006
 
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1 Brevets

1 Portolan M., Test apparatus and method for testing an integrated circuit, No. 17/54491, 19 mai 2017
 
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4 Conférences invitées

1 Di Natale G., Kooli M., Bosio A., Portolan M., Leveugle R., Reliability of computing systems: from flip flops to variables, Invited talk (Special Session), 23rd IEEE International Symposium on On-Line Testing and Robust System Design (IOLTS 2017), Thessaloniki, GREECE, DOI: 10.1109/IOLTS.2017.8046242, 3 au 5 juillet 2017
 
2 Anghel L., Portolan M., Managing Wear out and Variability Monitors: IEEE 1687 to the Rescue, Keynote talk, East West Design and test Symposium, Yerevan, ARMENIA, 13 au 16 octobre 2016
 
3 Portolan M., System Level Coordination of Multiple-Standard DfT, Invited Talk, Test Standards Application Workshop (TESTA’16), Amsterdam, NETHERLANDS, 28 mai 2016
 
4 Portolan M., Standards: Can they co-exist for System Level Test?, Invited Talk, VLSI Test Symposium, Las Vegas, NE, UNITED STATES, 25 au 27 avril 2016
 
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23 Conférences internationales

 1 Portolan M., Reynaud V., Maistri P., Leveugle R., Dynamic Authentication-Based Secure Access to Test Infrastructure, European Test Symposium (ETS 2020), Tallin, ESTONIA, 25 mai au 1 juin 2020
 
 2 Portolan M., Rearick J., Keim M., Linking Chip, Board, and System Test via Standards, European Test Symposium (ETS 2020), Tallinn, ESTONIA, 25 mai au 1 juin 2020
 
 3 Damljanovic A., Jutman A., Portolan M., Sanchez E., Squillero G., Tsertov A., Simulation-based Equivalence Checking between IEEE 1687 ICL and RTL, International Test Conference (ITC 2019), Washington DC, UNITED STATES, 11 au 14 novembre 2019
 
 4 Portolan M., Savino A., Leveugle R., Di Carlo S., Bosio A., Di Natale G., Alternatives to fault injections for early safety/security evaluations, 24th IEEE European Test Symposium (ETS 2019), Baden Baden, GERMANY, 27 au 31 mai 2019
 
 5 Savino A., Portolan M., Leveugle R., Di Carlo S., Approximate computing design exploration through data lifetime metrics, 24th IEEE European Test Symposium (ETS 2019), Baden Baden, GERMANY, 27 au 31 mai 2019
 
 6 Savino A., Portolan M., Di Carlo S., Leveugle R., Targeting approximation through data lifetime: a quest for optimization metrics, 4th Approximate Computing Workshop (AxC 2019), Florence, ITALY, 29 mars 2019
 
 7 Portolan M., Barragan M., Alhakim R., Mir S., Mixed-Signal BIST computation offloading using IEEE 1687, European Test Symposium (ETS 2017), Limassol, CYPRUS, 22 au 26 mai 2017
 
 8 Portolan M., Accessing 1687 systems using arbitrary protocols, International Test Conference (ITC'16), Fort Worth, UNITED STATES, DOI: 10.1109/TEST.2016.7805839, 15 au 17 novembre 2016
 
 9 Chibani K., Portolan M., Leveugle R., Application-aware soft error sensitivity evaluation without fault injections - Application to Leon3, European Conference on Radiation and its Effects on Components and Systems (RADECS'16), Bremen, GERMANY, 19 au 23 septembre 2016
 
10 Chibani K., Portolan M., Leveugle R., Evaluating Application-Aware Soft Error Effects in Digital Circuits Without Fault Injections or Probabilistic Computations, 22nd IEEE International Symposium on On-Line Testing and Robust System Design (IOLTS'16), pp. 54-59, St Feliu de Guixols, SPAIN, 4 au 6 juillet 2016
 
11 Portolan M., Barragan M., Malloug H., Mir S., Interactive Mixed-Signal Testing Through 1687, First International Test Standards Application Workshop (TESTA'16), Amsterdam, NETHERLANDS, 26 au 27 mai 2016
 
12 Portolan M., A Novel Test Generation and Application Flow for Functional Access to IEEE 1687 instruments, IEEE European Test Symposium (ETS'2016), Amsterdam, NETHERLANDS, DOI: 10.1109/ETS.2016.7519302, 23 au 27 mai 2016
 
13 Portolan M., Rolland R., Student-driven development of a digital tester, European Workshop on Microelectronics Education (EWME'16), pp. 1-3, Southampton, ENGLAND, DOI: 10.1109/EWME.2016.7496479, 11 mai 2016
 
14 Chibani K., Bergaoui S., Portolan M., Leveugle R., Criticality evaluation of embedded software running on a pipelined microprocessor and impact of compilation options, IEEE International Conference on Electronics, Circuits and Systems (ICECS), pp. 778-781, Marseille, FRANCE, 7 au 10 décembre 2014
 
15 Chibani K., Ben Jrad M., Portolan M., Leveugle R., Fast accurate evaluation of register lifetime and criticality in a pipelined microprocessor, 22nd IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC'14), pp. 260-265, Playa del Carmen, MEXICO, DOI: 10.1109/VLSI-SoC.2014.7004158, 5 au 8 octobre 2014
 
16 Chibani K., Portolan M., Leveugle R., Fast register criticality evaluation in a SPARC microprocessor, 10th Conference on Ph.D Research in Microelectronics and Electronics (PRIME'14), pp. 1-4, Grenoble, FRANCE, DOI: 10.1109/PRIME.2014.6872674, 30 juin au 3 juillet 2014
 
17 Vanhauwaert P., Portolan M., Leveugle R., Roche P., Usefulness and effectiveness of HW and SW protection mechanisms in a processor-based system, IEEE International Conference on Electronics, Circuits and Systems (ICECS'08)), pp. 113-116 , Saint Julians, MALTA, 1 au 3 septembre 2008
 
18 Portolan M., Leveugle R., Effective checkpoint and rollback using hardware/OS collaboration, 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT'07), pp. 370-378, Rome, ITALY, 26 au 28 septembre 2007
 
19 Portolan M., Leveugle R., Towards a secure and reliable system, Embedded and ubiquitous computing (International Conference EUC 2005), pp. 1085-1098, Nagasaki, JAPAN, DOI: 10.1007/11596356_108, 6 au 9 décembre 2005
 
20 Portolan M., Leveugle R., A highly flexible hardened RTL processor core based on LEON, 8th European Conference on Radiation and its Effects on Components and Systems (RADECS'05), Cap d'Agde, FRANCE, 19 au 23 septembre 2005
 
21 Portolan M., Leveugle R., On the Need for Common Evaluation Methods for Fault Tolerance Costs in Microprocessors, IEEE International On-Line Testing Symposium (IOLT'05), pp. 247- 252, St Raphael, FRANCE, DOI: 10.1109/IOLTS.2005.46, 6 au 8 juillet 2005
 
22 Portolan M., Leveugle R., A context-switch based checkpoint and rollback scheme, 19th Conference on Design of Circuits and Integrated Systems (DCIS'04), pp. 423-428, Bordeaux, FRANCE, 24 au 26 novembre 2004
 
23 Portolan M., Leveugle R., Operating system function reuse to achieve low-cost fault tolerance, 10th IEEE International On-Line Testing Symposium (IOLTS'04) , pp. 167- 172, Madeira, PORTUGAL, 12 au 14 juillet 2004
 
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2 Conférences nationales

1 Chibani K., Portolan M., Leveugle R., Analyse de criticité des registres dans un microprocesseur SPARC, 17èmes Journées Nationales du Réseau Doctoral en Microélectronique (JNRDM'14), pp. 4, Lille, FRANCE, 26 au 28 mai 2014
 
2 Portolan M., Leveugle R., Réalisation d'une tolérance aux fautes à bas coût dans les SoCs en utilisant le système d'exploitation, VIIème Journées Nationales du Réseau Doctoral en Microélectronique (JNRDM'04), pp. 454-456, Marseille, FRANCE, 4 au 6 mai 2004
 
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2 Autres communications

1 Portolan M., Cantoro R., Sanchez E., A Functional Approach to Test and Debug of IEEE 1687 Reconfigurable Networks, European Test Symposium (ETS 2019), Baden Baden, GERMANY, 2019
 
2 Portolan M., Cantoro R., Sanchez E., Sonza Reorda M., A Functional Approach to Test and Debug of IEEE 1687 Reconfigurable Networks, International Test Conference (ITC 2018), Phoenix, UNITED STATES, 2018
 
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2 Logiciels

1 Portolan M., "Manager for Soc Test" (MAST), Logiciel, 2 mai 2018
 
2 Leveugle R., Chibani K., Portolan M., EARS (Evaluation Avancée de Robustesse de Systèmes intégrés / Early Analysis of Robustness for integrated Systems), Logiciel, 30 décembre 2016
 
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1 Thèses

1 Portolan M., Dependable and secure design of an embedded system, These de Doctorat, 6 décembre 2006
 
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