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15 résultats

   4 Revues internationales
   1 Conférences invitées
  10 Conférences internationales

4 Revues internationales

1 Vatajelu I., Di Natale G., High-Entropy STT-MTJ-based TRNG, IEEE Transactions on Very Large Scale Integration (VLSI) Systems , Ed. IEEE, Vol. , DOI: 10.1109/TVLSI.2018.2879439, 2019
 
2 Anghel L., Benabdenbi M., Bosio A., Traiola M., Vatajelu I., Test and Reliability in Approximate Computing, Journal of Electronic Testing: Theory and Applications, Ed. Springer , Vol. 34, No. 4, pp. 375-387, DOI: 10.1007/s10836-018-5734-9, août 2018
 
3 Vatajelu I., Prinetto P., Taouil M., Hamdioui S., Challenges and Solutions in Emerging Memory Testing, IEEE Transactions on Emerging Topics in Computing, Ed. IEEE, Vol. PP, No. 99, DOI: 10.1109/TETC.2017.2691263, 2017
 
4 Vatajelu I., Pouyan P., Hamdioui S., State of the art and challenges for test and reliability of emerging nonvolatile resistive memories, International Journal of Circuit Theory and Applications, Ed. Wiley, Chichester, UK, Vol. 46, No. 1, pp. 4-28, DOI: 10.1002/cta.2418, octobre 2017
 
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1 Conférences invitées

1 Anghel L., Benabdenbi M., Bosio A., Vatajelu I., Test and reliability in approximate computing, Invited paper, Mixed Signals Testing Workshop (IMSTW 2017), Thessaloniki, GREECE, DOI: 10.1109/IMS3TW.2017.7995210, 3 au 5 juillet 2017
 
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10 Conférences internationales

 1 Vatajelu I., Di Natale G., Anghel L., Special Session: Reliability of Hardware-Implemented Spiking Neural Networks (SNN), IEEE VLSI Test Symposium (VTS 2019), Monterey, UNITED STATES, 23 au 25 avril 2019
 
 2 Di Natale G., Vatajelu I., Senthamarai Kannan K., Anghel L., Hidden-Delay-Fault Sensor for Test, Reliability and Security, IEEE Design Automation and Test Conference in Europe (DATE 2019), Florence, ITALY, 25 au 29 mars 2019
 
 3 Anghel L., Di Natale G., Miramond B., Vatajelu I., Vianello E., Neuromorphic Computing - From Robust Hardware Architectures to Testing Strategies, 26th IFIP IEEE International Conference on Very Large Scale Integration (VLSI SOC 2018), Verona, ITALY, 8 au 10 octobre 2018
 
 4 Morgül Muhammed Ceylan, Frontini L., Vatajelu I., Anghel L., Integrated Synthesis Methodology for Crossbar Arrays, IEEE NANOARCH'2018, Athens, GREECE, 18 au 19 juillet 2018
 
 5 Vatajelu I., Anghel L., Portal J.-M., Bocquet M., Prenat G., Resistive and Spintronic RAMs: Device, Simulation, and Applications, IEEE International On Line Testing (IOLTS'2018), Platja d'Aro, SPAIN, 2 au 4 juillet 2018
 
 6 Vatajelu I., Anghel L., Fully-Connected Single-Layer STT-MTJ-based Spiking Neural Network under Process Variability, ACM/IEEE International Symposium on Nanoscale Architectures (NANOARCH 2017), Newport, RI, UNITED STATES, 25 au 29 juillet 2017
 
 7 Vatajelu I., Di Natale G., Prinetto P., Zero bit-error-rate weak PUF based on Spin-Transfer-Torque MRAM memories, 2017 IEEE 2nd International Verification and Security Workshop (IVSW 2017), pp. 128-133, Thessaloniki, GREECE, DOI: 10.1109/IVSW.2017.8031552, 3 au 7 juillet 2017
 
 8 Vatajelu I., Anghel L., Reliability Analysis of MTJ-based Functional Module for Neuromorphic Computing, International Symposium on On-Line Testing and Robust System Design (IOLTS 2017), Thessaloniki, GREECE, 3 au 5 juin 2017
 
 9 Vatajelu I., Rodriguez-Montanes R., Renovell M., Figueras J., Mitigating Read & Write Errors in STT-MRAM Memories under DVS, European Test Symposium (ETS 2017), Limassol, CYPRUS, 22 au 26 mai 2017
 
10 Barbareschi M., Bosio A., Hamdioui S., Nguyen Hoang Anh Du, Traiola M., Vatajelu I., Memristive devices: Technology, Design Automation and Computing Frontiers, International Conference on Design &Technology of Integrated Systems in Nanoscale Era (DTIS 2017), Palma de Mallorca, SPAIN, 4 au 6 avril 2017
 
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