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51 résultats

   9 Revues internationales
   7 Conférences invitées
  24 Conférences internationales
   2 Chapitres de livre
   2 Livres & Éditions Ouvrages
   4 Conférences nationales
   2 Autres communications
   1 Thèses

9 Revues internationales

1 Silveira Feitoza R., Barragan M., Dzahini D., Mir S., Reduced-code static linearity test of split-capacitor SAR ADCs using an embedded incremental Sigma-Delta converter, IEEE Transactions on Device and Materials Reliability, Vol. 19, No. 1, pp. 37-45, DOI: 10.1109/TDMR.2019.2891298, mars 2019
 
2 Renaud G., Diallo M., Barragan M., Mir S., Fully-differential 4 V-output range 14.5-ENOB step-wise ramp stimulus generator for on-chip static linearity test of ADCs, IEEE Transactions on Very Large Scale Integration (VLSI) Systems , Ed. IEEE, Vol. 27, No. 2, pp. 281-293, DOI: 10.1109/TVLSI.2018.2876976, février 2019
 
3 Malloug H., Barragan M., Mir S., Practical Harmonic Cancellation Techniques for the On-Chip Implementation of Sinusoidal Signal Generators for Mixed-Signal BIST Applications, Journal of Electronic Testing: Theory and Applications, Ed. Springer , Vol. 34, No. 3, pp. 263-279, DOI: 10.1007/s10836-018-5720-2, juin 2018
 
4 Leger G., Barragan M., Brownian distance correlation-directed search: A fast feature selection technique for alternate test, Integration, the VLSI Journal, Ed. Elsevier, Vol. , 2016
 
5 Barragan M., Stratigopoulos H., Mir S., Le Gall H., Bhargava N., Bal A., Practical Simulation Flow for Evaluating Analog and Mixed-Signal Test Techniques, IEEE Design & Test, Ed. IEEE, Vol. 33, No. 6, pp. 46-54, DOI: 10.1109/MDAT.2016.2590985, décembre 2016
 
6 Barragan M., Alhakim R., Stratigopoulos H., Dubois M., Mir S., Le Gall H., Bhargava N., Bal A., A Fully-Digital BIST Wrapper Based on Ternary Test Stimuli for the Dynamic Test of a 40 nm CMOS 18-bit Stereo Audio Sigma-Delta ADC, IEEE Transactions on Circuits and Systems, Ed. IEEE, Vol. 63, No. 11, pp. 1876-1888, DOI: 10.1109/TCSI.2016.2602387, novembre 2016
 
7 Renaud G., Barragan M., Laraba A., Stratigopoulos H., Mir S., Le Gall H., Naudet H., A 65nm CMOS Ramp Generator Design and its Application Towards a BIST Implementation of the Reduced-Code Static Linearity Test Technique for Pipeline ADCs, Journal of Electronic Testing: Theory and Applications, Ed. Springer , Vol. 32, No. 4, pp. 407-421, DOI: 10.1007/s10836-016-5599-8, avril 2016
 
8 Barragan M., Leger G., A Procedure for Alternate Test Feature Design and Selection , IEEE Design and Test of Computers, Ed. IEEE, Vol. 32, No. 1, pp. 18-25, DOI: 10.1109/MDAT.2014.2361722, février 2015
 
9 Barragan M., Leger G., Vazquez D., Rueda A., On-chip sinusoidal signal generation with harmonic cancelation for analog and mixed-signal BIST applications, Analog Integrated Circuits and Signal Processing, Ed. Kluwer Academic Publishers, Vol. 82, No. 1, pp. 67-79, DOI: 10.1007/s10470-014-0456-0, janvier 2015
 
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7 Conférences invitées

1 Cilici F., Leger G., Barragan M., Mir S., Lauga-Larroze E., Bourdel S., Efficient generation of data sets for one-shot statistical calibration of RF/mm-wave circuits, Hot topic session, International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD 2019), Lausanne, SWITZERLAND, 15 au 18 juillet 2019
 
2 Barragan M., Leger G., Feature selection and feature design for machine learning indirect test: a tutorial review, Hot topic session, International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD 2019), Lausanne, SWITZERLAND, 15 au 18 juillet 2019
 
3 Mir S., Barragan M., Mammasse M., BIST Solutions for Industrial Mixed-signal Circuits, Invited talk (Special Session), 25th International On-Line Testing Symposium (IOLTS 2019), Rhodes, GREECE, 1 au 3 juillet 2019
 
4 Leger G., Barragan M., Mixed-signal test automation: are we there yet?, Invited talk (Special Session), IEEE International Symposium on Circuits & Systems (ISCAS'2018), Florence, ITALY, DOI: 10.1109/ISCAS.2018.8351734, 27 au 30 mai 2018
 
5 Leger G., Barragan M., Why is systematic AMS-RF test not there yet ?, Invited Tutorial, CEDA 2017, Barcelona, SPAIN, 21 novembre 2017
 
6 Barragan M., Leger G., Efficient strategies for feature selection and discovery in machine-learning test applications, Invited talk (Special Session), Conference on Design of Circuits and Integrated Systems (DCIS'15), Estoril, PORTUGAL, 25 au 27 novembre 2015
 
7 Dubois M., Stratigopoulos H., Barragan M., Alhakim R., Mir S., Analog/RF test problem solving with statistically sampled data, Invited talk (Elevator talk), IEEE VLSI Test Symposium (VTS'14), Napa, California, UNITED STATES, 14 au 16 mai 2014
 
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24 Conférences internationales

 1 Silveira Feitoza R., Barragan M., Mir S., Reduced-Code Techniques for On-Chip Static Linearity Test of SAR ADCs, 27th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), Cuzco, PERU, 6 au 9 octobre 2019
 
 2 Malloug H., Barragan M., Mir S., A 52 dB-SFDR 166 MHz sinusoidal signal generator for mixed-signal BIST applications in 28 nm FDSOI technology, European Test Symposium (ETS 2019), Baden Baden, GERMANY, 27 au 31 mai 2019
 
 3 Cilici F., Barragan M., Mir S., Lauga-Larroze E., Bourdel S., Leger G., Yield Recovery of mm-Wave Power Amplifiers using Variable Decoupling Cells and One-Shot Statistical Calibration, IEEE International Symposium on Circuits and Systems (ISCAS 2019), pp. 1-5, Sapporo, JAPAN, 26 au 29 mai 2019
 
 4 Barragan M., Leger G., Cilici F., Lauga-Larroze E., Bourdel S., Mir S., On the use of causal feature selection in the context of machine-learning indirect test, Design, Automation & Test in Europe Conference & Exhibition (DATE 2019), pp. 276-279, Florence, ITALY, 25 au 29 mars 2019
 
 5 Silveira Feitoza R., Barragan M., Mir S., Dzahini D., Reduced-code static linearity test of SAR ADCs using a built-in incremental Sigma-Delta converter, 24th IEEE International Symposium on On-Line Testing and Robust System Design (IOLTS'2018), pp. 29-34, Platja d'Aro, SPAIN, DOI: 978-1-5386-5992-2/18, 2 au 4 juillet 2018
 
 6 Cilici F., Barragan M., Mir S., Lauga-Larroze E., Bourdel S., Assisted test generation strategy for non-intrusive machine learning indirect test of millimeter-wave circuits, 23rd IEEE European Test Symposium (ETS'2018), pp. 1-6, Bremen, GERMANY, DOI: 978-1-5386-3728-9/18, 28 mai au 1 juin 2018
 
 7 Margalef-Rovira M., Barragan M., Sharma E., Ferrari P., Pistono E., Bourdel S., An Oscillation-Based Test technique for on-chip testing of mm-wave phase shifters, IEEE 36th VLSI Test Symposium (VTS'2018), pp. 1-6, San Francisco, UNITED STATES, DOI: 10.1109/VTS.2018.8368622, 22 au 25 avril 2018
 
 8 Malloug H., Barragan M., Mir S., Le Gall H., Harmonic cancellation strategies for on-chip sinusoidal signal generation using digital resources, International Mixed-Signal Testing Workshop (IMSTW 2017), Thessaloniki, GREECE, DOI: 10.1109/IMS3TW.2017.7995201, 3 au 5 juillet 2017
 
 9 Malloug H., Barragan M., Mir S., Basteres L., Le Gall H., Design of a sinusoidal signal generator with calibrated harmonic cancellation for mixed-signal BIST in a 28 nm FDSOI technology, European Test Symposium (ETS 2017), Limassol, CYPRUS, DOI: 10.1109/ETS.2017.7968214, 22 au 26 mai 2017
 
10 Renaud G., Margalef-Rovira M., Barragan M., Mir S., Analysis of an efficient on-chip servo-loop technique for reduced-code static linearity test of pipeline ADCs, VLSI Test Symposium (VTS 2017), Las Vegas, UNITED STATES, DOI: 10.1109/VTS.2017.7928951, 9 au 12 avril 2017
 
11 Barragan M., Leger G., Gines A., Peralias E., Rueda A., On the limits of machine learning-based test: a calibrated mixed-signal system case study, Design Automation and Test in Europe (DATE 2017), Lausanne, SWITZERLAND, DOI: 10.23919/DATE.2017.7926962, 27 au 31 mars 2017
 
12 Gines A., Peralias E., Leger G., Rueda A., Renaud G., Barragan M., Mir S., Design Trade-offs for On-chip Driving of High-speed High-performance ADCs in Static BIST Applications, IEEE 21st International Mixed-Signal Testing Workshop (IMSTW'16), Sant Feliu de Guixols, SPAIN, 4 au 7 juillet 2016
 
13 Malloug H., Barragan M., Mir S., Le Gall H., Mostly-digital design of sinusoidal signal generators for mixed-signal BIST applications using harmonic cancellation, IEEE 21st International Mixed-Signal Testing Workshop (IMSTW'16), Sant Feliu de Guixols, SPAIN, 4 au 7 juillet 2016
 
14 Portolan M., Barragan M., Malloug H., Mir S., Interactive Mixed-Signal Testing Through 1687, First International Test Standards Application Workshop (TESTA'16), Amsterdam, NETHERLANDS, 26 au 27 mai 2016
 
15 Gines A., Peralias E., Leger G., Rueda A., Renaud G., Barragan M., Mir S., Linearity Test of High-speed High-performance ADCs using a Self-Testable On-chip Generator, 21st IEEE European Test Symposium (ETS'16), Amsterdam, NETHERLANDS, 23 au 27 mai 2016
 
16 Leger G., Barragan M., Questioning the reliability of Monte Carlo simulation for machine learning test validation, 21st IEEE European Test Symposium (ETS'16), Amsterdam, NETHERLANDS, 23 au 27 mai 2016
 
17 Stratigopoulos H., Barragan M., Mir S., Le Gall H., Bhargava N., Bal A., Evaluation of low-cost mixed-signal test techniques for circuits with long simulation times, IEEE International Test Conference (ITC'15), Anaheim, CA, UNITED STATES, 6 au 8 octobre 2015
 
18 Leger G., Barragan M., A hybrid method for feature selection in the context of Alternate Test, International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD'15), pp. 1-4, Istanbul, TURKEY, 7 au 9 septembre 2015
 
19 Renaud G., Barragan M., Mir S., Design of an on-chip stepwise ramp generator for ADC static BIST applications, IEEE International Mixed-Signal Testing Workshop (IMS3TW'15), pp. 1-6, Paris, FRANCE, DOI: 10.1109/IMS3TW.2015.7177876, 24 au 26 juin 2015
 
20 Malloug H., Barragan M., Mir S., Evaluation of harmonic cancellation techniques for sinusoidal signal generation in mixed-signal BIST, IEEE International Mixed-Signal Testing Workshop (IMS3TW'15), Paris, FRANCE, DOI: 10.1109/IMS3TW.2015.7177877, 24 au 26 juin 2015
 
21 Barragan M., Leger G., Azais F., Blanton R.D., Singh Adit D., Sunter S., Special session: Hot topics: Statistical test methods, VLSI Test Symposium (VTS), 2015 IEEE 33rd, pp. 1-2, Napa, CA, UNITED STATES, DOI: 10.1109/VTS.2015.7116265, 27 au 29 avril 2015
 
22 Barragan M., Leger G., Feature selection for alternate test using wrappers: application to a LNA case study, Design Automation and Test in Europe Conference (DATE'15), Grenoble, FRANCE, DOI: doi: 10.7873/DATE.2015.0179, 9 au 13 mars 2015
 
23 Renaud G., Barragan M., Mir S., On-Chip Implementation of an Integrator-Based Servo-Loop for ADC Static Linearity Test , 23rd IEEE Asian Test Symposium (ATS'14), pp. 212-217, Hangzhou, CHINA, DOI: 10.1109/ATS.2014.47, 16 au 19 novembre 2014
 
24 Dubois M., Stratigopoulos H., Mir S., Barragan M., Evaluation of digital ternary stimuli for dynamic test of ΣΔ ADCs , IFIP/IEEE 22nd International Conference on Very Large Scale Integration (VLSI-SoC'14), pp. 1-6, Playa del Carmen, Mexico, MEXICO, DOI: 10.1109/VLSI-SoC.2014.7004153, 6 au 8 octobre 2014
 
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2 Chapitres de livre

1 Gines A., Fiorelli R., Villegas A., Doldan R., Barragan M., Vazquez D., Rueda A., Peralias E., Design of an energy efficient ZigBee transceiver, Mixed-Signal Circuits, M. Soma, T. Noulis (Eds.) , Ed. CRC Press, pp. , 2015
 
2 Dubois M., Stratigopoulos H., Mir S., Barragan M., Statistical evaluation of digital techniques for Sigma-Delta ADC BIST, VLSI-SoC: Internet of Things Foundations, Luc Claesen, Maria-Teresa Sanz-Pascual, Ricardo Reis, Arturo Sarmiento-Reyes (Eds.) , Ed. Springer , pp. 129-148, DOI: 10.1007/978-3-319-25279-7 8, 2015
 
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2 Livres & Éditions Ouvrages

1 Huang K., Barragan M. (Eds.) Journal of Electronic Testing: Special Issue on Analog, Mixed-Signal, and RF Testing, Vol. 34, pp. 213-370, Ed. Springer , 2018
 
2 Barragan M., Eisenstadt W. (Eds.) Guest Editorial: Analog, Mixed-Signal and RF Testing, Special issue of Journal of Electronic Testing, Vol. 33, pp. 281-282, Ed. Springer , 2017
 
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4 Conférences nationales

1 Silveira Feitoza R., Barragan M., Dzahini D., Mir S., Static linearity test of SAR ADCs using an embedded incremental Σ∆ converter, Journées Nationales du Réseau Doctoral en Micro-nanoélectronique (JNRDM 2019), Montpellier, FRANCE, 3 au 5 juin 2019
 
2 Margalef-Rovira M., Barragan M., Pistono E., Bourdel S., Ferrari P., Conception de déphaseurs RTPS faible consommation en bande millimétrique, 21èmes Journées Nationales Micro-ondes (JNM 2019), Caen, FRANCE, 14 au 17 mai 2019
 
3 Malloug H., Barragan M., Mir S., Conception d’un générateur de signal sinusoïdal basé sur les techniques d’annulation d’harmonique en 28nm FDSOI, Journées GDR SoC-SiP, Paris, FRANCE, 13 au 15 juin 2018
 
4 Cilici F., Barragan M., Lauga-Larroze E., Bourdel S., Mir S., Conception en vue du test d’un amplificateur de puissance à 60 GHz, Journées Nationales du Réseau Doctoral en Micro-nanoélectronique (JNRDM 2017), Strasbourg, FRANCE, 6 au 8 novembre 2017
 
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2 Autres communications

1 Portolan M., Barragan M., Alhakim R., Mir S., Mixed-Signal BIST computation offloading using IEEE 1687, European Test Symposium (ETS 2017), Limassol, CYPRUS, 2017
 
2 Barragan M., Leger G., Feature selection for Alternate Test using wrappers: application to an RF LNA case study, 1st Workshop on Statistical Test Methods (STEM'14), pp. 6, Paderborn, GERMANY, 2014
 
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1 Thèses

1 Barragan M., Built-In Self-Test solutions for high-performance and reliable analog, mixed-signal, and RF integrated circuits, HDR, 9 juillet 2019
 
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