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271 résultats

   62 Revues internationales
    3 Brevets
   12 Conférences invitées
  161 Conférences internationales
    6 Chapitres de livre
    3 Livres & Éditions Ouvrages
    3 Revues nationales
   10 Autres communications
   11 Rapports

62 Revues internationales

 1 Garay Trindade M., Coelho A., Valadares C., Andreoni Camponogara Viera R., Rey S., Cheymol B., Baylac M., Velazco R., Possamai Bastos R., Assessment of a Hardware-Implemented Machine Learning Technique under Neutron Irradiation, IEEE Transactions on Nuclear Science, Ed. IEEE, Vol. , juin 2019
 
 2 Franco F., Clemente J.A., Mecha H., Velazco R., Influence of Randomness during the Interpretation of Results from Single-Event Experiments on SRAMs (Early Access), IEEE Transactions on Device and Materials Reliability, Vol. , DOI: 10.1109/TDMR.2018.2886358, 2018
 
 3 Kchaou A., El Hadj Youssef W., Velazco R., Tourki R., An exhaustive analysis of SEU effects in the SRAM memory of soft processor, International Journal of Engineering Science and Technology, Vol. 13, No. 1, 2018
 
 4 Vargas V., Ramos P., Velazco R., Evaluation by Neutron Radiation of the NMR-MPar Fault-Tolerance Approach Applied to Applications Running on a 28-nm Many-Core Processor, Electronics Letters, Ed. IEEE, Vol. 7, No. 11, DOI: 10.3390/electronics7110312, novembre 2018
 
 5 Vargas V., Ramos P., Méhaut J-F., Velazco R., NMR-Mpar: A Fault-Tolerance Approach for Multi-Core and Many-Core Processors, Applied Sciences, Ed. MDPI, Vol. , DOI: 10.3990/app8030465, août 2018
 
 6 Ramos P., Vargas V., Baylac M., Zergainoh N.-E., Velazco R., SEE error-rate evaluation of an application implemented in COTS Multi/Many-core processors, IEEE Transactions on Nuclear Science, Ed. IEEE, Vol. 65, No. 8, pp. 1879-1886, DOI: 10.1109/TNS.2018.2838526, août 2018
 
 7 Ramos P., Vargas V., Zergainoh N.-E., Velazco R., Assessing the Static and Dynamic Sensitivity of a Commercial Off-the-Shelf Multicore Processor for Noncritical Avionic Applications, Journal of Nanotechnology, Ed. Hindawi Publishing Corporation, Vol. 2018, No. ID 2926392, pp. 1-8, DOI: 10.1155/2018/2926392, juillet 2018
 
 8 Franco F., Clemente J.A., Baylac M., Rey S., Villa F., Mecha H., Agapito J.-A., Puchner H., Hubert G., Velazco R., Statistical Deviations from the Theoretical only-SBU Model to Estimate MCU rates in SRAMs, IEEE Transactions on Nuclear Science, Ed. IEEE, Vol. 64, pp. 2152–2160, 2017
 
 9 Clemente J.A., Franco F., Villa F., Baylac M., Rey S., Mecha H., Puchner H., Agapito J.-A., Hubert G., Velazco R., SEU Characterization of Three Successive Generations of COTS SRAMs at Ultralow Bias Voltage to 14.2 MeV Neutrons, IEEE Transactions on Nuclear Science, Ed. IEEE, Vol. 64, No. 8, pp. 2152-2160, DOI: 10.1109/TNS.2017.2726938, août 2017
 
10 Fraire J., Madoery P., Burleigh S., Charif A., Zergainoh N.-E., Velazco R., Assessing Contact Graph Routing Performance and Reliability in Distributed Satellite Constellations, Journal of Computer Networks and Communications, Ed. Hindawi Publishing Corporation, Vol. 2017, pp. 1-18, DOI: 10.1155/2017/2830542, juillet 2017
 
11 Clemente J.A., Hubert G., Franco F., Villa F., Baylac M., Mecha H., Puchner H., Velazco R., Sensitivity Characterization of a COTS 90-nm SRAM at Ultra Low Bias Voltage, IEEE Transactions on Nuclear Science, Ed. IEEE, Vol. PP, No. 99, DOI: 10.1109/TNS.2017.2682984, mars 2017
 
12 Coelho A., Laurent R., Solinas M., Fraire J., Mazer E., Zergainoh N.-E., Velazco R., On the Robustness of Stochastic Bayesian Machines, IEEE Transactions on Nuclear Science, Ed. IEEE, Vol. PP, No. 99, DOI: 10.1109/TNS.2017.2678204, mars 2017
 
13 Vargas V., Ramos P., Ray V., Jalier C., Stevens R., Dupont De Dinechin B., Baylac M., Villa F., Rey S., Zergainoh N.-E., Méhaut J-F., Velazco R., Radiation Experiments on a 28nm Single-Chip Many-core Processor and SEU error-rate prediction, IEEE Transactions on Nuclear Science, Ed. IEEE, Vol. 64, No. 1, pp. 483-490, DOI: 10.1109/TNS.2016.2638081, janvier 2017
 
14 Souari A., Thibeault Cl., Blaquière Y., Velazco R., Towards an efficient SEU effects emulation on SRAM-based FPGAs, Microelectronics Reliability, Ed. Elsevier, Vol. 66, pp. 173-182, novembre 2016
 
15 Clemente J.A., Franco F., Villa F., Baylac M., Ramos P., Vargas V., Mecha H., Agapito J.-A., Velazco R., Neutron-Induced Single Events in a COTS Soft-Error Free SRAM at Low Bias Voltage Neutrons, IEEE Transactions on Nuclear Science, Ed. IEEE, Vol. 63, No. 4, pp. 2072-2079, août 2016
 
16 Ramos P., Vargas V., Clemente J.A., Zergainoh N.-E., Méhaut J-F., Velazco R., Evaluating the SEE Sensitivity of a 45 nm SOI Multi-Core Processor Due to 14 MeV Neutrons, IEEE Transactions on Nuclear Science, Ed. IEEE, Vol. 63, No. 4, pp. 2193 - 2200, DOI: 10.1109/TNS.2016.2537643, juillet 2016
 
17 Clemente J.A., Franco F., Villa F., Baylac M., Rey S., Mecha H., Agapito J.-A., Puchner H., Hubert G., Velazco R., Statistical Anomalies of Bitflips in SRAMs to Discriminate SBUs from MCUs, IEEE Transactions on Nuclear Science, Ed. IEEE, Vol. 63, No. 4, pp. 2087–2094, DOI: 10.1109/TNS.2016.2551263, avril 2016
 
18 Clemente J.A., Franco F., Villa F., Baylac M., Ramos P., Vargas V., Mecha H., Agapito J.-A., Velazco R., Single Events in a COTS Soft-Error Free SRAM at Low Bias Voltage Induced by 15-MeV Neutrons, IEEE Transactions on Nuclear Science, Ed. IEEE, Vol. 63, No. 4, pp. 2072 - 2079, DOI: 10.1109/TNS.2016.2522819, avril 2016
 
19 Clemente J.A., Mansour W., Ayoubi R., Serrano F., Mecha H., Ziade H., El Falou W., Velazco R., Hardware implementation of a fault-tolerant Hopfield Neural Network on FPGAs, Neurocomputing Journal, Ed. Elsevier, Vol. 171, No. 1, pp. 1606-1609, DOI: 10.1016/j.neucom.2015.06.038, janvier 2016
 
20 Velazco R., Clemente J.A., Hubert G., Mansour W., Palomar C., Franco F., Baylac M., Rey S., Rosetto O., Villa F., Evidence of the Robustness of a COTS Soft-Error Free SRAM to Neutron Radiation, IEEE Transactions on Nuclear Science, Ed. IEEE, Vol. 61, No. 6, pp. 3103-3108, DOI: 10.1109/TNS.2014.2363899, décembre 2014
 
21 Mansour W., Velazco R., Hubert G., Error-Rate Estimation Combining SEE Static Cross-Section Predictions and Fault-Injections Performed on HDL-Based Designs, IEEE Transactions on Nuclear Science, Ed. IEEE, Vol. 60, No. 6, pp. 4238-4242, décembre 2013
 
22 Hubert G., Velazco R., Federico C.A., Cheminet A., Silva Cardenas C., Caldas L.V., Pancher F., Lacoste V., Palumbo F., Mansour W., Artola L., Pineda F., Duzellier S., Continuous High-Altitude Measurements of Cosmic Ray Neutrons and SEU/MCU at Various Locations: Correlation and Analyses Based-On MUSCA SEP, IEEE Transactions on Nuclear Science, Ed. IEEE, Vol. 60, No. 4, pp. 2418-2426, DOI: 10.1109/TNS.2013.2240697, août 2013
 
23 Cheminet A., Hubert G., Lacoste V., Velazco R., Boscher D., Characterization of the Neutron Environment and SEE Investigations at the CERN-EU High Energy Reference Field and at the Pic du Midi , IEEE Transactions on Nuclear Science, Ed. IEEE, Vol. 60, August, No. 4, pp. 2411-2417, DOI: 10.1109/TNS.2012.2231699, août 2013
 
24 Mansour W., Velazco R., An Automated SEU Fault-Injection Method and Tool for HDL-Based Designs , IEEE Transactions on Nuclear Science, Ed. IEEE, Vol. 60, No. 4, pp. 2728 - 2733 , DOI: 10.1109/TNS.2013.2267097, janvier 2013
 
25 Azambuja J.R., Pagliarini S., Altieri M., Lima F., Hübner M., Becker J., Foucard G., Velazco R., A Fault Tolerant Approach to Detect Transient Faults in Microprocessors Based on a Non-Intrusive Reconfigurable Hardware , IEEE Transactions on Nuclear Science, Ed. IEEE, Vol. 59, No. 4, pp. 1117 - 1124 , DOI: 10.1109/TNS.2012.2201750, janvier 2012
 
26 Velazco R., Mansour W., Pancher F., Costa-Marques G., Sohier D., Bui A., Improving SEU Fault Tolerance Capabilities of a Self-Converging Algorithm , IEEE Transactions on Nuclear Science, Ed. IEEE, Vol. 59, No. 4, pp. 818 - 823, DOI: 10.1109/TNS.2012.2188303, janvier 2012
 
27 Mansour W., Ayoubi R., Ziade H., Velazco R., El Falou W., An Optimal Implementation on FPGA of a Hopfield Neural Network, Advances in Artificial Neural Systems, Ed. Hindawi Publishing Corporation, Vol. Article ID 189368, pp. 9 pages, DOI: 10.1155/2011/189368, 2011
 
28 Foucard G., Peronnard P., Velazco R., Reliability Limits of TMR Implemented in a SRAM-based FPGA: Heavy Ion Measures vs. Fault Injection Predictions, Journal of Electronic Testing: Theory and Applications, Ed. Springer , Vol. 27, No. 5, DOI: 10.1007/s10836-011-5245-4, octobre 2011
 
29 Ziade H., Ayoubi R., Velazco R., Idriss T., A new fault injection approach to study the impact of bitflips in the configuration of SRAM-based FPGAs, International Arab Journal of Information Technology (IAJIT), Vol. 8, No. 2, pp. 155-162, janvier 2011
 
30 Artola L., Velazco R., Hubert G., Duzellier S., Nuns T., Guerard B., Peronnard P., Mansour W., Pancher F., Bezerra F., In Flight SEU/MCU Sensitivity of Commercial Nanometric SRAMs: Operational Estimations , IEEE Transactions on Nuclear Science, Ed. IEEE, Vol. 58, No. 6, pp. 2644 - 2651 , DOI: 10.1109/TNS.2011.2172220 , janvier 2011
 
31 Peronnard P., Velazco R., Hubert G., Real-Life SEU Experiments on 90 nm SRAMs in Atmospheric Environment: Measures Versus Predictions Done by Means of MUSCA SEP3 Platform, IEEE Transactions on Nuclear Science, Ed. IEEE, Vol. 56, No. 6, pp. 3450 - 3455 , DOI: 10.1109/TNS.2009.2033362 , janvier 2009
 
32 Ferreyra P., Viganotti G., Marques C.A., Velazco R., Ferreyra R., Failure and coverage factors based Markoff models: a new approach for improving the dependability estimation in complex fault tolerant systems exposed to SEUs, IEEE Transactions on Nuclear Science, Ed. IEEE, Vol. Vol. 54, No. 4, Part 2, pp. 912-91, DOI: 10.1109/TNS.2007.895548, janvier 2007
 
33 Garcia-Valderas M., Faure F., Peronnard P., Ecoffet R., Bezerra F., Velazco R., Two complementary approaches for studying the effects of SEUs on digital processors, IEEE Transactions on Nuclear Science, Ed. IEEE, Vol. Vol. 54, No. 4, pp. 924-928, DOI: 10.1109/TNS.2007.893871, janvier 2007
 
34 Faure F., Velazco R., Peronnard P., Single-event-upset-like fault injection: a comprehensive framework, IEEE Transactions on Nuclear Science, Ed. IEEE, Vol. 52, No. 6, pp. 2205-2209, DOI: 10.1109/TNS.2005.860689, décembre 2005
 
35 Nicolescu B., Gorse N., Savaria B.Y., Aboulhamid E.M., Velazco R., On the Use of Model Checking for the Verification of a Dynamic Signature Monitoring Approach, IEEE Transactions on Nuclear Science, Ed. IEEE, Vol. 52, No. 5, pp. 1555-1561, DOI: 10.1109/TNS.2005.855819, janvier 2005
 
36 Nicolescu B., Savaria B.Y., Velazco R., Software detection mechanisms providing full coverage against single bit-flip faults, IEEE Transactions on Nuclear Science, Ed. IEEE, Vol. 51, No. 6, pp. 3510- 3518, DOI: 10.1109/TNS.2004.839110, janvier 2004
 
37 Velazco R., Rezgui S., Ziade H., Assessing the soft error rate of digital architectures devoted to operate in radiation environment: a case studied, Journal of Electronic Testing: Theory and Applications, Ed. Springer , Vol. 19, No. 1, pp. 83-90, DOI: 10.1023/A:1021900130241, janvier 2003
 
38 Faure F., Velazco R., Violante M., Rebaudengo M., Sonza Reorda M., Impact of data cache memory on the single event upset-induced error rate of microprocessors, IEEE Transactions on Nuclear Science, Ed. IEEE, Vol. 50, Part 1, No. 6, pp. 2101 - 2106, DOI: 10.1109/TNS.2003.821824, janvier 2003
 
39 Rebaudengo M., Sonza Reorda M., Violante M., Nicolescu B., Velazco R., Coping with SEUs/SETs in microprocessors by means of low-cost solutions: a comparison study, IEEE Transactions on Nuclear Science, Ed. IEEE, Vol. 49, Part 3, No. 3, pp. 1491 - 1495, DOI: 10.1109/TNS.2002.1039689, juin 2002
 
40 Rezgui S., Swift G., Velazco R., Farmanesh F.F., Validation of an SEU simulation technique for a complex processor: PowerPC7400, IEEE Transactions on Nuclear Science, Ed. IEEE, Vol. 49, Part 1, No. 6, pp. 3156 - 3162, DOI: 10.1109/TNS.2002.805982, janvier 2002
 
41 Rezgui S., Velazco R., Ecoffet R., Rodriguez S., Mingo J.R., Estimating error rates in processor-based architectures, IEEE Transactions on Nuclear Science, Ed. IEEE, Vol. 48, No. 5, pp. 1680 - 1687, DOI: 10.1109/23.960357, octobre 2001
 
42 Cota E.F., Lima F., Rezgui S., Carro L., Velazco R., Lubaszewski M., Reis R., Synthesis of an 8051-like microcontroller tolerant to transient faults, Journal of Electronic Testing: Theory and Applications, Ed. Springer , Vol. 17, No. 2, pp. 149 - 161, DOI: 10.1023/A:1011125927317, avril 2001
 
43 Cheynet P., Nicolescu B., Velazco R., Rebaudengo M., Sonza Reorda M., Violante M., Experimentally evaluating an automatic approach for generating safety-critical software with respect to transient errors, IEEE Transactions on Nuclear Science, Ed. IEEE, Vol. 47, Part 3, No. 6, pp. 2231-2236, DOI: 10.1109/23.903758, décembre 2000
 
44 Velazco R., Rezgui S., Ecoffet R., Predicting error rate for microprocessor-based digital architectures through C.E.U. (Code Emulating Upsets) injection, IEEE Transactions on Nuclear Science, Ed. IEEE, Vol. 47, Part 3, No. 6, pp. 2405-2411, DOI: 10.1109/23.903784, décembre 2000
 
45 Monnier T., Roche F.M., Cosculluela J., Velazco R., SEU testing of a novel hardened register implemented using standard CMOS technology, IEEE Transactions on Nuclear Science, Ed. IEEE, Vol. 46, No. 6, pp. 1440 - 1444, DOI: 10.1109/23.819105, décembre 1999
 
46 Faccio F., Kloukinas K., Marchioro A., Calin T., Cosculluela J., Nicolaidis M., Velazco R., Single event effects in static and dynamic registers in a 0.25 mu m CMOS technology, IEEE Transactions on Nuclear Science, Ed. IEEE, Vol. 46, No. 6, pp. 1434-1439, DOI: 10.1109/23.819104, décembre 1999
 
47 Jarron P., Anelli G., Calin T., Cosculluela J., Campbell M., Delmastro M., Faccio F., Giraldo A., Heijne E., Kloukinas K., Letheren M., Nicolaidis M., Moreira P., Paccagnella A., Marchioro A., Snoeys W., Velazco R., Deep submicron CMOS technologies for the LHC experiments, Nuclear Physics B Proceedings Supplements, Vol. 78, pp. 625-634, août 1999
 
48 Asenek V., Underwood C., Velazco R., Rezgui S., Oldfield M., Cheynet P., Ecoffet R., SEU induced errors observed in microprocessor systems, IEEE Transactions on Nuclear Science, Ed. IEEE, Vol. 45, part 1, No. 6, pp. 2876-2883, DOI: 10.1109/23.736542, décembre 1998
 
49 Cheynet P., Velazco R., Rezgui S., Peters L., Beck K., Ecoffet R., Digital fuzzy control: a robust alternative suitable for space application, IEEE Transactions on Nuclear Science, Ed. IEEE, Vol. 45, No. 6, pp. 2941-2947, DOI: 10.1109/23.736550, décembre 1998
 
50 Buchner S., Olmos M., Cheynet P., Velazco R., Mcmorrow D., Mellinger J., Ecoffet R., Muller J.D., Pulsed laser validation of recovery mechanisms of critical SEEs in an artificial neural network system, IEEE Transactions on Nuclear Science, Ed. IEEE, Vol. 45, No. 3, pp. 1501-1507, DOI: 10.1109/23.685230, juillet 1998
 
51 Velazco R., Cheynet P., Muller J.D., Ecoffet R., Buchner S., Artificial neural network robustness for on-board satellite image processing: results of upset simulations and ground tests, IEEE Transactions on Nuclear Science, Ed. IEEE, Vol. 44, part. 1, No. 6, pp. 2337-2344, DOI: 10.1109/23.659057, décembre 1997
 
52 Velazco R., Assoum A., Cheynet P., Olmos M., Ecoffet R., SEU experiments on an Artificial Neural Network implemented by means of digital processors, IEEE Transactions on Nuclear Science, Ed. IEEE, Vol. 43, part. 1, No. 6, pp. 2889-2896, DOI: 10.1109/23.556882, décembre 1996
 
53 Velazco R., Calin T., Nicolaidis M., Moss S., La Lumondiere S.D., Tran V.T., Koga R., SEU-hardened storage cell validation using a pulsed laser, IEEE Transactions on Nuclear Science, Ed. IEEE, Vol. 43, No. 6 part 1, pp. 2843-2848, DOI: 10.1109/23.556875, décembre 1996
 
54 Calin T., Nicolaidis M., Velazco R., Upset hardened memory design for submicron CMOS technology, IEEE Transactions on Nuclear Science, Ed. IEEE, Vol. 43, No. 6 part 1, pp. 2874-2878, DOI: 10.1109/23.556880, décembre 1996
 
55 Velazco R., Assoum A., Radi M.E., Ecoffet R., Botey X., SEU fault tolerance in artificial neural networks, IEEE Transactions on Nuclear Science, Ed. IEEE, Vol. 42, part. 1, No. 6, pp. 1856-1862, DOI: 10.1109/23.489227, décembre 1995
 
56 Calin T., Vargas F., Nicolaidis M., Velazco R., A low-cost, highly reliable SEU-tolerant SRAM: prototype and test results, IEEE Transactions on Nuclear Science, Ed. IEEE, Vol. 42, No. 6 part 1, pp. 1592-1598, DOI: 10.1109/23.488754, décembre 1995
 
57 Velazco R., Karoui S., Chapuis T., Benedek Zs., Rosier L.H., Heavy ion test results for the 68020 microprocessor and the 68882 coprocesso, IEEE Transactions on Nuclear Science, Ed. IEEE, Vol. 39, Part 1-2, No. 3, pp. 436-440, DOI: 10.1109/23.277533, juin 1992
 
58 Caspi P., Piotrowski J., Velazco R., An a priori approach to the evaluation of signature analysis efficiency, IEEE Transactions on Computers, Ed. IEEE, Vol. 40, No. 9, pp. 1068-1071, DOI: 10.1109/12.83653, septembre 1991
 
59 Velazco R., Conard D., Guyot A., Ziade H., Top down IC failure analysis using an E-beam system coupled to a functional teste, Microelectronic Engineering, Ed. Elsevier, Vol. 12, No. 1-4, pp. 113-120, DOI: 10.1016/0167-9317(90)90022-L, mai 1990
 
60 Velazco R., Provost-Grellier A., Chapuis T., Labrunee M., Falguere D., Koga R., Comparison between Californian and cyclotron SEU tests, IEEE Transactions on Nuclear Science, Ed. IEEE, Vol. 36, part. 1, No. 6, pp. 2383-2387, DOI: 10.1109/23.45452, décembre 1989
 
61 Velazco R., Provost-Grellier A., Comparisons of tests using heavy ions from californium and from cyclotron, Annales de Physique, Vol. 14, No. 2, pp. 357-372, décembre 1989
 
62 Velazco R., Fault localisation when testing complex circuits, IEE Proceedings G : Electronic Circuits and Systems, Vol. 132(5), No. 5, pp. 241-245, octobre 1985
 
remonter

3 Brevets

1 Rezgui S., Velazco R., Method for error injection by interruptions, No. FR2819603, 19 juillet 2002
 
2 Bessot D., Velazco R., Memory cell insensitive to collisions of heavy ions, No. US5640341, 7 juin 1997
 
3 Velazco R., Bessot D., Cellule mémoire insensible aux rayonnements, No. WO9422144, 23 septembre 1994
 
remonter

12 Conférences invitées

 1 Velazco R., Error-rate prediction for programmable circuits: methodology, tools and studied cases, Invited Talk, 2nd Aerospace Bolivian Conference (ABC’16), La Paz, BOLIVIA, 27 au 29 juillet 2016
 
 2 Velazco R., Error rate prediction for programmable circuits: methodology, tools and studied cases, Workshop on the Effects of Ionizing Radiation on Electronic and Photonic Components for Aerospacial applications (WERICE'15), São José dos Campos, BRAZIL, 3 au 5 novembre 2015
 
 3 Velazco R., Effects of radiation in digital integrated circuits: origins, mitigation technics and experimental tests, IEEE WESCIS (Education Society and Computer Intelligence Society), Tucuman, ARGENTINA, 2 octobre 2015
 
 4 Velazco R., Error-rate prediction for programmable circuits: methodology, tools and studied cases , SPIE Micro- and Nanotechnology Sensors, Systems, and Applications, pp. 1-8, Baltimore, MD, UNITED STATES, DOI: 10.1117/12.2015391, 29 mai 2013
 
 5 Velazco R., Soft-error-rate prediction for programmable circuits: methodology, tools and studied cases , Conférence magistrale in Congreso Internacional de Ingenieria Eléctrica, Electrónica, Sistemas y Ramas Afines (XVIII INTERCON), Lima, PERU, 8 au 12 août 2011
 
 6 Velazco R., Effects of Radiation on Integrated Circuits : origines, mitigation techniques, test and real-life experiments, Conférence magistrale in Congreso de Informática Univ. Tecnológica de Machala (III CIU/), Machala, ECUADOR, 15 au 17 juin 2011
 
 7 Velazco R., Error Rate Predictions for Programmable Circuits: Methodology, Tools and Studied Cases, International Workshop on Radiation Effects on Semiconductor Devices for Space Applications (RASEDA'10), Takasaki, JAPAN, 27 au 29 octobre 2010
 
 8 Velazco R., Effects of natural radiation on integrated circuits: origins, mitigation techniques and experiments in the natural environment , Congreso Nacional de Estudiantes de Ingenieria Mecanica, Electronica Electrica, y Ramas Afines (CONEIMERA'10), Trujillo, PERU, 20 au 25 septembre 2010
 
 9 Velazco R., Single Events on Digital Integrated Circuits , Bolivian Engineering and Technology Congress (BETCON'10), La Paz, BOLIVIA, 10 au 14 mai 2010
 
10 Velazco R., Managing transient effects of radiation on complex microelectronic systems, Invited Talk, ANDESCON 2008, Cusco, PERU, 15 au 17 octobre 2008
 
11 Velazco R., Single Event Effects on digital integrated circuits: origins and mitigation techniques, IEEE International Symposium on Industrial Electronics (ISIE'07), Vigo, SPAIN, 4 au 7 juin 2008
 
12 Velazco R., Managing transient effects of radiation on complex microelectronic systems, Design of Circuits and Integrated Systems (DCIS’06), Barcelone, SPAIN, 22 au 24 novembre 2006
 
remonter

161 Conférences internationales

  1 Coelho A., Charif A., Zergainoh N.-E., Velazco R., A Runtime Fault-Tolerant Routing Scheme for Partially Connected 3D Networks-on-Chip, IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT 2018), pp. 1-6, Chicago, UNITED STATES, 8 au 10 octobre 2018
 
  2 Garay Trindade M., Coelho A., Valadares C., Andreoni Camponogara Viera R., Rey S., Cheymol B., Baylac M., Velazco R., Possamai Bastos R., Assessment of Hardware-Implemented Support Vector Machine under Radiation Effects, Conference on Radiation Effects on Components and Systems (RADECS'2018), Gothenburg, SWEDEN, 16 au 21 septembre 2018
 
  3 Coelho A., Charif A., Zergainoh N.-E., Fraire J., Velazco R., A soft-error resilient route computation unit for 3D Networks-on-Chips, Design, Automation & Test in Europe (DATE'2018), Dresden, GERMANY, 19 au 23 mars 2018
 
  4 Fraire J., Madoery P., Raverta F., Finochietto J., Velazco R., DtnSim: Bridging the Gap Between Simulation and Implementation of Space-Terrestrial DTNs, 6th Conference on Space Mission Challanges for Information Technologies (SMC-IT 2017), Alcalá de Henares, SPAIN, 27 septembre 2017
 
  5 Solinas M., Coelho A., Fraire J., Zergainoh N.-E., Velazco R., TGV: Tester Generic and Versatile for Radiation Effects on Advanced VLSI Circuits, IEEE/ACM Design, Automation, and Test in Europe (DATE 2017), Univ. Booth, Lausanne, SWITZERLAND, 27 au 31 mars 2017
 
  6 Bonnoit T., Coelho A., Zergainoh N.-E., Velazco R., SEU Impact in Processor's Control-Unit: Preliminary Results Obtained for LEON3 Soft-Core, 18th IEEE Latin American Test Symposium (LATS 2017), pp. 1-4, Bogota, COLOMBIA, 13 au 15 mars 2017
 
  7 Barrientos J., Ferral A., Cara L., Fraire J., Velazco R., Madoery P., Ferreyra P., A Segmented Architecture Approach to Provide a Continuous, Long-Term, Adaptive and Cost-effective Glaciers Monitoring System Based on DTN Communications and Cubesat Platforms, 1st IAA Latin American Symposium on Small Satellites: Advanced Technologies and Distributed Systems, Buenos Aires, ARGENTINA, 7 au 10 mars 2017
 
  8 Ferreyra P., Fraire J., Gomez F., Barrientos J., Velazco R., Enhancing Contact Graph Routing Forwarding Performance for Segmented Satellites Architectures, 1st IAA Latin American Symposium on Small Satellites: Advanced Technologies and Distributed Systems, San Martin Buenos Aires, ARGENTINA, 7 au 10 mars 2017
 
  9 Solinas M., Coelho A., Fraire J., Zergainoh N.-E., Ferreyra P., Velazco R., Preliminary Results of NETFI-2: An Automatic Method for Fault Injection on HDL-Based Designs, 18th IEEE Latin-American Test Symposium (LATS 2017), Bogota, COLOMBIA, 1 mars 2017
 
 10 Bonnoit T., Zergainoh N.-E., Nicolaidis M., Velazco R., Low Cost Rollback to Improve Fault-Tolerance in VLSI Circuits, IEEE International Symposium on Circuits and Systems (LASCAS 2017), pp. 1-4, Bariloche, ARGENTINA, 20 au 23 février 2017
 
 11 Solinas M., Fraire J., Coderch N., Ferrer A., Velazco R., Primeros Resultados con NETFI-2: Una Nueva Herramienta para la Inyección de Fallos en Diseños Basados en HDL, VII Congreso de Microelectrónica Aplicada, San Luis, ARGENTINA, 26 au 28 octobre 2016
 
 12 Clemente J.A., Hubert G., Franco F., Villa F., Baylac M., Mecha H., Velazco R., Evaluation of the Sensitive of a COTS 90-nm Memory at Low Bias Voltage, Radiation and its Effects on Components and Systems (RADECS'16)), Bremen, GERMANY, 19 au 23 septembre 2016
 
 13 Coelho A., Solinas M., Laurent R., Fraire J., Mazer E., Zergainoh N.-E., Karaoui S., Velazco R., Evidences of Stochastic Bayesian Machines Robustness Against SEUs and SETs, IEEE European Conference on Radiation and its Effects on Components and Systems (RADECS'16), Bremen, GERMANY, 19 au 23 septembre 2016
 
 14 Franco F., Clemente J.A., Baylac M., Rey S., Villa F., Mecha H., Agapito J.-A., Puchner H., Hubert G., Velazco R., Some Properties of only-SBUs Scenarios in SRAMs Applied to the Detection of MCUs, Radiation and its Effects on Components and Systems (RADECS'16), Bremen, GERMANY, 19 au 23 septembre 2016
 
 15 Fraire J., Madoery P., Finochietto J., Ferreyra R., Velazco R., Internetworking Approaches Towards Along-Track Segmented Satellite Architectures, IEEE International Conference on Wireless for Space and Extreme Environments (WiSEE'16), Aachen, GERMANY, 1 au 9 septembre 2016
 
 16 Souari A., Thibeault Cl., Blaquière Y., Velazco R., An Automated Fault Injection for Evaluation of LUTs Robustness in SRAM-Based FPGAs, IEEE East-West Design & Test Symposium (EWDTS’15), Batumi, GEORGIA, 26 au 29 septembre 2015
 
 17 Clemente J.A., Franco F., Villa F., Baylac M., Ramos P., Vargas V., Mecha H., Agapito J.-A., Velazco R., Neutron-Induced Single Events in a COTS Soft-Error Free SRAM at Low Bias Voltage, Radiation and its Effects on Components and Systems (RADECS’15), pp. 1-4, Moscow, RUSSIAN FED, DOI: 10.1109/RADECS.2015.7365640 , 14 au 18 septembre 2015
 
 18 Ramos P., Vargas V., Baylac M., Villa F., Rey S., Clemente J.A., Zergainoh N.-E., Velazco R., Sensitivity to Neutron Radiation of a 45 nm SOI Multi-Core Processor, Radiation and Its Effects on Components and Systems (RADECS’15), Moscow, RUSSIAN FED, DOI: 10.1109/RADECS.2015.7365665 , 14 au 18 septembre 2015
 
 19 Clemente J.A., Franco F., Villa F., Baylac M., Rey S., Mecha H., Agapito J.-A., Puchner H., Hubert G., Velazco R., Statistical Anomalies of Bitflips in SRAMs to Discriminate MCUs from SEUs, Radiation and its Effects on Components and Systems (RADECS’15), pp. 1-4, Moscow, RUSSIAN FED, DOI: 10.1109/RADECS.2015.7365670, 14 au 18 septembre 2015
 
 20 Souari A., Thibeault Cl., Blaquière Y., Velazco R., Optimization of SEU emulation on SRAM FPGAs based on sensitiveness analysis, 21st International On-Line Testing Symposium (IOLTS'15), pp. 36-39, Halkidiki, GREECE, DOI: 10.1109/IOLTS.2015.7229827, 6 au 8 juillet 2015
 
 21 Vargas V., Ramos P., Velazco R., Méhaut J-F., Zergainoh N.-E., Evaluating SEU fault-injection on parallel applications implemented on multicore processors, IEEE 6th Latin American Symposium on Circuits & Systems (LASCAS'15), pp. 1-4, Montevideo, URUGUAY, DOI: 10.1109/LASCAS.2015.7250449, 25 au 27 février 2015
 
 22 Villa F., Baylac M., Rey S., Rossetto O., Mansour W., Ramos P., Velazco R., Hubert G., Accelerator-Based Neutron Irradiation of Integrated Circuits at GENEPI-2 (France), REDW (Radiation Effects Data Workshop) of IEEE NSREC (Nuclear and Space Radiation Effects Conference), pp. 1-5, Paris, FRANCE, DOI: 10.1109/REDW.2014.7004511, 14 au 18 juillet 2014
 
 23 Velazco R., Mansour W., Baylac M., Rey S., Rossetto O., Villa F., Clemente J.A., Palomar C., Franco F., Evidences of the robustness of a COTS soft-error free SRAM to neutron radiation, IEEE Nuclear and Space Radiation Effects Conference (NSREC'14), Paris, FRANCE, 14 au 18 juillet 2014
 
 24 Souari A., Thibeault Cl., Blaquière Y., Velazco R., Towards a realistic SEU effects emulation on SRAM Based FPGAs, IEEE Nuclear and Space Radiation Effects Conference (NSREC '14), Paris, FRANCE, 14 au 18 juillet 2014
 
 25 Vargas V., Ramos P., Mansour W., Méhaut J-F., Velazco R., Zergainoh N.-E., Preliminary results of SEU Fault Injection on Multicore processors in AMP mode, 20th IEEE International On-Line Testing Symposium (IOLTS’14), pp. 194-197, Platja d'Aro, Girona, SPAIN, DOI: 10.1109/IOLTS.2014.6873694, 7 au 9 juillet 2014
 
 26 Mansour W., Aguirre M., Guzman-Miranda H., Barrientos J., Velazco R., Two complementary approaches for studying the effects of SEUs on HDL-based designs, 20th IEEE International On-Line Testing Symposium (IOLTS’14), pp. 220-221, Platja d'Aro, Girona, SPAIN, DOI: 10.1109/IOLTS.2014.6873702, 7 au 9 juillet 2014
 
 27 Mansour W., Ramos P., Ayoubi R., Velazco R., SEU fault-injection at system level: method, tools and preliminary results, Latin American Test Workshop (LATW'14), Fortaleza, BRAZIL, 12 au 15 mars 2014
 
 28 Mansour W., Velazco R., Ayoubi R., El Falou W., Ziade H., Fault-tolerance capabilities of a software-implemented Hopfield Neural Network, 3rd International Conference on Communications and Information Technology (ICCIT'13), pp. 205 - 208 , Beirut, LEBANON, DOI: 10.1109/ICCITechnology.2013.6579550 , 19 au 21 juin 2013
 
 29 Marques C.A., Mansour W., Pancher F., Bui A., Sohier D., Velazco R., Optimization of a self-converging algorithm at assembly level to improve SEU Fault-Tolerance, 4th Latin American Symposium on Circuits And Systems (LASCAS'13), Cusco, PERU, DOI: 10.1109/LASCAS.2013.6519033, 27 février au 1 mars 2013
 
 30 Mansour W., Velazco R., An automated SEU fault-injection method and tool for HDLbased designs, Radiation Effects on Components and Systems (RADECS'12), Biarritz, FRANCE, 24 au 28 septembre 2012
 
 31 Cheminet A., Hubert G., Lacoste V., Velazco R., Boscher D., Characterization of the neutron environment at the CERN-EU High Energy Reference Field and at the Pic du Midi, Radiation Effects on Components and Systems (RADECS'12), Biarritz, FRANCE, 24 au 28 septembre 2012
 
 32 Hubert G., Velazco R., Federico C.A., Cheminet A., Silva Cardenas C., Caldas L.V., Pancher F., Lacoste V., Palumbo F., Mansour W., Artola L., Pineda F., Duzellier S., Continuous high-altitude measurements of cosmic ray neutrons and SEU/MCU at various locations: correlation and analyses based on MUSCA SEP3, Radiation Effects on Components and Systems (RADECS'12), Biarritz, FRANCE, 24 au 28 septembre 2012
 
 33 Hubert G., Bourdarie S., Velazco R., Artola L., Duzellier S., Ecoffet R., Operational risk assessment at solar events using a new statistical approach for SEU rate prediction, Nuclear and Space Radiation Effects Conference (NSREC'12), Miami, UNITED STATES, 16 au 20 juillet 2012
 
 34 Mansour W., Velazco R., SEU Fault-Injection in VHDL-Based Processors: A Case Study, 13th Latin-American Test Workshop (LATW'12), Quito, ECUADOR, DOI: 10.1109/LATW.2012.6261258, 11 au 13 avril 2012
 
 35 Velazco R., Mansour W., Pancher F., Costa-Marques G., Sohier D., Bui A., Improving SEU fault tolerance capabilities of a self-converging algorithm, European Conference on Radiation Effects on Component and Systems (RADECS’11), Sevilla, SPAIN, 19 au 23 septembre 2011
 
 36 Azambuja J.R., Pagliarini S., Altieri M., Lima F., Hübner M., Foucard G., Velazco R., Non-Intrusive Reconfigurable HW/SW Fault Tolerance Approach to Detect Transient Faults in Microprocessor Systems, 12th European Conference on Radiation and its Effects on Components and Systems (RADECS’11), Sevilla, SPAIN, 19 au 23 septembre 2011
 
 37 Velazco R., Foucard G., Pancher F., Mansour W., Costa-Marques G., Sohier D., Bui A., Robustness with respect to SEUs of a self-converging algorithm, IEEE Latin America Test Symposium Workshop (LATW’11), pp. 1 - 5 , Porto de Galinhas (PE), BRAZIL, DOI: 10.1109/LATW.2011.5985916 , 27 au 30 mars 2011
 
 38 Sanchez A.E., Ferreyra P., Marques C.A., Velazco R., Performance de Computadoras SIMD Implementadas en FPGAs, XVII IBERCHIP Workshop, Bogotá, COLOMBIA, 23 au 25 février 2011
 
 39 Peronnard P., Velazco R., Cabanillas E., Al Falou W., Ziade H., Evaluation of the soft error rate of a space application executed by a real time operating system, International Middle Eastern Multiconference on Simulation and Modelling (MESM'09), pp. 84-90, Beyrouth, LEBANON, 27 au 29 septembre 2009
 
 40 Hubert G., Velazco R., Peronnard P., A generic platform for remote accelerated tests and high altitude SEU experiments on advanced ICs: Correlation with MUSCA SEP3 calculations, International On-Line Test Symposium (IOLTS’09), pp. 180 - 180 , Sesimbra-Lisbon, PORTUGAL, DOI: 10.1109/IOLTS.2009.5196005 , 24 au 26 juin 2009
 
 41 Brac E., Ferreyra P., Velazco R., Marques C.A., A New Automatic VHDL Fault Injection Tool: A case studied, IBERCHIP Workshop, pp. 459-462, Buenos Aires, ARGENTINA, 25 au 27 mars 2009
 
 42 Velazco R., Peronnard P., Silva Cardenas C., Fernandez S., High altitude experiments to evaluate SEU sensitivity of advanced SRAMs, IBERCHIP Workshop, pp. 463-466, Buenos Aires, ARGENTINA, 25 au 27 mars 2009
 
 43 Ziade H., Velazco R., Ayoubi R., Idriss T., MSI: A Multiple SEU Injection Method for FPGAs, International Conference on Information Science, Technology and Applications (ISTA’09), Kuwait, KUWAIT, 20 au 22 mars 2009
 
 44 Brac E., Ferreyra P., Velazco R., Marques C.A., Test and qualification of a Fault Tolerant FPGA based Active Antenna System for space applications, Latin American Test Workshop (LATW’09), pp. 1 - 5 , Buzios, Rio de Janeiro, BRAZIL, DOI: 10.1109/LATW.2009.4813814 , 3 au 5 mars 2009
 
 45 Brac E., Ferreyra P., Velazco R., Marques C.A., Naguil J., Ferreyra R., Gastaldi R., Extending the Use of Failure Maps for FPGA Based Applications: A Case Studied, 23rd International Conference on Design of Circuits and Integrated Systems (DCIS’08), pp. Session 2D2 , Grenoble, FRANCE, 12 au 14 novembre 2008
 
 46 Peronnard P., Velazco R., Foucard G., Impact of the Software optimization on the Soft Error Rate: a case study, 23rd International Conference on Design of Circuits and Integrated Systems (DCIS’08), pp. session 4D3, Grenoble, FRANCE, 12 au 14 novembre 2008
 
 47 Foucard G., Perronnard P., Velazco R., Ferron J.B., Douin A., Pouget V., Bocquillon A., Miller F., Berger G., Charlier F., Boldrin F., Methodologies and Tools for the Evaluation of the Sensitivity to Radiation of SRAM-based FPGAs, 23rd International Conference on Design of Circuits and Integrated Systems (DCIS’08), pp. session 6D1 , Grenoble, FRANCE, 12 au 14 novembre 2008
 
 48 Lisboa C.A., Peronnard P., Rhod E., Velazco R., Carro L., Validation by Fault Injection of a Hardening Technique for Matrix Multiplication Algorithms , European Workshop on Radiation Effects on Components and Systems (RADECS’08), pp. 321-324, Jyväskylä, FINLAND, 10 au 12 septembre 2008
 
 49 Peronnard P., Velazco R., Foucard G., Pouget V., Berger G., Charlier F., Boldrin F., Remote SEE Testing Capabilities with Heavy Ions and Laser Beams at CYCLONE-HIF and ATLAS Facilities, Radiation Effects Data Workshop, pp. 106-109, Tucson, AZ, UNITED STATES, DOI: 10.1109/REDW.2008.26, 14 au 18 juillet 2008
 
 50 Pouget V., Douin A., Foucard G., Peronnard P., Lewis D., Fouillat P., Velazco R., Dynamic Testing of an SRAM-Based FPGA by Time-Resolved Laser Fault Injection, 14th IEEE International Symposium On-Line Testing (IOLT’08), pp. 295-301, Rhodes, GREECE, DOI: 10.1109/IOLTS.2008.39 , 7 au 9 juillet 2008
 
 51 Peronnard P., Ecoffet R., Pignol M., Bellin D., Velazco R., Foucard G., Predicting the SEU Error Rate through Fault Injection for a Complex Microprocessor, IEEE International Symposium on Industrial Electronics (ISIE'2008), pp. 2288-2292, Cambridge, UNITED KINGDOM, DOI: 10.1109/ISIE.2008.4677290, 30 juin au 2 juillet 2008
 
 52 Velazco R., Peronnard P., Foucard G., Fernandez S., Pechiar J., A generic platform for SEE high altitude experiments, Conference RADSOL “Electronique et rayonnements naturels au niveau du sol", Paris, FRANCE, 11 au 12 juin 2008
 
 53 Bellin D., Velazco R., Peronnard P., Pignol M., Ecoffet R., Alexandrescu D., Gauthier D., Single-Event Upset and Soft Error Rate in Power ArchitectureTM microprocessors, Components for Military and Space Electronics (CMSE’08), pp. 383-394, San Diego, CA, UNITED STATES, 11 au 14 février 2008
 
 54 Bocquillon A., Foucard G., Miller F., Buard N., Leveugle R., Daniel C., Rakers S., Carriere T., Pouget V., Velazco R., Highlights of laser testing capabilities regarding the understanding of SEE in SRAM Based FPGAs, 9th European Conference on Radiation and its Effects on Components and Systems (RADECS’07), Deauville, FRANCE, DOI: 10.1109/RADECS.2007.5205500, 10 au 14 septembre 2007
 
 55 Ferrer A., Velazco R., Ecoffet R., Bezerra F., Error rate issued from a multiple upset injection method with realistic time distribution: A case study, 8th Latin-American Test Workshop (LATW’07), Cuzco, PERU, 12 au 14 mars 2007
 
 56 Fernandes J. M., Santos M.B., Oliveira A. L., Teixeira J.P., Velazco R., Sensitivity to SEUs evaluation using probabilistic testability analysis at RTL, 8th Latin-American Test Workshop (LATW’07), Cuzco, PERU, 12 au 14 mars 2007
 
 57 Espinosa-Duran J.- M., Velasco-Medina J., Huertas G., Velazco R., Huertas J.L., Single event transient injection on an operational amplifier: a case study, 8th Latin-American Test Workshop (LATW’07), pp. session 8, Cuzco, PERU, 12 au 14 mars 2007
 
 58 Franco F., Velazco R., A Portable Low-Cost SEU Evaluation Board for SRAMs, Spanish Conference on Electron Devices (SCED’07), pp. 165-168, Madrid, SPAIN, DOI: 10.1109/SCED.2007.384018, 31 janvier au 2 février 2007
 
 59 Pouget V., Douin A., Lewis D., Fouillat P., Foucard G., Peronnard P., Maingot V., Ferron J.B., Anghel L., Leveugle R., Velazco R., Tools and methodology development for pulsed laser fault injection in SRAM-based FPGAs, 8th Latin-American Test Workshop (LATW’07), pp. 167-172, Cuzco, PERU, 12 au 14 janvier 2007
 
 60 Ferreyra P., Viganotti G., Marques C.A., Velazco R., Ferreyra R., Failure and coverage factors based Markoff models: a new approach for improving the dependability estimation in complex fault tolerant systems exposed to SEUs, Radiation and its Effects on Components and Systems (RADECS'06), pp. PA-9, Athens, GREECE, 16 au 19 septembre 2006
 
 61 Sager G.E., Alurralde M., Palumbo F., Prario I., Filevich A., Vertanessian A., Velazco R., Ferreyra P., TANDAR as a digital circuits test radiation facility, Latin American Test Workshop (LATW’06), pp. 179-183, Buenos Aires, ARGENTINA, 26 au 29 mars 2006
 
 62 Torrellas S., Nicolescu B., Valderas M.G., Velazco R., Savaria B.Y., Validation by fault injection of a software error detection technique dealing with critical Single Event Upsets, Latin American Test Workshop (LATW’06), pp. 111-116, Buenos Aires, ARGENTINA, 26 au 29 mars 2006
 
 63 Velazco R., Ecoffet R., Faure F., How to characterize the problem of SEU in processors & representative errors observed on flight, 11th-IEEE-International-On-Line-Testing-Symposium (IOLTS'05), pp. 303-308, Saint-Raphaël, FRANCE, DOI: 10.1109/IOLTS.2005.32, 6 au 8 juillet 2005
 
 64 Sonza Reorda M., Velazco R., Sanchez E., Squillero G., Automatic verification of RT-level microprocessor cores using behavioral specifications: a case study, XIX Conference on Design of Circuits and Integrated Systems (DCIS'04), Bordeaux, FRANCE, 24 au 26 novembre 2004
 
 65 Anghel L., Velazco R., Sanchez E., Sonza Reorda M., Squillero G., Coupling Different Methodologies to Validate Obsolete Microprocessors, 19th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'04), pp. 250-255, Cannes, FRANCE, DOI: 10.1109/DFT.2004.21, 10 au 13 octobre 2004
 
 66 Nicolescu B., Gorse N., Savaria B.Y., Aboulhamid E.M., Velazco R., Validating a dynamic signature monitoring approach using the LTL model checking technique, Radiation and Effects on Components and Systems Workshop (RADECS'04), Madrid, SPAIN, 22 au 24 septembre 2004
 
 67 Savaria B.Y., Nicolescu B., Velazco R., Performance evaluation and failure prediction for the soft implemented error detection technique, 10th International On-Line Testing Symposium (IOLTS'04), Funchal, Mareira, PORTUGAL, 12 au 14 juillet 2004
 
 68 Nicolescu B., Savaria B.Y., Velazco R., Performance evaluation and failure rate prediction for the soft implemented error detection technique, 10th IEEE International On Line Testing Symposium (IOLTS'04), pp. 233-238, Funchal, Madeira Island, PORTUGAL, 12 au 14 juillet 2004
 
 69 Nicolescu B., Savaria B.Y., Velazco R., SIED: software implemented error detection, 18th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'03), pp. 589-596, Boston, MA., UNITED STATES, DOI: 10.1109/DFTVS.2003.1250159, 5 novembre 2003
 
 70 Nicolescu B., Perronnard P., Velazco R., Savaria B.Y., Efficiency of transient bit-flips detection by software means: a complete study, 18th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'03), pp. 377-384, Boston, MA., UNITED STATES, DOI: 10.1109/DFTVS.2003.1250134, 3 au 5 novembre 2003
 
 71 Anghel L., Velazco R., Saleh S., Deswaertes S., El Moucary A., Preliminary Validation of an Approach Dealing with Processor Obsolescence, 18th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'03), pp. 493-500, Boston, MA, UNITED STATES, DOI: 10.1109/DFTVS.2003.1250148, 3 au 5 novembre 2003
 
 72 Alderighi M., Casini F., D'Angelo S., Faure F., Mancini M., Pastore S., Sechi G.R., Velazco R., Proposal for a radiation test of Virtex-based ALUs, 7th European Conference on Radiation and its Effects on Components and Systems (RADECS'03), pp. 341-345, Noordwijk, NETHERLANDS, 15 au 19 septembre 2003
 
 73 Faure F., Velazco R., Single event upsets on a read only memory based complex programmable logic device, 7th European Conference on Radiation and its Effects on Components and Systems (RADECS'03), pp. 279-282, Noordwijk, NETHERLANDS, 15 au 19 septembre 2003
 
 74 Pouget V., Fouillat P., Velazco R., Lewis D., Dallet D., Performance impact of various SEE mechanisms in classical analog-to-digital converter architectures, IEEE Nuclear and Space Radiation Effects Conference (NSREC'03), Monterey, CA, UNITED STATES, 19 au 23 juillet 2003
 
 75 Alderighi M., Casini F., D'Angelo S., Faure F., Mancini M., Pastore S., Sechi G.R., Velazco R., Radiation test methodology for SRAM-based FPGAs by using THESIC+, 9th IEEE International On Line Testing Symposium (IOLTS'03), pp. 162, Kos Island, GREECE, 7 au 9 juillet 2003
 
 76 Nicolescu B., Velazco R., Detecting soft errors by a purely software approach: method, tools and experimental results, Design, Automation and Test in Europe Conference and Exhibition (DATE'03), pp. 57-62, Munich, GERMANY, DOI: 10.1109/DATE.2003.10224, 3 au 7 mars 2003
 
 77 Nicolescu B., Velazco R., Efficiency of a software approach for transient error detection: a case study, 4th IEEE Latin-American Test Workshop (LATW'03), Natal, BRAZIL, 16 au 19 février 2003
 
 78 Velazco R., Anghel L., Saleh S., A Methodology for Test Replacement Solutions of Obsolete Processors, 9th IEEE International On-Line Testing Symposium (IOLTS'03), pp. 209-213, Kos Island, GREECE, DOI: 10.1109/OLT.2003.1214400, 7 au 9 janvier 2003
 
 79 Velazco R., Ferreyra P., Corominas Murtra A., Injecting bit flip faults by means of a purely software approach : a case studied, IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'02), Vancouver, BC, CANADA, 6 au 8 novembre 2002
 
 80 Velazco R., Corominas Murtra A., Ferreyra P., Injecting bit flip faults by means of a purely software approach: a case studied, 17th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'02), pp. 108-116, Vancouver, BC, CANADA, DOI: 10.1109/DFTVS.2002.1173507, 6 au 8 novembre 2002
 
 81 Corominas Murtra A., Velazco R., Ecoffet R., Predicting error rates provoked by radiation in digital architectures: methods and tools, 5th Workshop on Radiation Effects on Semiconductor Devices for Space Application (RESEDA'02), Takasaki, JAPAN, 8 au 10 octobre 2002
 
 82 Corominas Murtra A., Nicolescu B., Velazco R., An automated technique to provide software applications with SEU detection capabilities: basic principles and preliminary results, Radiation and its effects on Components and Systems Workshop (RADECS'02), Padova, ITALY, 19 au 20 septembre 2002
 
 83 Nicolescu B., Velazco R., Sonza Reorda M., Rebaudengo M., Violante M., A software fault tolerance method for safety-critical systems: effectiveness and drawbacks, 15th Symposium on Integrated Circuits and Systems Design (SBCCI'02), pp. 101-106, Porto Alegre, RS, BRAZIL, 9 au 13 septembre 2002
 
 84 Duzellier S., Bourdarie S., Velazco R., Nicolescu B., Ecoffet R., SEE in-flight data for two static 32KB memories on high earth orbit, IEEE Radiation Effects Data Workshop (REDW'02), pp. 1-6, Phoenix, Arizona, UNITED STATES, DOI: 10.1109/REDW.2002.1045524, 15 au 19 juillet 2002
 
 85 Cardarilli G.C., Kaddour F., Leandri A., Ottavi M., Pontarelli S., Velazco R., Bit flip injection in processor-based architectures: a case study, Eighth IEEE International On Line Testing Workshop (IOLTW'02), pp. 117-127, Isle of Bendor, FRANCE, DOI: 10.1109/OLT.2002.1030194, 8 au 10 juillet 2002
 
 86 Kaddour F., Rezgui S., Velazco R., Rodriguez S., De-Mingo J.R., Error Rate Estimation for a Flight Application Using the CEU Fault Injection Approach, Eighth IEEE International On Line Testing Workshop (IOLTW'02), pp. 195, Isle of Bendor, FRANCE, DOI: 10.1109/OLT.2002.1030218, 8 au 10 juillet 2002
 
 87 Carro L., Reis R., Velazco R., Injecting multiple upsets a SEU tolerant 8051 micro-controller, 8th IEEE International On-Line Testing Workshop (IOLT'02), Ile de Bendor, FRANCE, 8 au 10 juillet 2002
 
 88 Lima F., Carro L., Velazco R., Reis R., Injecting multiple upsets in a SEU tolerant 8051 micro-controller, Eighth IEEE International On Line Testing Workshop (IOLTW'02), pp. 194, Ile de Bendor, FRANCE, DOI: 10.1109/OLT.2002.1030217, 8 au 10 juillet 2002
 
 89 Chardonnereau D., Keulen R., Nicolaidis M., Dupont E., Torki K., Faure F., Velazco R., Fault Tolerant 32-bit RISC Processor: Implementation and Radiation Test Results, Single Event Effects Symposium (SEE'02), Manhattan Beach, California, UNITED STATES, 23 au 25 avril 2002
 
 90 Velazco R., Faure F., A flexible platform for the functional validation of programmable circuits, WRTLT Workshop (RTL ATPG and DFT Workshop) (WRTLT'01), Nara, JAPAN, 21 au 23 novembre 2001
 
 91 Calvo O., Velazco R., VHDL fault injection of SEUs in on FPGA based Fuzzy Logic Controller, 16th Conference on Design of Circuits and Integrated Systems (DCIS'01), Porto, PORTUGAL, 20 au 23 novembre 2001
 
 92 Velazco R., Leveugle R., Calvo O., Upset-like fault injection in VHDL descriptions: A method and preliminary results, IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'01), pp. 259-267, San Francisco, CA, UNITED STATES, DOI: 10.1109/DFTVS.2001.966778, 24 au 26 octobre 2001
 
 93 Velazco R., Olmos S., Ecoffet R., Nicolescu B., Dupont E., A flight experiment for the evaluation of hardware and software fault tolerance techniques, 52nd International Astronautical Congress (IAF'01), Toulouse, FRANCE, 1 au 5 octobre 2001
 
 94 Sonza Reorda M., Nicolescu B., Rebaudengo M., Violante M., Velazco R., Coping with SEUs/SETs in microprocessors by means of low-cost solutions: a comparative study and experimental results, 6th European Conference on Radiation and its Effects on Components and Systems (RADECS'01), Grenoble, FRANCE, 10 au 14 septembre 2001
 
 95 Ferreyra P., Marques C.A., Velazco R., Calvo O., Injecting single event upsets in a digital signal processor by means of direct memory access requests: a new method for generating bit flips, 6th IEEE Radiation and its Effects on Components and Systems (RADECS'01), pp. 248-252, Grrenoble, FRANCE, DOI: 10.1109/RADECS.2001.1159288, 10 au 14 septembre 2001
 
 96 Lima F., Rezgui S., Carro L., Velazco R., Reis R., On the use of VHDL simulation and emulation to derive error rates, 6th European Conference on Radiation and Its Effects on Components and Systems (RADECS'01), pp. 253-260, Grenoble, FRANCE, DOI: 10.1109/RADECS.2001.1159289, 10 au 14 septembre 2001
 
 97 Hansen H., Rezgui S., Convert P., Guerard B., Velazco R., Using the ILL facility to evaluate the sensitivity of integrated circuits to thermal neutrons, 6th Conference on Radiation and its Effects on Components and Systems (RADECS' 01), Grenoble, FRANCE, 10 au 14 septembre 2001
 
 98 Nicolescu B., Velazco R., Sonza Reorda M., Effectiveness and limitations of various software techniques for , Seventh International On Line Testing Workshop (IOLTW'01), pp. 172-177, Taormina, ITALY, DOI: 10.1109/OLT.2001.937838, 9 au 11 juillet 2001
 
 99 Velazco R., Rezgui S., Reguer E., THESIC : Una plataforma flexible para la validation funcional de circuitos integrados, IBERCHIP, Montevideo, URUGUAY, 23 au 28 mars 2001
 
100 Cheynet P., Nicolescu B., Velazco R., Rebaudengo M., Sonza Reorda M., Violante M., System safety through automatic high-level code transformations: an experimental evaluation, Design, Automation and Test in Europe. Conference and Exhibition (DATE'01), pp. 297-301, Munich, GERMANY, DOI: 10.1109/DATE.2001.915040, 13 au 16 mars 2001
 
101 Velazco R., Rezgui S., Ziade H., Assessing the soft error rate of digital architectures devoted to operate in radiation environment: a case studied, IEEE Latin-American Test Workshop (LATW'01), Cancun, MEXICO, 11 au 14 février 2001
 
102 Rezgui S., Velazco R., Mingo J.R., Rodriguez S., Ground testing of architecture including digital processor signal AD21060, European Conference on Digital Signal Processing (DSP'00), Munich, GERMANY, 11 au 12 octobre 2000
 
103 Rezgui S., Velazco R., Ecoffet R., Rodriguez S., A new methodology for the simulation of soft errors on microprocessors : a case study, Military and Aerospace of Programmable Devices and Technologies (MAPLD'00), Laurel, Maryland, UNITED STATES, 26 au 28 septembre 2000
 
104 Velazco R., Rezgui S., Cota E.F., Lubaszewski M., Lima F., Designing and testing a radiation hardened 8051-like micro-controller, Military and Aerospace of Programmable Devices and Technologies (MAPLD'00), Laurel, Maryland, UNITED STATES, 26 au 28 septembre 2000
 
105 Rezgui S., Cota E.F., Carro L., Lubaszewski M., Reis R., Velazco R., Designing a radiation hardened 8051-like micro-controller, 13th Symposium on Integrated Circuits and Systems Design (SBCC'00), pp. 255-260, Manaus, BRAZIL, DOI: 10.1109/SBCCI.2000.876039, 18 au 24 septembre 2000
 
106 Velazco R., Cheynet P., Tissot A., Haussy J., Lambert J., Ecoffet R., Evidences of SEU tolerance for digital implementations of artificial neural networks: one year MPTB flight results, Fifth European Conference on Radiation and Its Effects on Components and Systems (RADECS'99), pp. 565-568, Abbaye de Fontevraud, FRANCE, DOI: 10.1109/RADECS.1999.858648, 13 au 17 septembre 2000
 
107 Rezgui S., Velazco R., Ecoffet R., Rodriguez S., Mingo J.R., Estimating error rates in processor-based architectures, Workshop on Radiation Effects on Components and Systems (RADECS'00), Louvain-la-Neuve, BELGIUM, 11 au 13 septembre 2000
 
108 Vargas F., Amory A., Velazco R., Estimating Circuit Fault-Tolerance by Means of Transient-Fault Injection in VHDL, 6th IEEE International On-Line Testing Workshop (IOLTW'00), pp. 67, Palma de Mallorca, SPAIN, DOI: 10.1109/OLT.2000.856614, 3 au 5 juillet 2000
 
109 Rebaudengo M., Sonza Reorda M., Violante M., Cheynet P., Nicolescu B., Velazco R., Evaluating the effectiveness of a software fault-tolerance technique on RISC- and CISC-based architectures, 6th IEEE International On Line Testing Workshop (IOLTW'00), pp. 17-21, Palma de Mallorca, SPAIN, DOI: 10.1109/OLT.2000.856606, 3 au 5 juillet 2000
 
110 Cheynet P., Nicolescu B., Velazco R., Rebaudengo M., Sonza Reorda M., Violante M., Hardening the software with respect to transient errors: a method and experimental results, 1st IEEE Latin-American Test Workshop (LATW'00), Rio de Janeiro, BRAZIL, 13 au 15 mars 2000
 
111 Cota E.F., Carro L., Lubaszewski M., Velazco R., Rezgui S., Synthesis of a 8051-like microcontroller tolerant to transient faults, 1st IEEE Latin-American Test Workshop (LATW'00), Rio de Janeiro, BRAZIL, 13 au 15 mars 2000
 
112 Velazco R., Rezgui S., Transient bitflip injection in microprocessor embedded applications, 6th IEEE International On Line Testing Workshop (LATW'00), pp. 80-84, Rio de Janeiro, BRAZIL, DOI: 10.1109/OLT.2000.856616, 13 au 15 mars 2000
 
113 Velazco R., Cheynet P., Ecoffet R., Effects of radiation on digital architectures: one year results from a satellite experiment, XII Symposium on Integrated Circuits and Systems Design (SBCCI'99), pp. 164-169, Natal, BRAZIL, DOI: 10.1109/SBCCI.1999.803112, 29 septembre au 1 octobre 1999
 
114 Velazco R., Cheynet P., Ecoffet R., Effects of radiation on digital architectures: one year results of a satellite experiment, Brasilian Symposium on Circuit Design (SBCCI'99), pp. 168-174, Natal, BRAZIL, 29 septembre au 1 octobre 1999
 
115 David J.P., Loquet J.G., Cheynet P., Velazco R., Ecoffet R., Duzellier S., Comparison between ground tests and flight data for two static 32 KB memories, The 5th European Conference on Radiation and its effects on components and systems (RADECS'99), Abbaye de Fontevraud, FRANCE, 13 au 17 septembre 1999
 
116 Crain S.H., Velazco R., Alvarez M.T., Bofill A., Yu P., Koga R., Radiation effects in a fixed-point digital signal processor, IEEE Radiation Effects Data Workshop.-Workshop-Record. Held in conjunction with IEEE Nuclear and Space Radiation Effects Conference, pp. 30-34, Norfolk, VA , UNITED STATES, DOI: 10.1109/REDW.1999.816053, 12 au 16 juillet 1999
 
117 Cheynet P., Velazco R., Ecoffet R., Duzellier S., David J.P., Loquet J.G., One year SEU flight results for two 32KB commercial SRAMs on-board a scientific satellite, The 5th IEEE International On-Line Testing Workshop (IOLTW'99), pp. 108-111, Rhodes, GREECE, 5 au 7 juillet 1999
 
118 Velazco R., Godin C., Cheynet P., Torres-Alegre S., Andina D., Gordon M.B., Study of two ANN digital implementations of a radar detector candidate to an on-board satellite experiment, International Work Conference on Artificial and Natural Neural Networks (IWANN'99), pp. 615-624, Alicante, SPAIN, 2 au 4 juin 1999
 
119 Velazco R., Cheynet P., Robustness of digital intelligent control in space: from ground simulations towards on-board satellite experiments, 8th Latin American Congress on Automatic Control (CLCA'98), Viña del Mar, CHILI, 9 au 13 novembre 1998
 
120 Velazco R., Cheynet P., Ecoffet R., Operation in space of artificial neural networks implemented by means of a dedicated architecture based on a transputer, XI Brazilian Symposium on Integrated Circuit Design (SBCCI'98), pp. 162-165, Rio de Janeiro, BRAZIL, DOI: 10.1109/SBCCI.1998.715432, 30 septembre au 1 octobre 1998
 
121 Velazco R., The Alfa-Huerta project, XI Brazilian Symposium on Integrated Circuit Design , pp. 10-12, Rio de Janeiro, BRAZIL, DOI: 10.1109/SBCCI.1998.715401, 30 septembre au 1 octobre 1998
 
122 Alvarez M., Rodriguez S., Bofill A., Velazco R., Cheynet P., Ecoffet R., Space qualification of an architecture based on a digital signal processor for a nanosat project, 6th International Workshop on Digital Signal Processing Techniques For Space (DSP'98), Noordwijk, NETHERLANDS, 23 au 25 septembre 1998
 
123 Marchioro G.F., Moreira P., Noah E., Snoeys W., Calin T., Cosculluela J., Velazco R., Nicolaidis M., Giraldo A., Faccio F., Anelli G., Campbell M., Delmastro M., Jarron P., Kouklinas K., Total dose and Single Event Effects (SEE) in a 0.25 µm CMOS technology, Fourth Workshop on electronics for LHC experiments (LEB'98), Roma, ITALY, 21 au 25 septembre 1998
 
124 Cheynet P., Velazco R., Ecoffet R., Pulsed laser validation of recovery mechanisms of critical SEE's in an artificial neural network system, Fourth European Conference on Radiation and Its Effects on Components and Systems (RADECS'97), pp. 353-359, Cannes, FRANCE, DOI: 10.1109/RADECS.1997.698934, 15 au 19 septembre 1998
 
125 Calin T., Velazco R., Nicolaidis M., Moss S., La Lumondiere S.D., Tran V.T., Koga R., Clark K., Topology-related upset mechanisms in design hardened storage cells, Fourth European Conference on Radiation and its Effects on Components and Systems (RADECS'97), pp. 484-488, Cannes, FRANCE, DOI: 10.1109/RADECS.1997.698979, 5 au 19 septembre 1998
 
126 Buchner S., Velazco R., Beck K., Ecoffet R., Rezgui S., Peters L., Digital fuzzy control: a robust alternative suitable for space application, IEEE Nuclear and Space Radiation Effects Conference (NSREC'98), Newport Beach, UNITED STATES, 20 au 24 juillet 1998
 
127 Asenek V., Underwood C., Velazco R., Rezgui S., Oldfield S., Cheynet P., Ecoffet R., SEU induced errors observed in microprocessor systems, IEEE Nuclear and Space Radiation Effects Conference (NSREC'98), Newport Beach, UNITED STATES, 20 au 24 juillet 1998
 
128 Pouget V., Calin T., Lapuyade H., Lewis D., Fouillat P., Velazco R., Maidon Y., Sarger L., Elaboration of a new pulsed laser system for SEE testing, IEEE International On-Line Testing Workshop (IOLTW'98), Capri, ITALY, 6 au 8 juillet 1998
 
129 Cheynet P., Velazco R., Ecoffet R., Buchner S., Flight results analysis of digital experiment devoted to satellite image processing by means of neural nets, IEEE International On-Line Testing Workshop (IOLTW'98), Capri, ITALY, 6 au 8 juillet 1998
 
130 Velazco R., Cheynet P., Bofill A., Ecoffet R., THESIC: A testbed suitable for the qualification of integrated circuits devoted to operate in harsh environment, IEEE European Test Workshop (ETW'98), Barcelone, SPAIN, 27 au 29 mai 1998
 
131 Velazco R., Cheynet P., Beck K., Peters L., Olmos S., Rubio J.-C., Ecoffet R., Cabestany J., Radiation tolerance of a fuzzy controller, Engineering of Intelligent Systems (EIS'98), Tenerife, SPAIN, 11 au 13 février 1998
 
132 Cheynet P., Perrenot F., Velazco R., El Chakik F., Gordon M.B., Muller J.D., Ecoffet R., Cabestany J., Classical vs. neural approaches for on-board image satellite analysis: Preliminary Experimentes, 2nd round table on Micro-Nano Tehnologies for Space (ESTEC'97), pp. 279-286, Noordwijk, NETHERLANDS, 15 au 17 octobre 1997
 
133 Cheynet P., Muller J.D., Velazco R., Analysis and improvement of neural network robustness for on-board satellite image processing, International Conference on Artificial Neural Networks (ICANN'97), pp. 1211-1216, Lausanne, SWITZERLAND, 8 au 10 octobre 1997
 
134 Cheynet P., Rubio J.-C., Velazco R., Muller J.D., Evaluating neural network robustness with an architecture built around L-Neuro 2.3, 6th International Conference on Microelectronics for Neural Networks, Evolutionary & Fuzzy Systems (ICANN'97), Dresden, GERMANY, 24 au 26 septembre 1997
 
135 Buchner S., Olmos S., Cheynet P., Velazco R., Mcmorrow D., Mellinger J., Ecoffet R., Muller J.D., Pulsed laser validation of recovery mechanisms of critical SEE's in an artificial neural network system, Fourth European Conference on Radiation and their Effects on Devices and Systems (RADECS'97), pp. 353 - 359 , Cannes, FRANCE, DOI: 10.1109/RADECS.1997.698934, 15 au 19 septembre 1997
 
136 Assoum A., Velazco R., Ziade H., Single event upsets simulations on neural networks, 2nd LAAS International Conference on Computer Simulation, Beyrouth, LEBANON, 1 au 4 septembre 1997
 
137 Velazco R., Cheynet P., Muller J.D., Ecoffet R., Buchner S., Artificial neural network robustness for on-board satellite image processing : results of SEU simulations and ground tests, IEEE Nuclear and Space Radiation Effects Conference (NSREC'97), Snowmass, UNITED STATES, 21 au 25 juillet 1997
 
138 Vargas F., Velazco R., Terroso A.R., Nicolaidis M., Performance improvement of fault-tolerant systems through chip-level current monitoring, 3rd IEEE International On-Line Testing Workshop (IOLTW'97), Aghia Pelaghia Headland, Crete, GREECE, 7 au 9 juillet 1997
 
139 Velazco R., Cheynet P., Assoum A., Bezerra F., Experiments on fault tolerance of artificial neural networks implemented by means of a transputer, 2nd International FLINS Workshop Intelligent Systems and Soft Computing for Nuclear Science and Industry, pp. 174-180, Mol, BELGIUM, 25 au 27 septembre 1996
 
140 Calin T., Velazco R., Nicolaidis M., SEU-Hardened Storage Cell Validation using a Pulsed Laser, 33rd International Nuclear and Space Radiation Effects Conference (NSREC'96), Indian Wells, CA, UNITED STATES, 15 au 19 juillet 1996
 
141 Calin T., Nicolaidis M., Velazco R., Upset Hardened Memory Design for Submicron CMOS Technology, 33rd International Nuclear and Space Radiation Effects Conference (NSREC'96), Indian Wells, CA, UNITED STATES, 15 au 19 juillet 1996
 
142 Calin T., Nicolaidis M., Velazco R., Design of Radiation Hardened Memories, IEEE International On-Line Testing Workshop (IOLT'96), Biarritz, FRANCE, 1 juillet 1996
 
143 Assoum A., Radi M.E., Velazco R., Elie F., Ecoffet R., Robustness against S.E.U. of an artificial neural network space application, Third European Conference on Radiation and its Effects on Components and Systems (RADECS'95), pp. 443-448, Arcachon , FRANCE, DOI: 10.1109/RADECS.1995.509817, 18 au 22 septembre 1995
 
144 Bezerra F., Velazco R., Assoum A., Benezech D., SEU and latch-up results on transputers, Third European Conference on Radiation and its Effects on Components and Systems (RADECS'95), pp. 340-345, Arcachon, FRANCE, DOI: 10.1109/RADECS.1995.509800, 18 au 22 septembre 1995
 
145 Bezerra F., Hardy D., Velazco R., Ziade H., TILMICRO, a new SEU and latch-up tester for microprocessors: initial results on 32-bit floating point DSPs, Third European Conference on Radiation and its Effects on Components and Systems (RADECS'95), pp. 296-301, Arcachon, FRANCE, DOI: 10.1109/RADECS.1995.509793, 18 au 22 septembre 1995
 
146 Calin T., Vargas F., Nicolaidis M., Velazco R., A Low-Cost Highly Reliable SEU-Tolerant SRAM: Prototype and Test Experiments, 32nd International Nuclear and Space Radiation Effects Conference (NSREC'95), Madison, Wisconsin, UNITED STATES, 17 au 21 juillet 1995
 
147 Bessot D., Velazco R., Design of SEU-hardened CMOS memory cells: the HIT cell, European Conference on Radiation and its Effects on Components and Systems (RADECS'93), pp. 563-570, Saint-Malo, FRANCE, DOI: 10.1109/RADECS.1993.316519, 13 au 16 septembre 1993
 
148 Estreme F., Chapuis T., Velazco R., Karoui S., Trigaux R., Benezech D., Rosier L.H., SEU and latch-up results for SPARC processors, IEEE Radiation Effects Data Workshop (REDW'1993), pp. 13-19, Snowbird, Utah, UNITED STATES, DOI: 10.1109/REDW.1993.700562, 19 au 23 juillet 1993
 
149 Velazco R., Martinet B., Auvert G., Laser injection of spot defects on integrated circuits, First Asian Test Symposium (ATS'92), pp. 158-163, Hiroshima, JAPAN, DOI: 10.1109/ATS.1992.224415, 26 au 27 novembre 1992
 
150 Aktouf C., Mazare G., Robach C., Velazco R., A practical approach for the diagnosis of a MIMD network, First Asian Test Symposium (ATS'92), pp. 182-186, 10.1109/ATS.1992.224411, JAPAN, DOI: 10.1109/ATS.1992.224411, 1 janvier 1992
 
151 Velazco R., Karoui S., Chapuis T., SEU testing of 32-bit microprocessors [for space application], IEEE Radiation Effects Data Workshop (REDW'92), pp. 16-20, New Orleans, LA, UNITED STATES, DOI: 10.1109/REDW.1992.247330 10.1109/REDW.1992.247330, 1 janvier 1992
 
152 Velazco R., Martinet B., Physical fault injection: a suitable method for the evaluation of functional test efficiency, International Workshop on Defect and Fault Tolerance on VLSI Systems (DFTVS'91), pp. 179-182, Hidden Valley, Pennsylvania, UNITED STATES, DOI: 10.1109/DFTVS.1991.199960, 18 au 20 novembre 1991
 
153 Velazco R., Bellon C., Martinet B., Failure coverage of functional test methods: a comparative experimental evaluation, International Test Conference (ITC'90), pp. 1012-1017, Washington, DC , UNITED STATES, DOI: 10.1109/TEST.1990.114124, 10 au 14 septembre 1990
 
154 Bellon C., Velazco R., Ziade H., Analysis of experimental results on functional testing and diagnosis of complex circuits, International Test Conference (ITC'88), pp. 64-72, Washington, DC, UNITED STATES, DOI: 10.1109/TEST.1988.207781, 10 au 14 septembre 1988
 
155 Velazco R., Test and diagnosis problems in VLSI; experiences on microprocessor test and diagnosis, Microcomputer '86 - Design, Practice, Education, pp. 195-205, Wroclaw, POLAND, 1 janvier 1986
 
156 Velazco R., Ziade H., Kolokithas E., A microprocessor test approach allowing fault localisation, International Test Conference (ITC'85), pp. 737-743, Philadelphia, PA, UNITED STATES, 1 janvier 1985
 
157 Bellon C., Velazco R., Liothin A., Sadier S., Saucier G., Grillot F., Automatic generation of microprocessor test programs, Design Automation Conference Proceedings (DAC'84), pp. 566-73, Albuquerque, New Mexico, UNITED STATES, 25 au 27 juin 1984
 
158 Bellon C., Velazco R., Taking into account asynchronous signals in functional test of complex circuits, 21st Design Automation Conference (DAC'84), pp. 490-496, Albuquerque, New Mexico, UNITED STATES, 25 au 27 juin 1984
 
159 Bellon C., Velazco R., A behavioural test method for microprocessors and complex circuits, European Conference on Electronic Design Automation EDA 84., pp. 79-82, London, ENGLAND, 26 au 30 mars 1984
 
160 Bellon C., Velazco R., Hardware and software tools for microprocessor functional test, International Test Conference (ITC'84), pp. 804-810, Philadelphia, PA, UNITED STATES, 1 janvier 1984
 
161 Robach C., Saucier G., Velazco R., Flexible test method for microprocessors, Microprocessor systems : software, firmware, and hardware : Sixth EUROMICRO Symposium on Microprocessing and Microprogramming, pp. 329-339, London , ENGLAND, 16 au 18 septembre 1980
 
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6 Chapitres de livre

1 Ramos P., Vargas V., Velazco R., Zergainoh N.-E., Error Rate Prediction of Applications Implemented in Multi-Core and Many-Core Processors, Radiation Effects on Integrated Circuits and Systems for Space Applications, Velazco R., McMorrow D., Estela J. (Eds.) , Ed. Springer , pp. 145-173, Vol. 2, 2019
 
2 Vargas V., Ramos P., Méhaut J-F., Velazco R., Improving Reliability of Multi-/Many-Core Processors by Using NMR-MPar Approach, Radiation Effects on Integrated Circuits and Systems for Space Applications, Velazco R., McMorrow D., Estela J. (Eds.) , Ed. Springer , pp. 175-203, DOI: 10.1007/978-3-030-04660-6_8, 2019
 
3 Souari A., Thibeault Cl., Blaquière Y., Velazco R., Towards an efficient SEU effects emulation on SRAM-based FPGAs, Microelectronics Reliability, Professor N. D. S TOJADINOVIC (Eds.) , Ed. Elsevier, pp. 173-182, Vol. 66, 2016
 
4 Velazco R., Foucard G., Peronnard P., Integrated circuit qualification for Space and Ground-level Applications: Accelerated test and Error-Rate Prediction, Soft Errors in modern electronic systems, M. Nicolaidis (Eds.) , Ed. Springer , pp. 167-202, DOI: DOI: 10.1007/978-1-4419-6993-4_7 , 2011
 
5 Velazco R., Faure F., Error rate prediction for digital architectures: test methodology and tools, Radiation effects on embedded systems, VELAZCO R., FOUILLAT P., REIS R (Eds.) , Ed. Springer , pp. 233-258, DOI: DOI 10.1007/978-1-4020-5646-8_11, 2007
 
6 Nicolescu B., Velazco R., Detecting soft errors by a purely software approach: method, tools and experimental results, Embedded Software for SoC, Ed. Kluwer Academic Publishers, pp. Chapter 4, 39-50, 2003
 
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3 Livres & Éditions Ouvrages

1 Velazco R., Mcmorrow D., Estela J. (Eds.) Radiation Effects on Integrated Circuits and Systems for Space Applications, pp. 401 pages, Ed. Springer , 2019
 
2 Velazco R., Fouillat P., Reis R. (Eds.) Radiation effects on embedded systems, pp. 269 p., Ed. Springer , 2007
 
3 Aitken R., Velazco R., Salsano A., Sun X. (Eds.) 19th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT’04), Cannes, France, October 11-13, Ed. IEEE, 2004
 
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3 Revues nationales

1 Velazco R., Des cerveaux artificiels dans l'espace, Revue de l'Electricité et de l'Electronique, Ed. Société de l'électricité, de l'électronique et des technologies de l'information et de la communication, Vol. , No. 2, février 1998
 
2 Bellon C., Kolokithas E., Velazco R., The GAPT system: a test chain for microprocessors, L'Onde Electrique, Ed. Société française des électroniciens et des radioélectriciens, Vol. 65, No. 6, pp. 99-109, novembre 1985
 
3 Robach C., Saucier G., Velazco R., The functional test parameter of a microprocessor, Technique et Science Informatiques, Vol. 14, No. 3, pp. 293-308, mars 1980
 
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10 Autres communications

 1 Ramos P., Vargas V., Baylac M., Zergainoh N.-E., Velazco R., Error-rate prediction of applications implemented in Multi-core and Many-core processors, Radiation Effects on Components Systems (RADECS'2017), Geneva, SWITZERLAND, 2017
 
 2 Coelho A., Solinas M., Fraire J., Zergainoh N.-E., Ferreyra P., Velazco R., NETFI-2: An Automatic Method for Fault Injection on HDL-Based Designs, Design, Automation & Test in Europe (DATE 2017), Lausanne, SWITZERLAND, DOI: https://www.date-conference.com/system/files/file/date17/ubooth/119922.pdf, 2017
 
 3 Velazco R., Efectos de radiaciones en circuitos integrados digitales: orígenes, técnicas de mitigación y test experimentales, Reunión de trabajo en Procesamiento de la Información y Control (RPIC'15), Córdoba, ARGENTINA, 2015
 
 4 Velazco R., Estudio de la robustez frente a SEUs de algoritmos auto-convergentes, Conferencias de Investigación para Posgrado, Facultad de Informatics, Universidad Complutense, Madrid, SPAIN, 2015
 
 5 Velazco R., Robustness of intelligent control with respect to radiation induced faults. Estudio de la robustez del "control inteligente" frente a fallos inducidos por las radiaciones, Seminaire in the frame of “Post-graduate Research Conferences”, Conferencias de Investigación para Posgrado, Facultad de Informatics, Universidad Complutense, Madrid, SPAIN, 2015
 
 6 Velazco R., Inyección de fallos para el análisis de la sensibilidad a los errores transitorios, "soft errors", provocados por las radiaciones en circuitos integrados, Conferencias de Investigación para Posgrado, Facultad de Informatics, Universidad Complutense, Madrid, SPAIN, 2014
 
 7 Velazco R., . Radiation Effects on integrated circuits: origines, test methodologies and real life experiments, XV Reunión de Trabajo en Procesamiento de la Información y Control, San Carlos de Bariloche, ARGENTINA, 2013
 
 8 Velazco R., Single Event Effects on Digital Integrated Circuits: Origins and Mitigation Techniques, Workshop Education Society and Computational Iintelligence Society (WESCIS’13), Tucuman, ARGENTINA, 2013
 
 9 Federico C.A., Velazco R., Pancher F., Silva Cardenas C., Pineda F., Hubert G., Palumbo F., Goncalez O.L., Mansour W., Duzellier S., Caldas L.V., Medições de nêutrons oriundos de radiação cósmica em Puno (Peru), XXII WAI (IEAv anual Workshop), pp. 111, Sao José dos Campos, BRAZIL, 2012
 
10 Ziade H., Ayoubi R., Velazco R., A survey on fault injection techniques, International Arab Journal of Information Technology (IAJIT), Vol. 1, No. 2, pp. 171-186, 2004
 
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11 Rapports

 1 Anghel L., Velazco R., Saleh S., A methodology for test replacement solutions of obsolete processors, ISRN: TIMA-RR--03/08-05--FR, 1 janvier 2003
 
 2 Anghel L., Saleh S., Velazco R., Preliminary validation of an approach dealing with processor obsolescence, ISRN: TIMA-RR--03/08-03--FR, 1 janvier 2003
 
 3 Rebaudengo M., Violante M., Velazco R., Sonza Reorda M., Nicolescu B., Coping with SEUs/SETs in Microprocessors by Means of Low-cost Solutions: a Comparative Study and Experimental Results, ISRN: TIMA--RR-02/04/02--FR, 1 janvier 2002
 
 4 Nicolescu B., Rebaudengo M., Violante M., Cheynet P., Velazco R., Sonza Reorda M., Experimentally Evaluating an Automatic Approach for Generating Safety-Critical Software with Respect to Transient Errors, ISRN: TIMA--RR-02/02/5--FR, 1 janvier 2002
 
 5 Rezgui S., Velazco R., Ecoffet R., Predicting Error Rate for Microprocessor-Based Digital Architectures throughC.E.U. (Code Emulating Upsets) Injection, ISRN: TIMA--RR-02/02/6--FR, 1 janvier 2002
 
 6 Velazco R., Faure F., A flexible platform for the functional validation of programmable circuits, ISRN: TIMA-RR--01/10-5--FR, 1 janvier 2001
 
 7 Velazco R., Nicolescu B., Dupont E., Faure F., Ecoffet R., Olmos S., A flight experiment for the evaluation of hardware and software fault tolerance techniques, ISRN: TIMA--RR-01/10-8--FR, 1 janvier 2001
 
 8 Nicolescu B., Velazco R., Suescun R., Effectiveness and limitations of various software techniques for “soft error” detection:, ISRN: TIMA-RR--/10-7--FR, 1 janvier 2001
 
 9 Velazco R., Leveugle R., Calvo O., Upset-like Fault Injection in VHDL Descriptions:, ISRN: TIMA-RR--01/10-6--FR, 1 janvier 2001
 
10 Rezgui S., Cota E.F., Carro L., Lubaszewski M., Reis R., Velazco R., Lima F., Designing a Radiation Hardened 8051-like Micro-controller, ISRN: TIMA-RR--00/06-2--FR, 1 janvier 2000
 
11 Rezgui S., Cheynet P., Velazco R., Coderch N., Cueto J., Un système de test pour la qualification de circuits intégrés destinés à fonctionner en environnement sévère, ISRN: TIMA-RR--99/04-6--FR, 1 janvier 1999
 
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