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342 résultats

   40 Revues internationales
    2 Brevets
   31 Conférences invitées
  158 Conférences internationales
   11 Chapitres de livre
   11 Livres & Éditions Ouvrages
    2 Revues nationales
   36 Conférences nationales
   13 Autres communications
   37 Rapports
    1 Thèses

40 Revues internationales

 1 Cilici F., Barragan M., Lauga-Larroze E., Bourdel S., Leger G., Vincent L., Mir S., A Nonintrusive Machine Learning-Based Test Methodology for Millimeter-Wave Integrated Circuits, IEEE Transactions on Microwave Theory and Techniques, Ed. IEEE, Vol. , pp. 1-1, DOI: 10.1109/TMTT.2020.2991412, mai 2020
 
 2 Bounceur A., Mir S., Euler R., Beznia K., Estimation of Analog/RF Parametric Test Metrics Based on a Multivariate Extreme Value Model (Early Access), IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Ed. IEEE, Vol. , pp. 966-976, DOI: 10.1109/TCAD.2019.2907923, mars 2019
 
 3 Silveira Feitoza R., Barragan M., Dzahini D., Mir S., Reduced-code static linearity test of split-capacitor SAR ADCs using an embedded incremental Sigma-Delta converter, IEEE Transactions on Device and Materials Reliability, Vol. 19, No. 1, pp. 37-45, DOI: 10.1109/TDMR.2019.2891298, mars 2019
 
 4 Renaud G., Diallo M., Barragan M., Mir S., Fully-differential 4 V-output range 14.5-ENOB step-wise ramp stimulus generator for on-chip static linearity test of ADCs, IEEE Transactions on Very Large Scale Integration (VLSI) Systems , Ed. IEEE, Vol. 27, No. 2, pp. 281-293, DOI: 10.1109/TVLSI.2018.2876976, février 2019
 
 5 Malloug H., Barragan M., Mir S., Practical Harmonic Cancellation Techniques for the On-Chip Implementation of Sinusoidal Signal Generators for Mixed-Signal BIST Applications, Journal of Electronic Testing: Theory and Applications, Ed. Springer , Vol. 34, No. 3, pp. 263-279, DOI: 10.1007/s10836-018-5720-2, juin 2018
 
 6 Barragan M., Stratigopoulos H., Mir S., Le Gall H., Bhargava N., Bal A., Practical Simulation Flow for Evaluating Analog and Mixed-Signal Test Techniques, IEEE Design & Test, Ed. IEEE, Vol. 33, No. 6, pp. 46-54, DOI: 10.1109/MDAT.2016.2590985, décembre 2016
 
 7 Barragan M., Alhakim R., Stratigopoulos H., Dubois M., Mir S., Le Gall H., Bhargava N., Bal A., A Fully-Digital BIST Wrapper Based on Ternary Test Stimuli for the Dynamic Test of a 40 nm CMOS 18-bit Stereo Audio Sigma-Delta ADC, IEEE Transactions on Circuits and Systems, Ed. IEEE, Vol. 63, No. 11, pp. 1876-1888, DOI: 10.1109/TCSI.2016.2602387, novembre 2016
 
 8 Renaud G., Barragan M., Laraba A., Stratigopoulos H., Mir S., Le Gall H., Naudet H., A 65nm CMOS Ramp Generator Design and its Application Towards a BIST Implementation of the Reduced-Code Static Linearity Test Technique for Pipeline ADCs, Journal of Electronic Testing: Theory and Applications, Ed. Springer , Vol. 32, No. 4, pp. 407-421, DOI: 10.1007/s10836-016-5599-8, avril 2016
 
 9 Laraba A., Stratigopoulos H., Mir S., Naudet H., Exploiting pipeline ADC properties for a reduced-code linearity test technique, IEEE Transactions on Circuits and Systems, Ed. IEEE, Vol. 62, No. 10, pp. 2391-2400, DOI: 10.1109/TCSI.2015.2469014, octobre 2015
 
10 Dimakos A., Stratigopoulos H., Siligaris A., Mir S., De Foucauld E., Parametric Built-In Test for 65nm RF LNA Using Non-Intrusive Variation-Aware Sensors, Journal of Electronic Testing: Theory and Applications, Ed. Springer , Vol. 31, No. 4, pp. 381-394, DOI: 10.1007/s10836-015-5534-4, août 2015
 
11 Beznia K., Bounceur A., Euler R., Mir S., A tool for analog/RF BIST evaluation using statistical models of circuit parameters, Transactions on Design Automation of Electronic Systems (TODAES), Ed. ACM, NY, USA, Vol. 20 , No. 2, DOI: 10.1145/2699837, février 2015
 
12 Laraba A., Stratigopoulos H., Mir S., Naudet H., Bret G., Reduced code linearity testing of pipeline ADCs, IEEE Design and Test of Computers, Ed. IEEE, Vol. 30, No. 6, pp. 80-88, DOI: 10.1109/MDAT.2013.2267957, décembre 2013
 
13 Huang K., Stratigopoulos H., Mir S., Hora C., Xing Y., Kruseman B., Diagnosis of Local Spot Defects in Analog Circuits , IEEE Transactions on Instrumentation and Measurement, Ed. IEEE, Vol. 61, No. 10, pp. 2701 - 2712 , DOI: 10.1109/TIM.2012.2196390, octobre 2012
 
14 Stratigopoulos H., Mir S., Adaptive Alternate Analog Test, IEEE Design and Test of Computers, Ed. IEEE, Vol. 29, No. 4, pp. 71-79, DOI: 10.1109/MDT.2012.2205480, juillet-août 2012
 
15 Abdallah L., Stratigopoulos H., Mir S., Kelma C., RF Front-End Test Using Built-in Sensors , IEEE Design and Test of Computers, Ed. IEEE, Vol. 28, No. 6, pp. 76-84, DOI: 10.1109/MDT.2011.131 , novembre-décembre 2011
 
16 Bounceur A., Mir S., Stratigopoulos H., Estimation of Analog Parametric Test Metrics Using Copulas, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Ed. IEEE, Vol. 30, No. 9, pp. 1400-1410, DOI: 10.1109/TCAD.2011.2149522 , septembre 2011
 
17 Cenni F., Cazalbou J., Mir S., Rufer L., Design of a SAW-based chemical sensor with its microelectronics front-end interface , Microelectronics journal, Ed. Elsevier, Vol. 41, No. 11, pp. 723-732, DOI: 10.1016/j.mejo.2010.06.008 , novembre 2010
 
18 Tounsi F., Mezghani B., Rufer L., Masmoudi M., Mir S., Electromagnetic Investigation of a CMOS MEMS Inductive Microphone, Sensors & Transducers Journal (ISSN 1726- 5479), Ed. IFSA, International Frequency Sensor Association, Vol. 108, No. 9, pp. 40-53, septembre 2009
 
19 Dhayni A., Mir S., Rufer L., Bounceur A., Simeu E., Pseudorandom BIST for test and characterization of linear and nonlinear MEMS, Microelectronics journal, Ed. Elsevier, Vol. 40, No. 7, pp. 1054-1061, DOI: 10.1016/j.mejo.2008.05.012, juillet 2009
 
20 Stratigopoulos H., Mir S., Bounceur A., Evaluation of analog/RF test measurements at the design stage, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Ed. IEEE, Vol. 28, No. 4, pp. 582-590, DOI: 10.1109/TCAD.2009.2016136, avril 2009
 
21 Lalinsky T., Rufer L., Vanko G., Mir S., Hascik S., Mozolova Z., Vincze A., Uherek F., AlGaN/GaN heterostructure based surface acoustic wave structures for chemical sensors, Applied Surface Science, Ed. Elsevier, Vol. 255, No. 3, pp. 712-714, DOI: 10.1016/j.apsusc.2008.07.016 , novembre 2008
 
22 Simeu E., Nguyen H.N., Cauvet P., Mir S., Rufer L., Khereddine R., Using signal envelope detection for online and offline RF MEMS switch testing, Journal of VLSI Design, Ed. Hindawi Publishing Corporation, Vol. 2008, No. Article ID 294014, pp. 1-10, DOI: 10.1155/2008/294014, janvier 2008
 
23 Bounceur A., Mir S., Simeu E., Rolindez L., Estimation of test metrics for the optimisation of analogue circuit testing, Journal of Electronic Testing: Theory and Applications, Ed. Springer , Vol. 23, No. 6, pp. 471-484, DOI: 10.1007/s10836-007-5006-6, juin 2007
 
24 Rolindez L., Mir S., Bounceur A., Carbonero J.L., A BIST scheme for SNDR testing of sigma delta ADCs using sine-wave fitting, Journal of Electronic Testing: Theory and Applications, Ed. Springer , Vol. 22, No. 4-6, pp. 325-335, DOI: 10.1007/s10836-006-9500-z, décembre 2006
 
25 Rufer L., Domingues C., Mir S., Petrini V., Jeannot J.C., Delobelle P., A CMOS compatible ultrasonic transducer fabricated with deep reactive ion etching, Journal of Microelectromechanical Systems, Ed. IEEE, Vol. 15, No. 6, pp. 1766-1776, DOI: 10.1109/JMEMS.2006.886390, décembre 2006
 
26 Mir S., Rufer L., Dhayni A., Built-in-self-test techniques for MEMS, Microelectronics journal, Ed. Elsevier, Vol. 37, No. 12, pp. 1591-1597 , DOI: 10.1016/j.mejo.2006.04.016, décembre 2006
 
27 Prenat G., Mir S., Rolindez L., Vazquez D., A low-cost digital frequency testing approach for mixed-signal devices using Sigma Delta modulation, Microelectronics journal, Ed. Elsevier, Vol. 36, No. 12, pp. 1080-1090, DOI: 10.1016/j.mejo.2005.04.062, décembre 2005
 
28 Rufer L., Mir S., Simeu E., Domingues C., On-chip pseudorandom MEMS testing, Journal of Electronic Testing: Theory and Applications, Ed. Springer , Vol. 21, No. 3, pp. 233-241, DOI: 10.1007/s10836-005-6353-9, juin 2005
 
29 Roman C., Mir S., Charlot B., Building an analogue fault simulation tool and its application to MEMS, Microelectronics journal, Ed. Elsevier, Vol. 34, No. 10, pp. 897-906, DOI: 10.1016/S0026-2692(03)00162-9, octobre 2003
 
30 Benedek Zs., Courtois B., Farkas G., Kollar E., Mir S., Poppe A., Rencz M., Szekely V., Torki K., A scalable multi-functional thermal test chip family: design and evaluation, Journal of Electronic Packaging, Ed. ASME, Vol. 123, No. 4, pp. 323-330, DOI: 10.1115/1.1389846, décembre 2001
 
31 Charlot B., Mir S., Parrain F., Courtois B., Generation of electrically induced stimuli for MEMS self-test, Journal of Electronic Testing: Theory and Applications, Ed. Springer , Vol. 17, No. 6, pp. 459-470, DOI: 10.1023/A:1012860420235, décembre 2001
 
32 Mir S., Parrain F., Charlot B., Veychard D., Microbeams with electronically controlled high thermal impedance, Analog Integrated Circuits and Signal Processing, Ed. Kluwer Academic Publishers, Vol. 29, No. 1-2, pp. 71-83, DOI: 10.1023/A:1011282314105, octobre-novembre 2001
 
33 Charlot B., Mir S., Courtois B., Fault simulation of MEMS using HDLs, Journal of Modeling and Simulation of Microsystems, Ed. Computational Publications, Cambridge, MA, USA, Vol. 2, No. 1, pp. 35-42, janvier 2001
 
34 Mir S., Charlot B., Courtois B., Extending Fault-Based Testing to Microelectromechanical Systems, Journal of Electronic Testing: Theory and Applications, Ed. Springer , Vol. 16, No. 3, pp. 279-288, DOI: 10.1023/A:1008303717862, juin 2000
 
35 Lubaszewski M., Mir S., Kolarik V., Nielsen C., Courtois B., Design of self-checking fully differential circuits and boards, Transactions on Very Large Scale Integration (VLSI) Systems, Ed. IEEE, Vol. 8, No. 2, pp. 113-128, DOI: 10.1109/92.831432, avril 2000
 
36 Mir S., Charlot B., On the integration of design and test for chips embedding MEMS, IEEE Design and Test of Computers, Ed. IEEE, Vol. 16, No. 4, pp. 28-38, DOI: 10.1109/54.808204, octobre-décembre 1999
 
37 Mir S., Lubaszewski M., Kolarik V., Courtois B., Fault-based testing and diagnosis of balanced filters, Analog Integrated Circuits and Signal Processing, Ed. Kluwer Academic Publishers, Vol. 11, No. 1, pp. 5-19, DOI: 10.1007/BF00174235, septembre 1996
 
38 Mir S., Lubaszewski M., Courtois B., Fault-based ATPG for linear-analog circuits with minimal size multifrequency test sets, Journal of Electronic Testing: Theory and Applications, Ed. Springer , Vol. 9, No. 1-2, pp. 43-57, août-octobre 1996
 
39 Mir S., Lubaszewski M., Courtois B., Unified built-in self-test for fully differential analog circuits, Journal of Electronic Testing: Theory and Applications, Ed. Springer , Vol. 9, No. 1-2, pp. 135-151, août-octobre 1996
 
40 Kolarik V., Mir S., Lubaszewski M., Courtois B., Analog checkers with absolute and relative tolerances, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Ed. IEEE, Vol. 14, No. 5, pp. 607-612, DOI: 10.1109/43.384424, mai 1995
 
remonter

2 Brevets

1 Fei R., Mir S., Moreau J., Circuit and method for on-chip testing of a pixel array, No. 14/60121, 21 octobre 2014
 
2 Dubois M., Mir S., Stratigopoulos H., Sigma-Delta ADC with test circuit, No. 10/02741 , 1 juin 2010
 
remonter

31 Conférences invitées

 1 Cilici F., Leger G., Barragan M., Mir S., Lauga-Larroze E., Bourdel S., Efficient generation of data sets for one-shot statistical calibration of RF/mm-wave circuits, Hot topic session, International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD 2019), pp. 17-20, Lausanne, SWITZERLAND, 15 au 18 juillet 2019
 
 2 Mir S., Barragan M., Mammasse M., BIST Solutions for Industrial Mixed-signal Circuits, Invited talk (Special Session), 25th International On-Line Testing Symposium (IOLTS 2019), Rhodes, GREECE, 1 au 3 juillet 2019
 
 3 Mir S., Analog, mixed-signal and MEMS design-for-test and its use for intelligent sensors, Invited talk (Special Session), 36th IEEE VLSI Test Symposium (VTS'2018), San Francisco, UNITED STATES, DOI: 10.1109/VTS.2018.8368648, 22 au 25 avril 2018
 
 4 Pastorelli C., Mellot P., Tubert C., Mir S., Design of a Piece-Wise-Linear Ramp ADC for CMOS imagers, Invited talk (Special Session), 22nd IEEE International Mixed-Signal Test Workshop (IMSTW 2017), Thessaloniki, GREECE, 3 au 5 juillet 2017
 
 5 Mir S., Fei R., Moreau J., Droniou T., BIST of power and control lines in CMOS imagers, Invited talk (Special Session), 21st IEEE International Mixed-Signal Testing Workshop (IMSTW'16), Sant Feliu de Guixols, SPAIN, 4 au 6 juillet 2016
 
 6 Dimakos A., Andraud M., Abdallah L., Stratigopoulos H., Simeu E., Mir S., Test and calibration of RF circuits using built-in non-intrusive sensors, Invited talk (Special Session), IEEE International Computer Society Annual Symposium on VLSI (ISVLSI'15), pp. 627, Montpellier, FRANCE, DOI: 10.1109/ISVLSI.2015.42, 8 au 10 juillet 2015
 
 7 Mir S., Analog, mixed-signal and MEMS design-for-test and its use for WSN, Invited Tutorial, Winter School on Wireless Sensor Networks (WSWSN), Algiers, ALGERIA, 14 au 15 décembre 2014
 
 8 Altet J., Aldrete-Vidrio E., Reverter F., Gomez D., Gonzalez J.L., Onabajo M., Silva-Martinez J., Martineau B., Perpinà X., Abdallah L., Stratigopoulos H., Aragonès X., Jordà X., Vellvehi M., Dilhaire S., Mir S., Mateo D., Review of temperature sensors as monitors for RF mmW built-in testing and self-calibration schemes, Invited Talk, 57th IEEE Midwest Symposium on Circuits and Systems (MWSCAS'14), pp. 1081-1084, Texas, UNITED STATES, DOI: 10.1109/MWSCAS.2014.6908606, 3 au 6 août 2014
 
 9 Mir S., Analog/RF test techniques, Invited Tutorial, 14th European Test Symposium, Test Spring School, Paderborn, GERMANY, 26 au 30 mai 2014
 
10 Dubois M., Stratigopoulos H., Barragan M., Alhakim R., Mir S., Analog/RF test problem solving with statistically sampled data, Invited talk (Elevator talk), IEEE VLSI Test Symposium (VTS'14), Napa, California, UNITED STATES, 14 au 16 mai 2014
 
11 Mir S., Statistical learning for test and control of analog/RF circuits, Keynote talk, 4th European Workshop on CMOS Variability (VARI'13), Karlsruhe, GERMANY, 9 au 11 septembre 2013
 
12 Abdallah L., Stratigopoulos H., Mir S., Implicit Test of High-Speed Analog Circuits Using Non-Intrusive Sensors, Invited talk (Special Session), IEEE European Conference on Circuit Theory and Design (ECCTD’11), Linköping, SWEDEN, 29 au 31 août 2011
 
13 Stratigopoulos H., Mir S., Adaptive Alternate Analog Test, Invited talk (Special Session), IEEE Latin-American Test Workshop (LATW’11), Porto de Galinhas, BRAZIL, 27 au 30 mars 2011
 
14 Mir S., Stratigopoulos H., Dubois M., Bounceur A., Evaluation of parametric test metrics for mixed-signal/RF DFT solutions using statistical techniques, Invited Talk, Catrene European Nanoelectronics Design Technology Conference, Grenoble, FRANCE, 23 au 24 juin 2010
 
15 Mir S., Stratigopoulos H., Bounceur A., Density estimation for analog/RF test problem solving, Invited Talk, 28th IEEE VLSI Test Symposium, pp. 41, Santa Cruz, UNITED STATES, DOI: 10.1109/VTS.2010.5469620 , 19 au 22 avril 2010
 
16 Mir S., Evaluation of mixed-signal/RF DFT solutions for SiP devices using statistical techniques, Invited Talk, Workshop on Reliability & DfX engineering for System-in-Package Technologies (SiPeX'08), Pallanza, ITALY, 29 mai 2008
 
17 Mir S., Rufer L., Simeu E., Nguyen H.N., Khereddine R., DFT for MEMS, Invited Talk, RF-MEMS Workshop on Industry Applications: RF power MEMS: reliability and applications, Barcelona, SPAIN, 28 juin 2007
 
18 Mir S., Test intégré des circuits mixtes, Invited Talk, Journées de la section électronique du Club EEA, SiP et SoC : nouvelles perspectives, nouveaux défis, Montpellier, FRANCE, 27 mars 2007
 
19 Simeu E., Mir S., Rufer L., Concurrent testing embedded systems: adapting automatic control techniques to microelectronics testing , Invited Talk, 16th IFAC World Congress, pp. Paper Tu-A15-TO, Prague, CZECH REPUBLIC, 4 au 8 juillet 2005
 
20 Simeu E., Mir S., Rufer L., Online testing embedded systems: adapting automatic control techniques to microelectronics testing, Invited Talk, 16th IFAC World Congress, pp. 1180-1180, Prague, CZECH REPUBLIC, DOI: 10.3182/20050703-6-CZ-1902.01181, 1 juillet 2005
 
21 Mir S., Rufer L., Dhayni A., Built-In Self-Test techniques for MEMS, Invited Talk, 1st International Workshop on Advances in Sensors and Interfaces (IWASI'05), pp. 34-38, Bari, ITALY, 19 au 20 avril 2005
 
22 Mir S., Rufer L., Charlot B., Courtois B., On-chip testing of embedded silicon transducers, Plenary talk, The 16th International Conference on Microelectronics (ICM'04), pp. 1-7, Iowa, UNITED STATES, DOI: 10.1109/ICM.2004.1434190, 6 au 8 décembre 2004
 
23 Mir S., Charlot B., Rufer L., Courtois B., On-chip testing of embedded silicon transducers, Invited Talk, IEEE International SOC Conference (SOCC'04), pp. 13-18, Santa Clara, CA, UNITED STATES, DOI: 10.1109/SOCC.2004.1362334, 12 au 15 septembre 2004
 
24 Mir S., Prenat G., Rolindez L., Simeu E., Rufer L., On-chip analogue testing based on ΣΔ modulation, Invited Talk, Workshop on the testing of high resolution mixed signal interfaces, Ajaccio, Corse, FRANCE, 1 mai 2004
 
25 Mir S., Rufer L., Courtois B., On-chip testing of embedded transducers, Invited Talk, 17th International Conference on VLSI Design, pp. 463-472, Mumbai, INDIA, DOI: 10.1109/ICVD.2004.1260965, 5 au 9 janvier 2004
 
26 Mir S., Integrated circuit testing: from microelectronics to microsystems, Plenary talk, 5th IFAC Symposium on Fault Detection, Supervision and Safety of Technical Processes (SAFEPROCESS'03), Washington, D.C, UNITED STATES, 9 au 11 juin 2003
 
27 Mir S., Rolindez L., Domingues C., Rufer L., An implementation of memory-based on-chip analogue test signal generation, Invited Talk, Asia and South Pacific Design Automation Conference (ASP-DAC'03) , pp. 663-668, Kitakyushu, JAPAN, 21 au 24 janvier 2003
 
28 Mir S., From microelectronics to microsystem integrated circuit testing, Plenary talk, 8th International Conference on Quality, Reliability, Maintainability, Sinaia, ROMANIA, 18 au 20 septembre 2002
 
29 Charlot B., Mir S., MEMS testing, Invited Talk, International Summer School on Advanced Microelectronics (MIGAS), Autrans, FRANCE, 23 au 29 juin 2002
 
30 Mir S., Design and test of next generation integrated systems embedding MEMS, Invited Talk, 2nd Electronics-Circuits and Systems Conference (ECS'99), pp. 301-310, Bratislava, SLOVAKIA, 1 janvier 1999
 
31 Courtois B., Karam J.M., Mir S., Lubaszewski M., Szekely V., Rencz M., Kelly G., Alderman J., Morissey A., Hofmann K., Glesner M., CAD, CAT and MPW for MEMS, Invited Talk, Eighth Workshop on Synthesis and System Integration of Mixed Technologies (SASIMI'98), pp. 207-219, Sendai, JAPAN, 19 au 20 octobre 1998
 
remonter

158 Conférences internationales

  1 Portolan M., Silveira Feitoza R., Takam Tchendjou G., Reynaud V., Senthamarai Kannan K., Barragan M., Simeu E., Maistri P., Anghel L., Leveugle R., Mir S., A Comprehensive End-to-end Solution for a Secure and Dynamic Mixed-signal 1687 System, 2020 International Symposium on On-Line Testing and Robust System Design (IOLTS 2020), Naples (Napoli), ITALY, DOI: 10.1109/IOLTS50870.2020.9159721, 13 juillet au 21 septembre 2020
 
  2 Silveira Feitoza R., Barragan M., Gines A., Mir S., On-chip reduced-code static linearity test of Vcm -based switching SAR ADCs using an incremental analog-to-digital converter, IEEE European Test Symposium (ETS 2020), Tallinn, ESTONIA, DOI: 10.1109/ETS48528.2020.9131588, 25 mai au 1 juin 2020
 
  3 Silveira Feitoza R., Barragan M., Mir S., Reduced-Code Techniques for On-Chip Static Linearity Test of SAR ADCs, 27th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), pp. 263-268, Cuzco, PERU, 6 au 9 octobre 2019
 
  4 Malloug H., Barragan M., Mir S., A 52 dB-SFDR 166 MHz sinusoidal signal generator for mixed-signal BIST applications in 28 nm FDSOI technology, European Test Symposium (ETS 2019), Baden Baden, GERMANY, 27 au 31 mai 2019
 
  5 Cilici F., Barragan M., Mir S., Lauga-Larroze E., Bourdel S., Leger G., Yield Recovery of mm-Wave Power Amplifiers using Variable Decoupling Cells and One-Shot Statistical Calibration, IEEE International Symposium on Circuits and Systems (ISCAS 2019), pp. 1-5, Sapporo, JAPAN, 26 au 29 mai 2019
 
  6 Barragan M., Leger G., Cilici F., Lauga-Larroze E., Bourdel S., Mir S., On the use of causal feature selection in the context of machine-learning indirect test, Design, Automation & Test in Europe Conference & Exhibition (DATE 2019), pp. 276-279, Florence, ITALY, 25 au 29 mars 2019
 
  7 Silveira Feitoza R., Barragan M., Mir S., Dzahini D., Reduced-code static linearity test of SAR ADCs using a built-in incremental Sigma-Delta converter, 24th IEEE International Symposium on On-Line Testing and Robust System Design (IOLTS'2018), pp. 29-34, Platja d'Aro, SPAIN, DOI: 978-1-5386-5992-2/18, 2 au 4 juillet 2018
 
  8 Cilici F., Barragan M., Mir S., Lauga-Larroze E., Bourdel S., Assisted test generation strategy for non-intrusive machine learning indirect test of millimeter-wave circuits, 23rd IEEE European Test Symposium (ETS'2018), pp. 1-6, Bremen, GERMANY, DOI: 978-1-5386-3728-9/18, 28 mai au 1 juin 2018
 
  9 Malloug H., Barragan M., Mir S., Le Gall H., Harmonic cancellation strategies for on-chip sinusoidal signal generation using digital resources, International Mixed-Signal Testing Workshop (IMSTW 2017), Thessaloniki, GREECE, DOI: 10.1109/IMS3TW.2017.7995201, 3 au 5 juillet 2017
 
 10 Malloug H., Barragan M., Mir S., Basteres L., Le Gall H., Design of a sinusoidal signal generator with calibrated harmonic cancellation for mixed-signal BIST in a 28 nm FDSOI technology, European Test Symposium (ETS 2017), Limassol, CYPRUS, DOI: 10.1109/ETS.2017.7968214, 22 au 26 mai 2017
 
 11 Portolan M., Barragan M., Alhakim R., Mir S., Mixed-Signal BIST computation offloading using IEEE 1687, European Test Symposium (ETS 2017), Limassol, CYPRUS, 22 au 26 mai 2017
 
 12 Renaud G., Margalef-Rovira M., Barragan M., Mir S., Analysis of an efficient on-chip servo-loop technique for reduced-code static linearity test of pipeline ADCs, VLSI Test Symposium (VTS 2017), Las Vegas, UNITED STATES, DOI: 10.1109/VTS.2017.7928951, 9 au 12 avril 2017
 
 13 Gines A., Peralias E., Leger G., Rueda A., Renaud G., Barragan M., Mir S., Design Trade-offs for On-chip Driving of High-speed High-performance ADCs in Static BIST Applications, IEEE 21st International Mixed-Signal Testing Workshop (IMSTW'16), Sant Feliu de Guixols, SPAIN, 4 au 7 juillet 2016
 
 14 Malloug H., Barragan M., Mir S., Le Gall H., Mostly-digital design of sinusoidal signal generators for mixed-signal BIST applications using harmonic cancellation, IEEE 21st International Mixed-Signal Testing Workshop (IMSTW'16), Sant Feliu de Guixols, SPAIN, 4 au 7 juillet 2016
 
 15 Portolan M., Barragan M., Malloug H., Mir S., Interactive Mixed-Signal Testing Through 1687, First International Test Standards Application Workshop (TESTA'16), Amsterdam, NETHERLANDS, 26 au 27 mai 2016
 
 16 Gines A., Peralias E., Leger G., Rueda A., Renaud G., Barragan M., Mir S., Linearity Test of High-speed High-performance ADCs using a Self-Testable On-chip Generator, 21st IEEE European Test Symposium (ETS'16), Amsterdam, NETHERLANDS, 23 au 27 mai 2016
 
 17 Dimakos A., Stratigopoulos H., Siligaris A., Mir S., De Foucauld E., Built-in test of millimeter-wave circuits based on non-intrusive sensors, Design, Automation and Test in Europe Conference (DATE'16), pp. 505-510, Munich, GERMANY, 14 au 18 mars 2016
 
 18 Pastorelli C., Mellot P., Mir S., Tubert C., ADC techniques for optimized conversion time in CMOS image sensors, IS&T International Symposium on Electronic Imaging, Image Sensors and Imaging Systems, pp. 268.1-268.6, San Francisco, CA, UNITED STATES, 14 au 18 février 2016
 
 19 Stratigopoulos H., Barragan M., Mir S., Le Gall H., Bhargava N., Bal A., Evaluation of low-cost mixed-signal test techniques for circuits with long simulation times, IEEE International Test Conference (ITC'15), Anaheim, CA, UNITED STATES, 6 au 8 octobre 2015
 
 20 Renaud G., Barragan M., Mir S., Design of an on-chip stepwise ramp generator for ADC static BIST applications, IEEE International Mixed-Signal Testing Workshop (IMS3TW'15), pp. 1-6, Paris, FRANCE, DOI: 10.1109/IMS3TW.2015.7177876, 24 au 26 juin 2015
 
 21 Malloug H., Barragan M., Mir S., Evaluation of harmonic cancellation techniques for sinusoidal signal generation in mixed-signal BIST, IEEE International Mixed-Signal Testing Workshop (IMS3TW'15), Paris, FRANCE, DOI: 10.1109/IMS3TW.2015.7177877, 24 au 26 juin 2015
 
 22 Pastorelli C., Mellot P., Mir S., Tubert C., Piece-wise-linear ramp ADC for CMOS imager sensor and calibration techniques, International Image Sensor Workshop (IISW'15), Vaals, NETHERLANDS, 8 au 11 juin 2015
 
 23 Le Gall H., Alhakim R., Valka M., Mir S., Stratigopoulos H., Simeu E., High Frequency Jitter Estimator for SoCs, 20th IEEE European Test Symposium (ETS'15), Cluj-Napoca, ROMANIA, DOI: 10.1109/ETS.2015.7138760, 25 au 29 mai 2015
 
 24 Fei R., Moreau J., Mir S., Marcellin A., Mandier G., Huiss E., Palmigiani G., Vitrou P., Droniou T., Horizontal-FPN fault coverage improvement in production test of CMOS imagers, 33rd IEEE International VLSI Test Symposium (VTS'15), Napa, California, UNITED STATES, DOI: 10.1109/VTS.2015.7116278, 27 au 29 avril 2015
 
 25 Serhan A., Abdallah L., Stratigopoulos H., Mir S., Low-cost EVM built-in test of RF transceivers, 9th IEEE International Design and Test Symposium (IDT'14), pp. 51-54, Algiers, ALGERIA, DOI: 10.1109/IDT.2014.7038586, 16 au 18 décembre 2014
 
 26 Renaud G., Barragan M., Mir S., On-Chip Implementation of an Integrator-Based Servo-Loop for ADC Static Linearity Test , 23rd IEEE Asian Test Symposium (ATS'14), pp. 212-217, Hangzhou, CHINA, DOI: 10.1109/ATS.2014.47, 16 au 19 novembre 2014
 
 27 Dubois M., Stratigopoulos H., Mir S., Barragan M., Evaluation of digital ternary stimuli for dynamic test of ΣΔ ADCs , IFIP/IEEE 22nd International Conference on Very Large Scale Integration (VLSI-SoC'14), pp. 1-6, Playa del Carmen, Mexico, MEXICO, DOI: 10.1109/VLSI-SoC.2014.7004153, 6 au 8 octobre 2014
 
 28 Dimakos A., Stratigopoulos H., Siligaris A., Mir S., De Foucauld E., Non-intrusive built-in test for 65nm RF LNA , IEEE International Mixed-signals, Sensors and Systems Test Workshop (IMS3TW'14), Porto Alegre, BRAZIL, DOI: 10.1109/IMS3TW.2014.6997397, 17 au 19 septembre 2014
 
 29 Andraud M., Deluthault A., Dieng M., Azais F., Bernard S., Cauvet P., Comte M., Kervaon T., Kerzerho V., Mir S., Pugliesi-Conti P., Renovell M., Soulier F., Simeu E., Stratigopoulos H., Solutions for the self-adaptation of communicating systems in operation, IEEE International On-line Test Symposium (IOLTS'14), pp. 234-239, Platja d’Aro, SPAIN, DOI: 10.1109/IOLTS.2014.6873705, 7 au 9 juillet 2014
 
 30 Beznia K., Bounceur A., Mir S., Euler R., Output parameter reduction for an efficient evaluation of alternative test techniques, 28th International Conference on Design of Circuits and Integrated Systems (DCIS'13), pp. 258-263, San Sebastian, SPAIN, 27 au 29 novembre 2013
 
 31 Bentobache M., Bounceur A., Euler R., Kieffer Y., Mir S., New techniques for selecting test frequencies for linear analog circuits, 21st IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC'13), pp. 90-95, Istanbul, TURKEY, 7 au 9 octobre 2013
 
 32 Huang K., Stratigopoulos H., Mir S., Fault modeling and diagnosis for nanometric analog circuits, IEEE International Test Conference (ITC'13), Paper PTF3, Anaheim, CA, UNITED STATES, DOI: 10.1109/TEST.2013.6651886, 6 au 13 septembre 2013
 
 33 Abdallah L., Stratigopoulos H., Mir S., Non-intrusive sensors for testing RF circuits, IEEE International Test Conference (ITC'13), Paper PTF2, Anaheim, CA, UNITED STATES, DOI: 10.1109/TEST.2013.6651885, 6 au 13 septembre 2013
 
 34 Fei R., Moreau J., Mir S., BIST of interconnection lines in the pixel matrix of CMOS imagers, 5th IEEE International Workshop on Advances in Sensors and Interfaces (IWASI'13), pp. 174-177, Bari, ITALY, DOI: 10.1109/IWASI.2013.6576068, 13 au 14 juin 2013
 
 35 Abdallah L., Stratigopoulos H., Mir S., Altet J., Defect-Oriented Non-Intrusive RF Test Using On-Chip Temperature Sensors, IEEE VLSI Test Symposium (VTS'13), Berkeley, CA, UNITED STATES, DOI: 10.1109/VTS.2013.6548889, 29 avril 2013
 
 36 Laraba A., Stratigopoulos H., Mir S., Naudet H., Bret G., Reduced code linearity testing of pipeline adcs in the presence of noise , IEEE VLSI Test Symposium (VTS'13), Berkeley, CA, UNITED STATES, DOI: 10.1109/VTS.2013.6548913, 29 avril 2013
 
 37 Huang K., Stratigopoulos H., Abdallah L., Mir S., Bounceur A., Multivariate Statistical Techniques for Analog Parametric Test Metrics Estimation, 8th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS'13), pp. 06-11, Abu Dhabi, UNITED ARABIAN EMIRATES, 26 au 28 mars 2013
 
 38 Beznia K., Bounceur A., Mir S., Euler R., Statistical Modelling of Analog Circuits for Test Metrics Computation, 8th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS'13), pp. 25-29, Abu Dhabi, UNITED ARABIAN EMIRATES, 26 au 28 mars 2013
 
 39 Beznia K., Bounceur A., Abdallah L., Huang K., Mir S., Euler R., Accurate estimation of analog test metrics with extreme circuits, 19th IEEE International Conference on Electronics, Circuits, and Systems (ICECS'12), pp. 272 - 275, Sevilla, SPAIN, DOI: 10.1109/ICECS.2012.6463748, 9 au 12 décembre 2012
 
 40 Bounceur A., Euler R., Saoud B., Beznia K., Mir S., A tool for statistical modeling by means of Copulas of analog and mixed-signal circuits, 27th International Conference on Design of Circuits and Integrated Systems (DCIS'12), pp. 256-260, Avignon, FRANCE, 28 au 30 novembre 2012
 
 41 Abdallah L., Stratigopoulos H., Mir S., Kelma C., Experiences with non-intrusive sensors for RF built-in test, IEEE International Test Conference (ITC'12), Paper 17.1, Anaheim, CA, UNITED STATES, DOI: 10.1109/TEST.2012.6401587 , 5 au 8 novembre 2012
 
 42 Dragulinescu A., Lizarraga L., Mir S., Effects of doping concentrations on the photocurrent and dark current of a CMOS photodiode, Advanced Topics in Optoelectronics, Microelectronics, and Nanotechnologies VI, Constanta, ROMANIA, DOI: 10.1117/12.966394 , 1 novembre 2012
 
 43 Laraba A., Stratigopoulos H., Mir S., Naudet H., Forel C., Enhanced Reduced Code Linearity Test Technique for Multi-bit/Stage Pipeline ADCs, 17th IEEE European Test Symposium (ETS’12), Annecy, FRANCE, DOI: 10.1109/ETS.2012.6233009, 28 mai 2012
 
 44 Dubois M., Stratigopoulos H., Mir S., Ternary Stimulus for Fully Digital Dynamic Testing of SC ΣΔ ADCs , IEEE International Mixed-Signals, Sensors, and Systems Test Workshop (IMS3TW'12), pp. 5 - 10 , Taipei, TAIWAN, DOI: 10.1109/IMS3TW.2012.12, 14 au 16 mai 2012
 
 45 Akkouche N., Mir S., Simeu E., Slamani M., Analog/RF test ordering in the early stages of production testing , 30th IEEE VLSI Test Symposium (VTS'12), pp. 25-30 , Hawaii, UNITED STATES, DOI: 10.1109/VTS.2012.6231075, 23 au 25 avril 2012
 
 46 Abdallah L., Stratigopoulos H., Mir S., Altet J., Testing RF Circuits With True Non-Intrusive Built-In Sensors, IEEE Design, Automation and Test in Europe (DATE'12), pp. 1090-1095, Dresden, GERMANY, 12 au 16 mars 2012
 
 47 Spyronasios A., Abdallah L., Stratigopoulos H., Mir S., On Replacing an RF Test with an Alternative Measurement: Theory and a Case Study, IEEE Asian Test Symposium (ATS’11), pp. 365-370, New Delhi, INDIA, DOI: 10.1109/ATS.2011.44 , 2 au 23 novembre 2011
 
 48 Beznia K., Bounceur A., Mir S., Euler R., Parametric test metrics estimation using non-Gaussian copulas, IEEE International Mixed-Signals, Sensors, and Systems Test Workshop (IMS3TW’11), pp. 48-52, Santa Barbara, Ca, UNITED STATES, DOI: 10.1109/IMS3TW.2011.19, 16 au 18 mai 2011
 
 49 Huang K., Stratigopoulos H., Mir S., Bayesian fault diagnosis of RF circuits using nonparametric density estimation, IEEE Asian Test Symposium (ATS’10), pp. 295-298, Shanghai, CHINA, DOI: 10.1109/ATS.2010.57 , 1 au 4 décembre 2010
 
 50 Stratigopoulos H., Mir S., Analog test metrics estimates with PPM accuracy, IEEE/ACM International Conference on Computer-Aided Design (ICCAD'10), pp. 241-247, San Jose, CA, UNITED STATES, DOI: 10.1109/ICCAD.2010.5654165 , 7 au 11 novembre 2010
 
 51 Khereddine R., Abdallah L., Simeu E., Mir S., Cenni F., Adaptive Logical Control of RF LNA performances for efficient energy consumption, 18th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC'10), pp. 161-166, Madrid, SPAIN, 27 au 29 septembre 2010
 
 52 Tongbong J., Abdallah L., Mir S., Stratigopoulos H., Evaluation of built-in sensors for RF LNA response measurement, 16th IEEE International Mixed-signals, Sensors and Systems Test Workshop (IMS3TW'10), La Grande Motte, FRANCE, DOI: 10.1109/IMS3TW.2010.5502996 , 7 au 9 juin 2010
 
 53 Abdallah L., Stratigopoulos H., Kelma C., Mir S., Sensors for built-in alternate RF test, IEEE European Test Symposium (ETS’10), pp. 49-54, Prague, CZECH REPUBLIC, DOI: 10.1109/ETSYM.2010.5512783 , 24 au 28 mai 2010
 
 54 Arthaud Y., Rufer L., Mir S., Study of a 3D MEMS-based tactile vibration sensor for the use in the middle ear surgery, International Symposium on Design, Test, Integration and Packaging of MEMS/MOEMS (DTIP’10), pp. 266-271, Sevilla, SPAIN, 5 au 7 mai 2010
 
 55 Akkouche N., Mir S., Simeu E., Ordering of analog specification tests based on parametric defect level estimation, 28th IEEE VLSI Test Symposium (VTS'10), pp. 301 - 306 , Santa Cruz, UNITED STATES, DOI: 10.1109/VTS.2010.5469546 , 19 au 22 avril 2010
 
 56 Huang K., Stratigopoulos H., Mir S., Fault diagnosis of analog circuits based on machine learning, Design, Automation and Test in Europe Conference (DATE’10) Germany, pp. 1761-1766, Dresden, GERMANY, 8 au 12 mars 2010
 
 57 Rehder G.P., Mir S., Rufer L., Simeu E., Nguyen H.N., Low Frequency Test for RF MEMS Switches, IEEE International Symposium on Electronic Design, Test and Applications (DELTA’10), pp. 350-354, Ho Chi Minh City, VIET NAM, DOI: 10.1109/DELTA.2010.16 , 13 au 15 janvier 2010
 
 58 Tounsi F., Rufer L., Mezghani B., Masmoudi M., Mir S., Highly Flexible Membrane Systems for Micromachined Microphones – Modeling and Simulation, 3rd IEEE International Conference on Signals, Circuits and Systems, (SCS'09), DJerba, TUNISIA, 6 au 8 novembre 2009
 
 59 Cenni F., Simeu E., Mir S., Macro-modeling of analog blocks for SystemC-AMS simulation: A chemical sensor case-study, 17th IFIP International Conference on Very Large Scale Integration (VLSI-SoC’09), Florianapolis, BRAZIL, 12 octobre 2009
 
 60 Dubois M., Stratigopoulos H., Mir S., Hierarchical parametric test metrics estimation: A sigma-delta converter BIST case-study, 27th IEEE International Conference on Computer Design (ICCD’09), pp. 78-83, Lake Tahoe, California, UNITED STATES, DOI: 10.1109/ICCD.2009.5413173 , 4 au 7 octobre 2009
 
 61 Cenni F., Mir S., Rufer L., Behavioral modeling and simulation of a chemical sensor with its microelectronics front-end interface, 3rd IEEE International Workshop on Advances in Sensors and Interfaces (IWASI’09), pp. 92-97, Trani, ITALY, DOI: 10.1109/IWASI.2009.5184776, 25 au 26 juin 2009
 
 62 Stratigopoulos H., Mir S., Acar E., Ozev S., Defect filter for alternate RF test, IEEE European Test Symposium (ETS’09), pp. 101-106 , Sevilla, SPAIN, DOI: 10.1109/ETS.2009.32, 25 au 29 mai 2009
 
 63 Lizarraga L., Mir S., Sicard G., Experimental validation of a BIST technique for CMOS active pixel sensors, 27th IEEE VLSI Test Symposium (VTS’09), pp. 189-194, Santa Cruz, UNITED STATES, DOI: 10.1109/VTS.2009.30, 3 au 7 mai 2009
 
 64 Asquini A., Bounceur A., Mir S., Badets F., Carbonero J.L., Bouzaida L., DFT technique for RF PLLs using built-in monitors , Design and Technology of Integrated Systems (DTIS’09), pp. 210-215, Cairo, EGYPT, 6 au 7 avril 2009
 
 65 Tounsi F., Mezghani B., Rufer L., Mir S., Masmoudi M., Electromagnetic modelling of an integrated micromachined inductive microphone, Design and Technology of Integrated Systems (DTIS’09), pp. 38-44, Cairo, EGYPT, DOI: 10.1109/DTIS.2009.4938020, 6 au 7 avril 2009
 
 66 Stratigopoulos H., Mir S., Makris Y., Enrichment of limited training sets in machine-learning-based analog/RF Test, Design, Automation and Test in Europe Conference (DATE’09), pp. 1668 - 1673 , Nice, FRANCE, 2 au 24 avril 2009
 
 67 Khereddine R., Simeu E., Mir S., Parameter identification of RF transceiver blocks using regressive models, IFAC Workshop on Programmable Devices and Embedded Systems (PDeS’09), pp. 67-72, Roznov pod Radhostem, CZECH REPUBLIC, 1 au 12 février 2009
 
 68 Lechuga Y., Bounceur A., Mozuelos R., Martinez M., Bracho S., Mir S., Test limit evaluation for an ADC Design-for-Test approach by using a CAT platform, 23rd International Conference on Design of Circuits and Integrated Systems (DCIS’08), Grenoble, FRANCE, 12 au 14 novembre 2008
 
 69 Kupka R., Simeu E., Stratigopoulos H., Rufer L., Mir S., Tumova O., Signature analysis for MEMS pseudorandom testing using neural networks, 12th IMEKO TC1 & TC7 Joint Symposium on Man Science & Measurement, pp. 321-325, Annecy, FRANCE, 3 au 5 septembre 2008
 
 70 Bounceur A., Mir S., Estimation of test metrics for AMS/RF BIST using Copulas, 14th IEEE International Mixed-Signals, Sensors and Systems Test Workhop (IMS3TW’08), Vancouver, CANADA, DOI: 10.1109/IMS3TW.2008.4581615 , 18 au 20 juin 2008
 
 71 Asquini A., Badets F., Mir S., Carbonero J.L., Bouzaida L., PFD output monitoring for RF PLL BIST, 14th IEEE International Mixed-Signals, Sensors and Systems Test Workhop (IMS3TW’08), Vancouver, CANADA, DOI: 10.1109/IMS3TW.2008.4581625 , 18 au 20 juin 2008
 
 72 Khereddine R., Simeu E., Mir S., RF transceiver parameter identification using regressive models, International Conference on Design and Technology of Integrated Systems (DTIS’08), pp. 166, Tozeur, TUNISIA, DOI: 10.1109/DTIS.2008.4540208 , 25 au 27 mars 2008
 
 73 Stratigopoulos H., Tongbong J., Mir S., A general method to evaluate RF BIST techniques based on non-parametric density estimation , IEEE Design Automation and Test in Europe (DATE'08), pp. 68-73, Munich, GERMANY, DOI: 10.1109/DATE.2008.4484662, 10 au 14 mars 2008
 
 74 Rolindez L., Mir S., Carbonero J.L., Goguet D., Chouba N., A Stereo Audio ΣΔ ADC Architecture with Embedded SNDR Self-Test, IEEE International Test Conference (ITC’07), Paper 32.1, Santa Clara, UNITED STATES, 23 au 25 octobre 2007
 
 75 Lizarraga L., Mir S., Sicard G., Evaluation of a BIST technique for CMOS imagers, IEEE Asian Test Symposium (ATS’07) , pp. 378-383 , Beijing, CHINA, 8 au 11 octobre 2007
 
 76 Akkouche N., Bounceur A., Mir S., Simeu E., Minimization of functional tests by statistical modelling of analogue circuits, International Conference on Design and Technology of Integrated Systems (DTIS’07), pp. 35-40, Rabat, MOROCCO, 2 au 5 septembre 2007
 
 77 Lalinsky T., Rufer L., Vanko G., Mir S., AlGaN/GaN heterostructure based surface acoustic wave structures for chemical sensors, 11th International Conference on the Formation of Semiconductor Interfaces (ICFSI’07), Manaus, BRAZIL, 19 au 24 août 2007
 
 78 Simeu E., Mir S., Khereddine R., Nguyen H.N., Envelope detection based transition time supervision for online testing of RF MEMS switches, IEEE International On-Line Test Symposium (IOLT’07), pp. 237-243, Crete, GREECE, DOI: 10.1109/IOLTS.2007.30, 8 au 11 juillet 2007
 
 79 Akkouche N., Bounceur A., Mir S., Simeu E., Functional test compaction by statistical modelling of analogue circuits, 13th IEEE International Mixed-Signals Testing Workhop (IMSTW’07), pp. 20-24, Porto, PORTUGAL, 18 au 20 juin 2007
 
 80 Simeu E., Nguyen H.N., Cauvet P., Mir S., Rufer L., Khereddine R., Using signal envelope detection for RF MEMS switch testing, 13th IEEE International Mixed-Signals Testing Workhop (IMSTW’07), pp. 68-73, Porto, PORTUGAL, 18 au 20 juin 2007
 
 81 Asquini A., Carbonero J.L., Mir S., Test measurements evaluation for VCO and charge pump blocks in RF PLLs, SPIE International Symposium on Microtechnologies for the New Millenium, VLSI Circuits and Systems Conference, pp. 1A1-1A8, Gran Canaria, SPAIN, DOI: 10.1117/12.721819 , 10 mai 2007
 
 82 Tongbong J., Mir S., Carbonero J.L., Evaluation of test measures for LNA production testing using a multinormal statistical model, IEEE Design, Automation & Test in Europe Conference & Exhibition (DATE '07), pp. 731-736, Nice, FRANCE, DOI: 10.1109/DATE.2007.364682, 16 au 20 avril 2007
 
 83 Lizarraga L., Mir S., Sicard G., Dragulinescu A., Defect and fault modelling of CMOS active pixel sensors, IEEE Latin American Test Workshop (LATW’07), Cuzco, PERU, 11 au 14 mars 2007
 
 84 Dragulinescu A., Lizarraga L., Mir S., Sicard G., Defect and fault modelling of a CMOS n-diffusion photodiode, 3rd International Conference on Advanced Topics in Optoelectronics, Microelectronics and Nanotechnologies (ATOM-N’06), pp. 43-44, Bucharest, ROMANIA, 24 au 26 novembre 2006
 
 85 Rolindez L., Mir S., Carbonero J.L., Design of a 96-dB audio Sigma-Delta ADC including a BIST technique for SNDR testing, 21st Conference on Design of Circuits and Integrated Systems (DCIS’06), Barcelona, SPAIN, 22 au 24 novembre 2006
 
 86 Dhayni A., Mir S., Rufer L., Bounceur A., Characterization and testing of MEMS nonlinearities, International Design and Test Symposium (IDT’06), Dubai, UNITED ARABIAN EMIRATES, 19 au 20 novembre 2006
 
 87 Bounceur A., Mir S., Simeu E., Rolindez L., CAT platform for analogue and mixed-signal test evaluation and optimization , 14th IFIP International Conference on Very Larage Scale Integration (VLSI-SoC’06), pp. 320-325, Nice, FRANCE, 16 au 18 octobre 2006
 
 88 Rufer L., Lalinsky T., Grobelny D., Mir S., Vanko G., Oszi Z., Mozolova Z., Gregus J., GaAs and GaN based SAW chemical sensors: acoustic part design and technology , 6th International Conference on Advanced Semiconductor Devices and Microsystems (ASDAM’06), pp. 165-168, Smolenice, SLOVAKIA, 16 au 18 octobre 2006
 
 89 Lizarraga L., Mir S., Sicard G., Bounceur A., Study of a BIST technique for CMOS active pixel sensors, 14th IFIP International Conference on Very Large Scale Integration (VLSI-SoC’06), pp. 326-331, Nice, FRANCE, 16 au 18 octobre 2006
 
 90 Bounceur A., Mir S., Simeu E., Rolindez L., Estimation of test metrics for multiple analogue parametric deviations, International Conference on Design and Technology of Integrated Systems (DTIS'06), pp. 234-239, Tunis, TUNISIA, 5 au 7 septembre 2006
 
 91 Bounceur A., Mir S., Rolindez L., Simeu E., On the accurate estimation of test metrics for multiple analogue parametric deviations, 12th International Mixed-Signals Testing Workshop (IMSTW’06), pp. 19-26, Edinburgh, UNITED KINGDOM, 21 au 23 juin 2006
 
 92 Dhayni A., Mir S., Rufer L., Pseudorandom functional BIST for MEMS, 12th International Mixed-Signals Testing Workshop (IMSTW’06), pp. 143-149, Edinburgh, UNITED KINGDOM, 21 au 23 juin 2006
 
 93 Rolindez L., Mir S., Bounceur A., Carbonero J.L., A SNDR BIST for SigmaDelta Analogue-to-Digital Converters, 24th IEEE VLSI Test Symposium (VTS'06), pp. 314-319, Berkeley, CA, UNITED STATES, DOI: 10.1109/VTS.2006.12, 30 avril 2006
 
 94 Dhayni A., Mir S., Rufer L., Bounceur A., Pseudorandom Functional BIST for Linear and Nonlinear MEMS, IEEE Design, Automation and Test in Europe Conference (DATE '06), pp. 664-669, Munich, GERMANY, 6 au 10 mars 2006
 
 95 Rufer L., Torres A., Mir S., Alam M.O., Lalinsky T., Chan Y.C., SAW chemical sensors based on AlGaN/GaN piezoelectric material system: acoustic design and packaging considerations, International Symposium on Electronics Materials and Packaging (EMAP'05), pp. 204-208, Tokyo, JAPAN, DOI: 10.1109/EMAP.2005.1598262, 11 au 14 décembre 2005
 
 96 Dhayni A., Mir S., Rufer L., Bounceur A., On-chip pseudorandom testing for linear and nonlinear MEMS, International Conference on Very Larage Scale Integration (VLSI-SoC’05), pp. 435-440, Perth, AUSTRALIA, 17 au 19 octobre 2005
 
 97 Matakias S., Tsiatouhas Y., Arapoyanni A., Haniotakis Th., Prenat G., Mir S., A built-in IDDQ testing circuit, 31st European Solid-State Circuits Conference (ESSCIRC'05), pp. 471-474, Grenoble, FRANCE, DOI: 10.1109/ESSCIR.2005.1541662, 12 au 16 septembre 2005
 
 98 Rolindez L., Mir S., Bounceur A., Carbonero J.L., A digital bist for a 16-bit audio sigma-delta analogue-to-digital converter, 11th Annual International Mixed-Signals Testing Workshop (IMSTW'05), pp. 45-52, Cannes, FRANCE, 27 au 29 juin 2005
 
 99 Dhayni A., Mir S., Rufer L., Bounceur A., Nonlinearity effects on MEMS on-chip pseudorandum testing, 11th Annual International Mixed-Signals Testing Workshop (IMSTW'05), pp. 224-233, Cannes, FRANCE, 27 au 29 juin 2005
 
100 Simeu E., Mir S., Parameter identification based diagnosis in linear and non-linear mixed-signal systems , International Mixed-Signals Testing Workshop (IMSTW'05), pp. 140-147, Cannes, FRANCE, 27 au 29 juin 2005
 
101 Dhayni A., Mir S., Rufer L., Evaluation of impulse response-based BIST techniques for MEMS in the presence of weak nonlinearities, European Test Symposium (ETS 2005), pp. 82-87, Tallinn, ESTONIA, DOI: 10.1109/ETS.2005.21, 22 au 25 mai 2005
 
102 Rolindez L., Mir S., Prenat G., Digital test of a ΣΔ modulator in a mixed-signal BIST architecture, SPIE Microtechnologies for the New Millennium, VLSI circuits and systems II, pp. 502-512, Sevilla, SPAIN, DOI: 10.1117/12.607615, 9 au 11 mai 2005
 
103 Kheriji R., Danelon V., Carbonero J.L., Mir S., Optimising Test Sets for a Low Noise Amplifier with a Defect-Oriented Approach, IEEE Design, Automation and Test in Europe Conference (DATE'05), pp. 170-171, Munich, GERMANY, DOI: 10.1109/DATE.2005.233, 7 au 11 mars 2005
 
104 Kheriji R., Danelon V., Carbonero J.L., Mir S., Optimising test sets for RF components with a defect-oriented approach, 16th International Conference on Microelectronics (ICM'04), pp. 400-403, Tunis, TUNISIA, DOI: 10.1109/ICM.2004.1434597, 6 au 8 décembre 2004
 
105 Bounceur A., Mir S., Simeu E., Optimisation of digitally coded test vectors for mixed-signal components, 19th Conference on Design of Circuits and Integrated Systems (DCIS'04), Bordeaux, FRANCE, 24 au 26 novembre 2004
 
106 Prenat G., Mir S., Vasquez D., Rolindez L., A low-cost digital frequency testing approach for mixed-signal devices using sigma-delta modulation, 10th International Mixed-Signal Testing Workshop (IMSTW'04), Portland, UNITED STATES, 23 au 25 juin 2004
 
107 Dhayni A., Mir S., Rufer L., MEMS Built-In-Self-Test Using MLS, IEEE European Test Symposium (ETS'04), pp. 66-71, Corse, FRANCE, DOI: 10.1109/ETSYM.2004.1347607, 23 au 26 mai 2004
 
108 Rolindez L., Mir S., Prenat G., Bounceur A., A 0.18 mu m CMOS implementation of on-chip analogue test signal generation from digital test patterns, Design, Automation and Test in Europe Conference (DATE'04), pp. 704-705, Dresden, GERMANY, DOI: 10.1109/DATE.2004.1268939, 24 au 28 janvier 2004
 
109 Naal M. A., Simeu E., Mir S., Comparative study of online testing methods for AMS application to decimation filters, International Conference on Information and Communication Technologies: From Theory to Applications (ICTTA'04), pp. 393-394, Damascus, SYRIAN ARAB REPUBLIC, DOI: 10.1109/ICTTA.2004.1307797, 1 janvier 2004
 
110 Domingues C., Mir S., Rufer L., Design of a MEMS-based ultrasonic pulse-echo system, 18th Conference on Design of Circuits and Integrated Systems (DCIS'03), pp. 623-628, Ciudad Real, SPAIN, 18 au 21 novembre 2003
 
111 Rufer L., Mir S., Domingues C., Simeu E., MLS-based technique for MEMS characterization , 3rd International Workshop on Microfabricated Ultrasonic Transducers (MUT'03), pp. 157-164, Lausanne, SWITZERLAND, 26 au 27 juin 2003
 
112 Rufer L., Mir S., Simeu E., Domingues C., On-chip pseudorandom MEMS testing, 9th International Mixed-Signal Testing Workshop (IMSTW'03), pp. 93-98, Sevilla, SPAIN, 25 au 27 juin 2003
 
113 Rufer L., Mir S., Simeu E., Domingues C., On-chip testing of MEMS using pseudo-random test sequences, Design, Test, Integration and Packaging of MEMS/MOEMS (DTIP'03) , pp. 50-55, Mandelieu (Cannes), FRANCE, DOI: 10.1109/DTIP.2003.1287007, 5 au 7 mai 2003
 
114 Rufer L., Mir S., Simeu E., On-chip testing of linear time invariant systems using maximum length sequences, IFAC Workshop on Programmable Devices and Systems (PDS'03), pp. 437-440, Ostrava, CZECH REPUBLIC, 11 au 13 février 2003
 
115 Naal M. A., Simeu E., Mir S., On-Line Testable Decimation Filter Design for AMS Systems, 9th IEEE International On-Line Testing Symposium (IOLT'03), pp. 83-88, Kos Island, GREECE, DOI: 10.1109/OLT.2003.1214371, 1 janvier 2003
 
116 Mir S., Rufer L., Domingues C., Behavioral modelling and simulation of a MUT-based pulso-echo system, 2nd International Workshop on Microfabricated Ultrasonic Transducers, pp. 18-24, Besançon, FRANCE, 27 au 28 juin 2002
 
117 Mir S., Diedrich C., Roman C., Domingues C., On-chip test signal generation for acoustic and ultrasound microelectronic interfaces, 8th IEEE International Mixed-Signal Testing Workshop (IMSTW'02), pp. 137-144, Montreux, SWITZERLAND, 13 au 15 juin 2002
 
118 Roman C., Mir S., Charlot B., Building and analogue fault simulation tool and its application to MEMS, 8th IEEE International Mixed-Signal Testing Workshop (IMST3W'02), pp. 65-74, Montreux, SWITZERLAND, 1 juin 2002
 
119 Rufer L., Domingues C., Mir S., Behavioural modelling and simulation of a MEMS-based ultrasonic pulse-echo system, Symposium on Design, Test, Integration and Packaging of MEMS/MOEMS (DTIP'02), pp. 171-182, Cannes, FRANCE, 1 janvier 2002
 
120 Charlot B., Mir S., Parrain F., Courtois B., Electrically induced stimuli for MEMS self-test, 19th IEEE VLSI Test Symposium (VTS'01), pp. 210-215, Marina del Rey, CA, UNITED STATES, DOI: 10.1023/A:1012860420235, 29 avril au 3 mai 2001
 
121 Charlot B., Parrain F., Mir S., Courtois B., A self-testable CMOS thermopile-based infrared imager, Design, Test, Integration, and Packaging of MEMS/MOEMS (DTIP'01), pp. 96-103, Mandelieu (Cannes), FRANCE, 25 au 27 avril 2001
 
122 Poppe A., Farkas G., Rencz M., Benedek Zs., Pohl L., Szekely V., Torki K., Mir S., Courtois B., Design issues of a multi-functional intelligent thermal test die, Seventeenth Annual IEEE Semiconductor Thermal Measurement and Management Symposium (SEMI-THERM'01), pp. 50-57, San Jose, CA, UNITED STATES, DOI: 10.1109/STHERM.2001.915144, 20 au 22 mars 2001
 
123 Courtois B., Mir S., Charlot B., Lubaszewski M., An analog-based approach for MEMS testing, 2nd IEEE Latin-American Test Workshop (LATW'01 ), pp. 200-203, Cancun, MEXICO, 11 au 14 février 2001
 
124 Courtois B., Mir S., Charlot B., Lubaszewski M., From microelectronics to MEMS testing, IEEE Microelectronics Reliability and Qualification Workshop , pp. paper VI.8, Glendale, Ca., UNITED STATES, 31 octobre au 1 novembre 2000
 
125 Poppe A., Farkas G., Rencz M., Benedek Zs., Pohl L., Szekely V., Torki K., Mir S., Courtois B., Design of a scalable multi-functional thermal test die with direct and boundary scan access for programmed excitation and data measurement, 6th International Workshop on Thermal Investigations of ICs and Systems (THERMINIC'00), pp. 267-272, Budapest, HUNGARY, 24 au 27 septembre 2000
 
126 Mir S., Charlot B., Parrain F., Veychard D., High thermal impedance beams for suspended MEMS, Design, Test, Integration, and Packaging of MEMS/MOEMS (DTIP'00), pp. 99-107, Paris, FRANCE, 9 au 11 mai 2000
 
127 Mir S., Charlot B., Nicolescu G., Coste P., Parrain F., Zergainoh N.-E., Courtois B., Jerraya A. A., Rencz M., Towards design and validation of mixed-technology SOCs, Great Lakes Symposium on VLSI , pp. 29 - 33, Chicago, Illinois, UNITED STATES, DOI: 10.1145/330855.330950, 2 au 4 mars 2000
 
128 Charlot B., Mir S., Cota E.F., Lubaszewski M., Courtois B., Fault modeling of suspended thermal MEMS, IEEE International Test Conference (ITC'99), pp. 319-28, Atlantic City, NJ , UNITED STATES, DOI: 10.1109/TEST.1999.805646, 28 au 30 septembre 1999
 
129 Mir S., Charlot B., Courtois B., Extending fault-based testing to microelectromechanical systems, European Test Workshop (ETW'99), pp. 64-68, Constance, GERMANY, DOI: 10.1109/ETW.1999.804234, 25 au 28 mai 1999
 
130 Charlot B., Moussouris S., Mir S., Courtois B., Fault modeling of electrostatic comb-drives for MEMS, Design, Test, and Microfabrication of MEMS and MOEMS (DTIP'99), pp. 398-405, Paris, FRANCE, DOI: 10.1117/12.341226, 31 mars au 1 avril 1999
 
131 Charlot B., Mir S., Cota E.F., Lubaszewski M., Courtois B., Fault simulation of MEMS using HDLs, SPIE Symposium on Design, Test and Microfabrication of MEMS/MOEMS (DTIP'99), pp. 70-77, Paris, FRANCE, DOI: 10.1117/12.341215, 31 mars au 1 avril 1999
 
132 Courtois B., Karam J.M., Mir S., Lubaszewski M., Szekely V., Rencz M., Hofmann K., Glesner M., Design and test of MEMS, Twelfth International Conference on VLSI Design, pp. 270-275, Goa, INDIA, DOI: 10.1109/ICVD.1999.745160, 7 au 10 janvier 1999
 
133 Velasco-Medina J., Mir S., Nicolaidis M., Current-based testing for high-frequency CMOS operational amplifiers, XIII International Conference on Design of Circuits and Integrated Systems (DCIS'98), pp. 438-443, Madrid, SPAIN, 15 novembre 1998
 
134 Castillejo A., Veychard D., Mir S., Karam J.M., Courtois B., Failure Mechanisms and Fault Classes for CMOS-Compatible Microelectromechanical Systems, IEEE International Test Conference (ITC'98), pp. 541-550, Washington, D.C, UNITED STATES, DOI: 10.1109/TEST.1998.743197, 18 au 23 octobre 1998
 
135 Velasco-Medina J., Mir S., Nicolaidis M., Current-testable high-frequency CMOS operational amplifiers, Eleventh Annual IEEE International ASIC Conference, pp. 95-99, Rochester, N.Y., UNITED STATES, DOI: 10.1109/ASIC.1998.722810, 16 septembre 1998
 
136 Lubaszewski M., Renovell M., Mir S., Azais F., Bertrand Y., A multi-mode stimuli generator for analogue and mixed-signal built-in-self-test, 4th IEEE International Mixed Signal Testing Workshop (IMSTW'98), pp. 100-106, The Hague, NETHERLANDS, 8 au 11 juin 1998
 
137 Mir S., Rueda A., Vazquez D., Huertas J.L., Switch-level fault coverage analysis for switched-capacitor systems, IEEE Design, Automation and Test in Europe (DATE'98), pp. 810-814, Paris, FRANCE, DOI: 10.1109/DATE.1998.655951, 23 au 26 février 1998
 
138 Lubaszewski M., Renovell M., Mir S., Azais F., Bertrand Y., A built-in multi-mode stimuli generator for analogue and mixed-signal testing, XI Brazilian Symposium on Integrated Circuit Design, pp. 175 - 178, Buzios, Rio de Janeiro, BRAZIL, DOI: 10.1109/SBCCI.1998.715435, 1 janvier 1998
 
139 Mir S., Rueda A., Vazquez D., Huertas J.L., Test optimization in switched-capacitor systems through switch-level fault coverage analysis, XII International Conference on Design of Circuits and Integrated Systems (DCIS'97), pp. 125-130, Sevilla, SPAIN, 1 novembre 1997
 
140 Renovell M., Lubaszewski M., Mir S., Azais F., Bertrand Y., A multi-mode signature analyzer for analog and mixed circuits, 9th IFIP International Conference on Very Large Scale Integration (VLSI'97), pp. 65-76, Gramado, BRAZIL, 1 août 1997
 
141 Mir S., Rueda A., Huertas J.L., Liberali V., A BIST technique for sigma-delta modulators based on circuit reconfiguration, IEEE 3rd International Test Mixed Signal Testing Workshop (IMSTW'97), pp. 179-184, Seattle, UNITED STATES, 3 au 6 juin 1997
 
142 Mir S., Rueda A., Olbrich T., Peralias E., Huertas J.L., SWITTEST: Automatic Switch-level Fault Simulation and Test Evaluation of Switched-Capacitor Systems, 34th Conference on Design Automation Conference (DAC'97), pp. 281-286, Anaheim, CA, UNITED STATES, DOI: 10.1109/DAC.1997.597158, 1 janvier 1997
 
143 Lubaszewski M., Mir S., Pulz L., ABILBO: Analog BuILt-in block observer, IEEE/ACM International Conference on Computer Aided Design (ICCAD'96), pp. 600-603, San Jose, CA, UNITED STATES, DOI: 10.1109/ICCAD.1996.569917, 10 au 14 novembre 1996
 
144 Francesconi F., Liberali V., Lubaszewski M., Mir S., Design of high-performance band-pass sigma-delta modulator with concurrent error detection, Third IEEE International Conference on Electronics, Circuits, and Systems (ICECS '96), pp. 1202-1205, Rhodes, GREECE, DOI: 10.1109/ICECS.1996.584641, 13 au 16 octobre 1996
 
145 Lubaszewski M., Mir S., Pulz L., A multifunctional test structure for analog BIST, IEEE International Mixed Signal Testing Workshop (IMSTW'96), pp. 239-244, Quebec, CANADA, 1 mai 1996
 
146 Mir S., Kolarik V., Lubaszewski M., Vasquez D., Detectability of differential bridges in balanced circuits, IEEE International Mixed Signal Testing Workshop (IMSTW'96), pp. 23-28, Quebec, CANADA, 1 mai 1996
 
147 Mir S., Lubaszewski M., Kolarik V., Courtois B., Automatic test generation for maximal diagnosis of linear analog circuits, European Design and Test Conference (ED&TC'96), pp. 254-258, Paris, FRANCE, DOI: 10.1109/EDTC.1996.494157, 11 au 14 mars 1996
 
148 Mir S., Lubaszewski M., Liberali V., Courtois B., Built-in self-test approaches for analogue and mixed-signal integrated circuits, 38th Midwest Symposium on Circuits and Systems (MSCS'95), pp. 1145-50, Rio de Janeiro, BRAZIL, DOI: 10.1109/MWSCAS.1995.510298, 1 août 1995
 
149 Lubaszewski M., Mir S., Rueda A., Huertas J.L., Concurrent error detection in analog and mixed-signal integrated circuits, 38th Midwest Symposium on Circuits and Systems (MSCS'95), pp. 1151-1156, Rio de Janeiro, BRAZIL, DOI: 10.1109/MWSCAS.1995.510299, 1 août 1995
 
150 Mir S., Lubaszewski M., Kolarik V., Courtois B., Programmable self-checking analogue oscillators, IEEE International On-line Testing Workshop (IOLT'95), pp. 30-33, Nice, FRANCE, 4 au 5 juillet 1995
 
151 Mir S., Lubaszewski M., Kolarik V., Courtois B., Analogue on-line/off-line test unification for fully differential circuits, IEEE International Mixed Signal Testing Workshop, pp. 56-61, Villard-de-Lans, FRANCE, 1 juin 1995
 
152 Mir S., Lubaszewski M., Kolarik V., Courtois B., Optimal ATPG for analogue built-in self-test and fault diagnosis, IEEE International Mixed Signal Testing Workshop (IMSTW'95), pp. 80-85, Villard-de-Lans, FRANCE, 1 juin 1995
 
153 Lubaszewski M., Kolarik V., Mir S., Nielsen C., Courtois B., Mixed-signal circuits and boards for high safety applications, European Design and Test Conference (ED&TC '95), pp. 34-39, Paris, FRANCE, DOI: 10.1109/EDTC.1995.470, 6 au 9 mars 1995
 
154 Mir S., Kolarik V., Lubaszewski M., Nielsen C., Courtois B., Built-in self-test and fault diagnosis of fully differential analogue circuits, IEEE International Conference on Computer Aided Design (ICCAD'94), pp. 486-90, San Jose, CA, UNITED STATES, 6 au 10 novembre 1994
 
155 Kolarik V., Lubaszewski M., Mir S., Courtois B., A brief on analogue on-line checkers, Electronic Devices and Systems Conference (EDS'94), pp. 198-201, Brno, CZECH REPUBLIC, 1 novembre 1994
 
156 Mir S., Filer N.-P., Re-engineering hardware specifications by exploiting design semantics, European Design Automation Conference (Euro-DAC'94), pp. 336-341, Grenoble, FRANCE, 1 septembre 1994
 
157 Mir S., Filer N.-P., Heuristic classification of cells in logic electronic specifications, 10th IEEE Conference on Artificial Intelligence for Applications, pp. 23.1-23.7, San Antonio, UNITED STATES, 1 au 4 mars 1994
 
158 Mir S., Kolarik V., Lubaszewski M., Courtois B., Built-in self-test of fully differential circuits, Electronic Devices and Systems Conference (EDS), pp. 33-36, Brno, CZECH REPUBLIC, 1 janvier 1994
 
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11 Chapitres de livre

 1 Bentobache M., Bounceur A., Euler R., Mir S., Kieffer Y., Minimizing test frequencies for linear analog circuits: new models and efficient solution methods, in VLSI-SoC: At the Crossroads of Emerging Trends, A. Orailoglu et al. (Eds.) , Ed. Springer , pp. 188-207, Vol. 461, DOI: 10.1007/978-3-319-23799-2 9, 2015
 
 2 Dubois M., Stratigopoulos H., Mir S., Barragan M., Statistical evaluation of digital techniques for Sigma-Delta ADC BIST, VLSI-SoC: Internet of Things Foundations, Luc Claesen, Maria-Teresa Sanz-Pascual, Ricardo Reis, Arturo Sarmiento-Reyes (Eds.) , Ed. Springer , pp. 129-148, DOI: 10.1007/978-3-319-25279-7 8, 2015
 
 3 Khereddine R., Abdallah L., Simeu E., Mir S., Cenni F., Adaptive logical control of RF LNA performances for efficient energy consumption, in VLSI-SoC: Forward-Looking Trends in IC and Systems Design , J. Ayala, D. Atienza, R. Reis (Eds.) , Ed. Springer , pp. 43-68, Volume 373, DOI: DOI: 10.1007/978-3-642-28566-0_3, 2012
 
 4 Bounceur A., Mir S., Rolindez L., Simeu E., CAT platform for analogue and mixed-signal test evaluation and optimization, in VLSI-SoC: Research trends in VLSI and Systems on Chip, G. De Micheli, S. Mir, R. Reis (Eds.) , Ed. Springer , pp. 281-300, Vol. 249, 2007
 
 5 Dhayni A., Mir S., Rufer L., Bounceur A., On-Chip pseudorandom testing for linear and non-linear MEMS, VLSI-SOC: From Systems to Silicon, Reis, Ricardo; Osseiran, Adam; Pfleiderer, Hans-Joerg (Eds.) , Ed. Springer , pp. 245-266, Vol. 240, DOI: DOI 10.1007/978-0-387-73661-7 , 2007
 
 6 Charlot B., Martinez S., Mir S., La CAO des microsystèmes, Conception de microsystèmes sur silicium, Ed. Hermès, pp. 129-176, 2002
 
 7 Mir S., Parrain F., Les interfaces microélectroniques, Conception de microsystèmes sur silicium , Mir S. (Eds.) , Ed. Hermès, pp. 177-215, 2002
 
 8 Mir S., Charlot B., Parrain F., Les microsystèmes thermiques, Dispositifs et physique des microsystèmes sur silicium , Mir S. (Eds.) , Ed. Hermès, pp. 65-104, 2002
 
 9 Mir S., Charlot B., Perspectives des microsystèmes sur silicium, Dispositifs et physique des microsystèmes sur silicium, Mir S. (Eds.) , Ed. Hermès, pp. 199-214, 2002
 
10 Mir S., Martinez S., Introduction aux microsystèmes sur silicium, Conception de microsystèmes sur silicium , Mir S. (Eds.) , Ed. Hermès, pp. 19-38, 2002
 
11 Mir S., Charlot B., From Microelectronics to Integrated Microsystems Testing, Microsystems Technology - Fabrication, test and reliability, J. Boussey (Eds.) , Ed. Lavoisier, pp. 241-263, 2002
 
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11 Livres & Éditions Ouvrages

 1 Mir S., Tsui C.-Y., Reis R., Choi C.-H. (Eds.) VLSI-SoC: Advanced Research for Systems on Chip, IFIP Advances in Information and Communication Technology , Vol. 379, pp. 187 p., Ed. Springer , 2012
 
 2 Mir S., Tsui C.-Y., Choi C.-H., Reis R. (Eds.) Proceedings of 19th IFIP International Conference on Very Large Scale Integration (VLSI-SoC), Hong-Kong, pp. 187 p., Ed. IFIP, 2011
 
 3 De Micheli G., Mir S., Reis R. (Eds.) VLSI-SoC: Research Trends in VLSI and Systems on Chip, IFIP Advances in Information and Communication Technology, Vol. 249, pp. 398 p., Ed. Springer , 2007
 
 4 Simeu E., Mir S., De Micheli G., Reis R. (Eds.) Digest of Papers PhD Forum at 14th IFIP International Conference on Very Large Scale Integration (VLSI-SoC), pp. 83 pages, Ed. IFIP, 2006
 
 5 Mir S., Richardson A., Cheng K.T. (Eds.) Guest Editorial: Mixed-Signal Testing, Journal of Electronic Testing : Theory and Applications, Vol. 22, No. 4-6, pp. 311, Ed. Springer , 2006
 
 6 Mir S., De Micheli G., Reis R., Simeu E. (Eds.) Proceedings 14th IFIP International Conference on Very Large Scale Integration (VLSI-SoC’06), pp. 416 p., Ed. IFIP, 2006
 
 7 Mir S. (Eds.) Proceedings 11th International Mixed-Signals Testing Workshop, Grenoble, France, pp. 358 pages, Ed. , 2005
 
 8 Kaminska B., Sunter S., Mir S. (Eds.) Guest Editorial: Analog and mixed signal test techniques for SOC development, Microelectronics Journal, Vol. 36, n°12, pp. 1063, Ed. Elsevier, 2005
 
 9 Kaminska B., Sunter S., Mir S. (Eds.) Proceedings 10th International Mixed-Signals Testing Workshop, Portland, USA, pp. 246 pages, Ed. , 2004
 
10 Mir S. (Eds.) Conception de microsystèmes sur silicium (Traité EGEM, série Electronique et micro-électronique), pp. 224 p., Ed. Hermès, 2002
 
11 Mir S. (Eds.) Dispositifs et physique des microsystèmes sur silicium (Traité EGEM, série Electronique et micro-électronique), pp. 224 p., Ed. Hermès, 2002
 
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2 Revues nationales

1 Mir S., Charlot B., From microelectronics to integrated microsystems testing , Nano et Micro-Technologies, Ed. Hermès, Vol. 2, No. 1-2, pp. 249-270, janvier 2002
 
2 Parrain F., Mir S., Charlot B., Courtois B., Capteur infrarouge CMOS à thermopiles comportant des fonctions de self-test, Nano et Micro-Technologies, Ed. Hermès, Vol. 1, No. 3-4, pp. 387-412, janvier 2001
 
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36 Conférences nationales

 1 Silveira Feitoza R., Barragan M., Dzahini D., Mir S., Static linearity test of SAR ADCs using an embedded incremental Σ∆ converter, Journées Nationales du Réseau Doctoral en Micro-nanoélectronique (JNRDM 2019), Montpellier, FRANCE, 3 au 5 juin 2019
 
 2 Malloug H., Barragan M., Mir S., Conception d’un générateur de signal sinusoïdal basé sur les techniques d’annulation d’harmonique en 28nm FDSOI, Journées GDR SoC-SiP, Paris, FRANCE, 13 au 15 juin 2018
 
 3 Cilici F., Barragan M., Lauga-Larroze E., Bourdel S., Mir S., Conception en vue du test d’un amplificateur de puissance à 60 GHz, Journées Nationales du Réseau Doctoral en Micro-nanoélectronique (JNRDM 2017), Strasbourg, FRANCE, 6 au 8 novembre 2017
 
 4 Bounceur A., Euler R., Beznia K., Mir S., Estimation des métriques de test analogique à base d’un échantillon multivarié de circuits extrêmes, Journées GDR SoC-SiP, Lyon, FRANCE, 11 au 12 juin 2013
 
 5 Beznia K., Bounceur A., Euler R., Mir S., Réduction des paramètres de sortie des circuits analogiques par l’estimation des métriques de test, Journées GDR SoC-SiP, Lyon, FRANCE, 11 au 12 juin 2013
 
 6 Beznia K., Bounceur A., Euler R., Mir S., Estimation des métriques de test analogique à base d’un échantillon multivarié de circuits extrêmes, 16ème Journées Nationales du Réseau Doctoral en Microélectronique (JNRDM'13), Grenoble, FRANCE, 10 juin 2013
 
 7 Fei R., Mir S., Moreau J., Défauts catastrophiques dans les capteurs optiques CMOS 1T75 PIN photodiode, Journées GDR ondes, Grenoble, FRANCE, 17 au 18 janvier 2013
 
 8 Saoud B., Beznia K., Bounceur A., Mir S., Kerkar M., Outil de modélisation statistique des circuits analogiques et mixtes, Journées GDR SoC-SiP, Paris, FRANCE, 13 au 15 juin 2012
 
 9 Beznia K., Bounceur A., Mir S., Euler R., Test metrics computation using the statistical model of analog circuits, Journées GDR SoC-SiP, Paris, FRANCE, 13 au 15 juin 2012
 
10 Abdallah L., Stratigopoulos H., Mir S., Conception et évaluation d’une technique de test pour un mélangeur RF, Journées GDR SoC-SiP, Lyon, FRANCE, 15 au 17 juin 2011
 
11 Huang K., Stratigopoulos H., Mir S., Diagnostic de fautes de circuits analogiques basé sur l’estimation non paramétrique de densité , Journées GDR SoC-SiP, Lyon, FRANCE, 15 au 17 juin 2011
 
12 Beznia K., Bounceur A., Mir S., Euler R., Evaluation d’un BIST d’un capteur de vision CMOS à base d’une copule non Gaussienne, Journées GDR SoC-SiP, Lyon, FRANCE, 15 au 17 juin 2011
 
13 Laraba A., Dubois M., Stratigopoulos H., Mir S., Evaluation de la technique de test basée sur la mesure d’un nombre réduit de codes pour les convertisseurs analogique-numérique de type pipeline, Journées Nationales du Réseau Doctoral en Microélectronique (JNRDM’11), Paris, FRANCE, 23 au 25 mai 2011
 
14 Abdallah L., Stratigopoulos H., Mir S., Moniteurs embarqués pour le test à bas coût d’un front-end RF, Journées Nationales du Réseau Doctoral en Microélectronique (JNRDM’11), Paris, FRANCE, 23 au 25 mai 2011
 
15 Abdallah L., Stratigopoulos H., Kelma C., Mir S., Capteurs embarqués pour le test alternatif des circuits RF, Journées GDR SoC-SiP, Paris, FRANCE, 9 au 11 juin 2010
 
16 Huang K., Stratigopoulos H., Mir S., Diagnostic de fautes de circuits analogiques basé sur l’apprentissage automatique, Journées GDR SoC-SiP, Paris, FRANCE, 9 au 11 juin 2010
 
17 Dubois M., Stratigopoulos H., Mir S., Evaluation des métriques de test pour des circuits analogiques/mixtes complexes, Journées GDR SoC-SiP, Paris, FRANCE, 9 au 11 juin 2010
 
18 Abdallah L., Tongbong J., Stratigopoulos H., Mir S., Alternate LNA testing using an envelope detector, Journées GDR SoC-SiP, Paris, FRANCE, 1 au 12 juin 2009
 
19 Arthaud Y., Rufer L., Mir S., Capteur MEMS faible impédance mécanique haute sensibilité pour la chirurgie de l’oreille moyenne, Journées GDR MNS, Montpellier, FRANCE, 3 au 5 décembre 2008
 
20 Schmerber S., Arthaud Y., Rufer L., Mir S., Outils de monitoring per-opératoire de la biomécanique ossiculaire par micro-capteur en chirurgie otologique - Etude de faisabilité, 115eme Congres de la SFORL, Paris, FRANCE, 12 au 14 octobre 2008
 
21 Dubois M., Chouba N., Mir S., Calibrage automatique d’un convertisseur Sigma-Delta utilisant un BIST, 11ème Journées Nationales du Réseau Doctoral en Microélectronique (JNRDM’08), Bordeaux, FRANCE, 14 au 16 mai 2008
 
22 Akkouche N., Mir S., Simeu E., Stratigopoulos H., Réduction de tests fonctionnels en utilisant des techniques d'estimation non paramétrique, 11ème Journées Nationales du Réseau Doctoral en Microélectronique (JNRDM’08), Bordeaux, FRANCE, 14 au 16 mai 2008
 
23 Khereddine R., Simeu E., Mir S., Utilisation des modèles de regression pour l’identification des paramètres d’un transceiver RF, 11ème Journées Nationales du Réseau Doctoral en Microélectronique (JNRDM’08), Bordeaux, FRANCE, 14 au 16 mai 2008
 
24 Rufer L., Arthaud Y., Mir S., Schmerber S., Dauvé S., Noury N., Outil de monitoring per-opératoire dans la chirurgie de l'oreille moyenne, Journées GDR MNS, Toulouse, FRANCE, 21 au 23 novembre 2007
 
25 Nguyen H.N., Rufer L., Simeu E., Mir S., RF MEMS series capacitive switch: test and diagnosis, Journées GDR SoC-SiP, Paris, FRANCE, 13 au 15 juin 2007
 
26 Khereddine R., Simeu E., Mir S., Utilisation des techniques de regression pour le test et le diagnostic des composantes RF , Journées GDR SoC-SiP, Paris, FRANCE, 13 juin 2007
 
27 Akkouche N., Bounceur A., Mir S., Réduction de tests fonctionnels par modélisation statistique des circuits analogiques, 10ème Journées Nationales du Réseau Doctoral en Microélectronique (JNRDM’07), Lille, FRANCE, 14 au 16 mai 2007
 
28 Rufer L., Domingues C., Mir S., Petrini V., Jeannot J.C., Delobelle P., Transducteur ultrasonore microusiné compatible CMOS, Ecole MEMS & Acoustique, Villeneuve d’Ascq, FRANCE, 3 au 4 avril 2007
 
29 Dhayni A., Mir S., Rufer L., Bounceur A., BIST pour les microsystèmes nonlinéaires, Journées Nationales du Réseau Doctoral de Microélectronique (JNRDM'06), Rennes, FRANCE, 10 au 12 mai 2006
 
30 Lizarraga L., Mir S., Sicard G., Vers une technique d’auto test incorporé (BIST) pour des pixels actifs CMOS, Journées Nationales du Réseau Doctoral en Microélectronique (JNRDM’06), Rennes, FRANCE, 10 au 12 mai 2006
 
31 Rufer L., Domingues C., Wong M., Dong J., Mir S., Electroacoustic and ultrasonic microtransducers, 8th French Acoustical Congress, pp. 487-490, Tours, FRANCE, 24 au 27 avril 2006
 
32 Kheriji R., Danelon V., Carbonero J.L., Mir S., Test orienté défaut pour les circuits radio fréquences, 14ème Journées Nationales Microondes (JNM’05), Nantes, FRANCE, 11 au 14 mai 2005
 
33 Dhayni A., Mir S., Rufer L., Bounceur A., Autotest Intégré des Microsystèmes Nonlinéaires, 8ème Journées Nationales du Réseau Doctoral de Microélectronique (JNRDM’05), pp. 256-258, Paris, FRANCE, 10 au 12 mai 2005
 
34 Bounceur A., Dhayni A., Mir S., Rufer L., Génération de vecteurs de test pour les MEMS non linéaires pour le calcul des noyaux de Volterra, 8ème Journées Nationales du Réseau Doctoral de Microélectronique (JNRDM’05), pp. 340-342, Paris, FRANCE, 10 au 12 mai 2005
 
35 Bounceur A., Mir S., Simeu E., Génération et optimisation de vecteurs de test pour des composants analogiques et mixtes, 7ème Journées Nationales du Réseau Doctoral de Microélectronique (JNRDM'04), pp. 198-200, Marseille, FRANCE, 4 au 6 mai 2004
 
36 Domingues C., Rufer L., Mir S., Modélisation et simulation d'un microsystème ultrasonore pour une application pulse-echo , 5ème Journées Nationales du Réseau Doctoral de Microélectronique (JNRDM'02), pp. 87-88, Grenoble, FRANCE, 23 au 25 avril 2002
 
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13 Autres communications

 1 Kriekouki I., Camirand Lemyre J., Rochette S., Rohrbacher C., Drouin D., Barragan M., Mir S., Galy P., Pioro-Ladrière M., UTBB FD-SOI Technology for Silicon-based Quantum Dots and Cryo-CMOS Electronics, Silicon Quantum Electronics Workshop (SIQEW'2019), San Sebastian, SPAIN, 2019
 
 2 Bentobache M., Bounceur A., Euler R., Kieffer Y., Mir S., Efficient minimization of test frequencies for linear analog circuits, 13th IEEE European Test Symposium (ETS'13), Avignon, FRANCE, 2013
 
 3 Stratigopoulos H., Mir S., Adaptive alternate analog test, IEEE International Test Workshop on Defect and Adaptive Test Analysis (DATA'12), Anaheim, CA, UNITED STATES, 2012
 
 4 Stratigopoulos H., Mir S., Tongbong J., A versatile technique for evaluating test measurements at the design stage, 15th IEEE International Mixed-Signals, Sensors and Systems Test Workhop (IMST3W'09), Phoenix, UNITED STATES, 2009
 
 5 Bounceur A., Mir S., Rolindez L., Simeu E., A CAT platform for analogue and mixed-signal test evaluation and optimization , Digest of Papers of the IEEE European Test Symposium (ETS’06), pp. 217-222, Southampton, UNITED KINGDOM, 2006
 
 6 Tongbong J., Bounceur A., Mir S., Carbonero J.L., Evaluation of test measures for low-cost LNA production testing, PhD Forum at 14th IFIP International Conference on Very Large Scale Integraation (VLSI-SoC’06), pp. 48-52, Nice, FRANCE, 2006
 
 7 Nguyen H.N., Simeu E., Rufer L., Mir S., Use of regressive method for RF MEMS test and diagnosis, PhD Forum at International Conference on Very Large Scale Integration (VLSI-Soc'06), pp. 56-61, Nice, FRANCE, 2006
 
 8 Rufer L., Simeu E., Mir S., Built-in self-test of linear time invariant systems using maximum-length sequences, Poster at IEEE European Test Workshop (ETW'03), pp. 111-112, Maastricht, NETHERLANDS, 2003
 
 9 Rufer L., Mir S., Analysis of acoustic capacitive transducers, 1st International Workshop on Microfabricated Ultrasonic Transducers, Rome, ITALY, 2001
 
10 Mir S., Rufer L., Thouraud B.-Z., Simo M., CMOS front-end for capacitive micromachined ultrasonic transducers, 1st International Workshop on Microfabricated Ultrasonic Transducers, Roma, ITALY, 2001
 
11 Rufer L., Mir S., Modelling of silicon electrostatic ultrasonic transducers, 1st International Workshop on Microfabricated Ultrasonic Transducers, Roma, ITALY, 2001
 
12 Charlot B., Mir S., Intégration de la conception et du test dans des puces avec dispositifs microsystème embarqués, Colloque CAO de circuits intégrés et systèmes, Aix-en-Provence, FRANCE, 1999
 
13 Mir S., Karam J.M., Courtois B., Technologies and fabrication processes for microsystems, Forum and exhibition on microtechnologies: from Microsystems to measurements of micro- and nano-mechanical properties of materials, Liège, BELGIUM, 1998
 
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37 Rapports

 1 Mir S., Rolindez L., Carbonero J.L., Design of a 96-dB Audio SD ADC including a BIST Technique for SNDR Testing , ISRN: TIMA-RR--06/10-02--FR, 1 janvier 2006
 
 2 Bounceur A., Simeu E., Mir S., Rolindez L., Estimation of test metrics for the optimisation of analogue circuit testing , ISRN: TIMA-RR--06/10-03--FR, 1 janvier 2006
 
 3 Dhayni A., Rufer L., Mir S., Bounceur A., On-chip Pseudorandom Testing for Linear and Nonlinear MEMS, ISRN: TIMA-RR--06/10-04--FR, 1 janvier 2006
 
 4 Simeu E., Mir S., Diagnosis in Linear and Nonlinear Mixed-Signal Systems: a Parameter Identification Based Technique, ISRN: TIMA-RR--05/06-01--FR, 1 janvier 2005
 
 5 Rolindez L., Prenat G., Bounceur A., Mir S., A 0.18 ìm CMOS Implementation of On-chip Analogue Test Signal Generation from Digital Test Patterns, ISRN: TIMA-RR--04/05-05--FR, 1 janvier 2004
 
 6 Mir S., Bounceur A., Rolindez L., Prenat G., A 0.18 ìm CMOS Implementation On-chip Analogue Test Signal Generation from Digital Test Patterns, ISRN: TIMA-RR--04/02-02--FR, 1 janvier 2004
 
 7 Prenat G., Vasquez D., Mir S., Rolindez L., A low-cost digital frequency testing approach for mixed-signal devices using sigma delta modulation , ISRN: TIMA-RR--04/05-03--FR, 1 janvier 2004
 
 8 Naal M. A., Mir S., Simeu E., Comparative Study of On-Line Testing Methods for AMS Systems. Application to Decimation Filters, ISRN: TIMA-RR--04/05-02--FR, 1 janvier 2004
 
 9 Mir S., Bounceur A., Simeu E., Génération et optimisation de vecteurs de test pour des composants analogiques et mixtes, ISRN: TIMA-RR--04/05-04--FR, 1 janvier 2004
 
10 Dhayni A., Mir S., Rufer L., MEMS Built-in-Self-Test Using MLS , ISRN: TIMA-RR--04/05-06--FR, 1 janvier 2004
 
11 Charlot B., Courtois B., Mir S., Rufer L., On-chip testing of embedded silicon transducers, ISRN: TIMA-RR--04/07-02--FR, 1 janvier 2004
 
12 Mir S., Rufer L., Courtois B., On-chip testing of embedded transducers, ISRN: TIMA-RR--04/05-07--FR, 1 janvier 2004
 
13 Simeu E., Mir S., Rufer L., Online Testing Embedded Systems: Adapting Automatic Control Techniques to Microelectronic Testing , ISRN: ISRN-RR--04/09-01-FR, 1 janvier 2004
 
14 Danelon V., Mir S., Kheriji R., Carbonero J.L., Optimising test sets for RF components with a defect-oriented approach, ISRN: TIMA-RR--05/02-01--FR, 1 janvier 2004
 
15 Simeu E., Rufer L., Mir S., Built-in-self -test of linear time invariant systems using maximum - lenght sequences, ISRN: TIMA-RR--03/07-02--FR, 1 janvier 2003
 
16 Mir S., Integrated circuits testing: from microelectronics to microsystems, ISRN: TIMA-RR--03/07-01--FR, 1 janvier 2003
 
17 Rufer L., Simeu E., Mir S., Domingues C., On-chip pseudorandom MEMS testing, ISRN: TIMA-RR--03/06-01--FR, 1 janvier 2003
 
18 Rufer L., Mir S., Simeu E., On-chip testing of linear time invariant systems using maximum-length sequences, ISRN: TIMA-RR--03/01-01--FR, 1 janvier 2003
 
19 Rufer L., Simeu E., Mir S., Domingues C., On-Chip testing of MEMS using pseudo-random test sequences, ISRN: TIMA-RR--03/03-02--FR, 1 janvier 2003
 
20 Naal M. A., Mir S., Simeu E., On-Line Testable Design: Application to Decimation Filter for AMS Systems, ISRN: TIMA-RR--03/08-01--FR, 1 janvier 2003
 
21 Mir S., Domingues C., Rolindez L., Rufer L., An implementation of memory-based on-chip analogue test signal generation, ISRN: TIMA-RR--02/11-02--FR, 1 janvier 2002
 
22 Domingues C., Rufer L., Mir S., Behavioural modelling and simulation of a MEMS-based ultrasonic pulse-echo system , ISRN: TIMA--RR-02/02/3--FR, 1 janvier 2002
 
23 Charlot B., Parrain F., Mir S., Courtois B., Generation of Electrically Induced Stimuli for MEMS self-test, ISRN: TIMA--RR-02/02/1--FR, 1 janvier 2002
 
24 Mir S., Roman C., Diedrich C., Domingues C., On-chip test signal generation for acoustic and ultrasound microelectronic interfaces, ISRN: TIMA-RR--02/09-01--FR, 1 janvier 2002
 
25 Parrain F., Mir S., Charlot B., Courtois B., Capteur infrarouge CMOS à thermopiles comportant des fonctions de self-test, ISRN: TIMA-RR--01/07-01--FR, 1 janvier 2001
 
26 Mir S., Rufer L., Thouraud B.-Z., Simo M., CMOS Front-end for Capacitive Micromachined Ultrasonic Transducers, ISRN: TIMA-RR--01/06-01--FR, 1 janvier 2001
 
27 Benedek Zs., Farkas G., Pohl L., Poppe A., Rencz M., Szekely V., Torki K., Mir S., Design of a muli-functional intelligent thermal test die, ISRN: TIMA-RR--01/03-01--FR, 1 janvier 2001
 
28 Charlot B., Mir S., Parrain F., Courtois B., Electrically Induced Stimuli For MEMS Self-Test, ISRN: TIMA-RR-01/02-01--FR, 1 janvier 2001
 
29 Mir S., Parrain F., Charlot B., Veychard D., Microbeams with electronically controlled high thermal impedance, ISRN: TIMA-RR--01/06-03--FR, 1 janvier 2001
 
30 Rufer L., Mir S., Modelling of Silicon Electrostatic Ultrasonic Transducers, ISRN: TIMA-RR--01/06-02--FR, 1 janvier 2001
 
31 Charlot B., Parrain F., Mir S., Courtois B., A Self-Testable CMOS Thermopile-Based Infrared Imager, ISRN: TIMA-RR-00/10-02--FR, 1 janvier 2000
 
32 Courtois B., Mir S., Charlot B., Lubaszewski M., From Microelectronics to MEMS Testing, ISRN: TIMA-RR-00/10-01--FR, 1 janvier 2000
 
33 Mir S., Charlot B., Nicolescu G., Coste P., Parrain F., Zergainoh N.-E., Courtois B., Jerraya A. A., Rencz M., Towards Design And Validation Of Mixed-Technology SOCs, ISRN: TIMA-RR--00/01-1--FR, 1 janvier 2000
 
34 Mir S., Courtois B., Charlot B., Extending fault­based testing to Microelectromechanical Systems, ISRN: TIMA-RR--99/05-1--FR, 1 janvier 1999
 
35 Mir S., Lubaszewski M., Charlot B., Cota E.F., Courtois B., Fault simulation of thermal MEMS, ISRN: TIMA-RR--99/05-2--FR, 1 janvier 1999
 
36 Charlot B., Mir S., Intégration de la conception et des methodologies de test pour le microsystèmes, ISRN: TIMA-RR--99/04-5--FR, 1 janvier 1999
 
37 Courtois B., Mir S., Karam J.M., Rencz M., Szekely V., Lubaszewski M., Multi-Purpose System-Level Simulation of MEMS, ISRN: TIMA-RR--99/01-1--FR, 1 janvier 1999
 
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1 Thèses

1 Mir S., Design and Integrated Test of Analogue, Mixed-Signal and Microsystems Devices, HDR, 18 mai 2005
 
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