Publications

Publications

Recherche

Recherche

Auteur
hors TIMA
Équipe :

Mot clé
Type de publications
Tous
Sélectionne/déselectionne tous les types de publications
Journal art.
International National Tous
 Brevets  Conférences invitées
Conference art.
International National Tous
Chapitres de livre  Livres & Éditions Ouvrages
 Autres communications
 Logiciels  Thèses
 
 année
 

259 résultats

   26 Revues internationales
   17 Conférences invitées
  167 Conférences internationales
    9 Chapitres de livre
    2 Livres & Éditions Ouvrages
    3 Revues nationales
   21 Conférences nationales
    7 Autres communications
    5 Rapports
    2 Logiciels

26 Revues internationales

 1 Roux J., Beroulle V., Morin-Allory K., Leveugle R., Bossuet L., Cezilly F., Berthoz F., Genevrier G., Cerisier F., High-level fault injection to assess FMEA on critical systems, Microelectronics Reliability, Ed. Elsevier, Vol. 122, pp. 114135, DOI: 10.1016/j.microrel.2021.114135, juillet 2021
 
 2 Dutertre J.M., Beroulle V., Candelier P., De Castro S., Faber L.-B., Flottes M.-L., Gendrier P., Hély D., Leveugle R., Maistri P., Di Natale G., Papadimitriou A., Sensitivity to Laser Fault Injection: CMOS FD-SOI vs. CMOS bulk (Early Access), IEEE Transactions on Device and Materials Reliability, Vol. , DOI: 10.1109/TDMR.2018.2886463, décembre 2018
 
 3 Leveugle R., Mkhinini A., Maistri P., Hardware Support for Security in the Internet of Things: From Lightweight Countermeasures to Accelerated Homomorphic Encryption, Information - Open Access Journal of Information Science, Ed. MDPI, Vol. 9, No. 5, pp. 114, DOI: 10.3390/info9050114, mai 2018
 
 4 Mkhinini A., Maistri P., Leveugle R., Tourki R., Co-designed accelerator for homomorphic encryption applications, Advances in Science, Technology and Engineering Systems Journal (ASTESJ), Vol. 3, No. 1, pp. 426-433, DOI: 10.25046/aj030152, février 2018
 
 5 Pontié S., Maistri P., Leveugle R., Dummy operations in scalar multiplication over elliptic curves: a tradeoff between security and performance, Microprocessors and Microsystems, Ed. Elsevier, Vol. 47, No. Part A, pp. 23-36, DOI: 10.1016/j.micpro.2016.02.016, novembre 2016
 
 6 Papadimitriou A., Hély D., Beroulle V., Maistri P., Leveugle R., Analysis of laser-induced errors: RTL fault models versus layout locality characteristics, Microprocessors and Microsystems, Ed. Elsevier, Vol. 47, No. Part A, pp. 64-73, DOI: 10.1016/j.micpro.2016.01.018, novembre 2016
 
 7 Houssany S., Guibbaud N., Bougerol A. , Leveugle R., Santini T., Miller F., Experimental assessment of cache memory soft error rate prediction technique, IEEE Transactions on Nuclear Science, Ed. IEEE, Vol. 60, No. 4, part 1, pp. 2734-2741, DOI: 10.1109/TNS.2013.2252626 , août 2013
 
 8 Alberto D., Maistri P., Leveugle R., Forecasting the effects of electromagnetic fault injections on embedded cryptosystems, Information Security Journal: A Global Perspective, Ed. Taylor & Francis group, Vol. 22, No. 5-6, pp. 237-243, DOI: 10.1080/19393555.2014.891278, mai-juin 2013
 
 9 Bergaoui S., Wecxsteen A., Leveugle R., Detailed analysis of compilation options for robust software-based embedded systems, Journal of Electronic Testing: Theory and Applications, Ed. Springer , Vol. 29, April, No. 2, pp. 211-222, DOI: 10.1007/s10836-013-5371-2, avril 2013
 
10 Houssany S., Guibbaud N., Bougerol A. , Leveugle R., Miller F., Buard N., Microprocessor Soft Error Rate Prediction Based on Cache Memory Analysis, IEEE Transactions on Nuclear Science, Ed. IEEE, Vol. 59, No. 4, Part 1, pp. 980-987, DOI: 10.1109/TNS.2012.2204775 , août 2012
 
11 Bougerol A. , Miller F., Guibbaud N., Leveugle R., Carriere T., Buard N., Experimental demonstration of pattern influence on DRAM SEU and SEFI radiation sensitivities, IEEE Transactions on Nuclear Science, Ed. IEEE, Vol. 58, part 2, No. 3, pp. 1032-1039, DOI: 10.1109/TNS.2011.2107528 , juin 2011
 
12 Canivet G., Maistri P., Leveugle R., Clédière J., Valette F., Renaudin M., Glitch and laser fault attacks onto a secure AES implementation on a SRAM-based FPGA, Journal of Cryptology, Ed. Springer , Vol. 24, No. 2, pp. 247-268, DOI: 10.1007/s00145-010-9083-9, avril 2011
 
13 Bergaoui S., Vanhauwaert P., Leveugle R., A new critical variable analysis in processor-based systems, IEEE Transactions on Nuclear Science, Ed. IEEE, Vol. 57, part 1, No. 4, pp. 1992-1999, DOI: 10.1109/TNS.2010.2043540 , août 2010
 
14 Maistri P., Leveugle R., Double-Data-Rate computation as a countermeasure against fault analysis, IEEE Transactions on Computers, Ed. IEEE, Vol. 57, No. 11, pp. 1528-1539, DOI: 10.1109/TC.2008.149 , novembre 2008
 
15 O'Connor I., Liu J., Gaffiot F., Pregaldiny F., Maneux C., Lallement C., Goguet J., Fregonese S., Zimmer T., Anghel L., Leveugle R., Dang T.T., CNTFET modeling and reconfigurable logic circuit design, IEEE Transactions on Circuits and Systems, Ed. IEEE, Vol. 54, No. 11, pp. 2365-2379, DOI: 10.1109/TCSI.2007.907835 , novembre 2007
 
16 Leveugle R., Early analysis of fault-based attack effects in secure circuits, IEEE Transactions on Computers, Ed. IEEE, Vol. 56, No. 10, pp. 1431-1434, DOI: 10.1109/TC.2007.1078, octobre 2007
 
17 Maingot V., Ferron J.B., Leveugle R., Pouget V., Douin A., Configuration errors analysis in SRAM-based FPGAs: software tool and practical results , Microelectronics Reliability, Ed. Elsevier, Vol. 47, No. 9-11, pp. 1836-1840, DOI: 10.1016/j.microrel.2007.07.074 , septembre-novembre 2007
 
18 Monnet Y., Renaudin M., Leveugle R., Designing Resistant Circuits against Malicious Faults Injection Using Asynchronous Logic, IEEE Transactions on Computers, Ed. IEEE, Vol. 55, No. 9, pp. 1104 - 1115, DOI: 10.1109/TC.2006.143, septembre 2006
 
19 Portolan M., Leveugle R., A highly flexible hardened RTL processor core based on LEON2, IEEE Transactions on Nuclear Science, Ed. IEEE, Vol. 53, Part 1, No. 4, pp. 2069 - 2075, DOI: 10.1109/TNS.2006.876508, août 2006
 
20 Ammari A., Hadjiat K., Leveugle R., Combined Fault Classification and Error Propagation Analysis to Refine RT-Level Dependability Evaluation, Journal of Electronic Testing: Theory and Applications, Ed. Springer , Vol. 21, No. 4, pp. 365 - 376, DOI: 10.1007/s10836-005-0974-x, août 2005
 
21 Leveugle R., Hadjiat K., Multi-level fault injections in VHDL descriptions: alternative approaches and experiments, Journal of Electronic Testing: Theory and Applications, Ed. Springer , Vol. 19, No. 5, pp. 559-75, DOI: 10.1023/A:1025178014797, octobre 2003
 
22 Antoni L., Leveugle R., Feher B., Using run-time reconfiguration for fault injection applications, IEEE Transactions on Instrumentation and Measurement, Ed. IEEE, Vol. 52, No. 5, pp. 1468-73, DOI: 10.1109/TIM.2003.817144, octobre 2003
 
23 Leveugle R., Ubar R., Synthesis of decision diagrams from clock-driven multi-process VHDL descriptions for test generation, Electron Technology, Vol. 32, No. 3, pp. 282-287, 1999
 
24 Rochet R., Leveugle R., Saucier G., ASYL-SdF: a synthesis tool for dependability in controllers, IEICE Transactions on Information and Systems, Vol. E79-D, No. 10, pp. 1382-1388, octobre 1996
 
25 Leveugle R., Koren Z., Koren I., Saucier G., Wehn N., The Hyeti defect tolerant microprocessor: a practical experiment and its cost-effectiveness analysis, IEEE Transactions on Computers, Ed. IEEE, Vol. 43, No. 12, pp. 1398-1406, DOI: 10.1109/12.338099, décembre 1994
 
26 Leveugle R., Saucier G., Optimized synthesis of concurrently checked controllers, IEEE Transactions on Computers, Ed. IEEE, Vol. 39, No. 4, pp. 419-25, DOI: 10.1109/12.54835, avril 1990
 
remonter

17 Conférences invitées

 1 Maistri P., Reynaud V., Portolan M., Leveugle R., Secure Test with RSNs: Seamless Authenticated Extended Confidentiality, Invited paper, 19th IEEE International New Circuits and Systems Conference (NEWCAS 2021), Toulon, FRANCE, DOI: 10.1109/NEWCAS50681.2021.9462778, 13 au 16 juin 2021
 
 2 Di Natale G., Kooli M., Bosio A., Portolan M., Leveugle R., Reliability of computing systems: from flip flops to variables, Invited talk (Special Session), 23rd IEEE International Symposium on On-Line Testing and Robust System Design (IOLTS 2017), Thessaloniki, GREECE, DOI: 10.1109/IOLTS.2017.8046242, 3 au 5 juillet 2017
 
 3 Leveugle R., New approaches towards early dependability evaluation of digital integrated systems, Invited Tutorial, 11th IEEE International Design & Test Symposium (IDT'16), Hammamet, TUNISIA, 18 au 20 décembre 2016
 
 4 Leveugle R., DFT vs. Security - Is it a Contradiction? How Can We Get the Best of Both Worlds?, Invited Talk, 1st IEEE International Verification and Security Workshop, St Feliu de Guixols, SPAIN, 4 au 6 juillet 2016
 
 5 Vanhauwaert P., Maistri P., Leveugle R., Papadimitriou A., Hély D., Beroulle V., On error models for RTL security evaluations, 9th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS'14), pp. 115-120, Santorini, GREECE, DOI: 10.1109/DTIS.2014.6850666, 6 au 7 mai 2014
 
 6 Leveugle R., Taking care of security in hardware design, Invited Tutorial, The Fourth International Conference on Dependability (DEPEND'11), Nice, FRANCE, 21 au 27 août 2011
 
 7 Leveugle R., Natural and malicious soft errors: dependability and security issues in reconfigurable platforms, Embedded tutorial, 6th International Workshop on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC'11), Montpellier, FRANCE, 20 au 22 juin 2011
 
 8 Anghel L., Ferron J.B., Leveugle R., Criticality of Configuration Bits in SRAM-based FPGAs: Predictive Analysis and Experimental Results, Workshop on Design for Reliability and Variability (DRVW’11), Dana Point, CA, UNITED STATES, 4 au 5 mai 2011
 
 9 Leveugle R., Early robustness evaluation of digital integrated systems, 13th Forum for Design Languages (FDL'10), Southampton, UNITED KINGDOM, 14 au 16 septembre 2010
 
10 Leveugle R., Integrated systems security: hardware-based threats and solutions, Embedded tutorial, 1st IEEE Latin American Symposium on Circuits and Systems (LASCAS'10), Iguassu, BRAZIL, 24 au 26 février 2010
 
11 Leveugle R., Integrated and embedded systems security: hardware-based threats and solutions, Invited Tutorial, 2nd International Conference on Signals, Circuits & Systems (SCS'09), Djerba, TUNISIA, 6 au 8 novembre 2009
 
12 Di Natale G., Flottes M.-L., Rouzeyre B., Maistri P., Leveugle R., Ensuring High Testability without Degrading Security, Embedded tutorial, European Test Symposium (ETS’09), Sevilla, SPAIN, 25 au 29 mai 2009
 
13 Leveugle R., Chip level security: Why ? How ?, Invited Tutorial, IEEE International Conference on Electronics, Circuits and Systems (ICECS'08), Saint Julians, MALTA, 31 août au 3 septembre 2008
 
14 Leveugle R., Dependability issues in SRAM-based FPGA design, Invited Tutorial, IEEE International Conference on Electronics, Circuits and Systems (ICECS'07), Marrakech, MOROCCO, 11 au 14 décembre 2007
 
15 Leveugle R., Design and validation of dependable integrated systems, Invited Tutorial, IEEE International Conference on Electronics, Circuits and Systems (ICECS'06), Nice, FRANCE, 10 au 13 décembre 2006
 
16 Leveugle R., Design & Test of Integrated Systems in Nanoscale Technology, Invited Tutorial, IEEE International Conference on Design and Test of Integrated Systems in Nanoscale Technology (DTIS'06), Tunis, TUNISIA, 5 au 7 septembre 2006
 
17 Anghel L., Leveugle R., Vanhauwaert P., Evaluation of SET and SEU effects at multiple abstraction levels, 11th IEEE International On Line Testing Symposium (IOLTS'05), pp. 309-12, St Raphael, FRANCE, DOI: 10.1109/IOLTS.2005.28, 6 au 8 juillet 2005
 
remonter

167 Conférences internationales

  1 Roux J., Beroulle V., Morin-Allory K., Leveugle R., Bossuet L., Cezilly F., Berthoz F., Genevrier G., Cerisier F., High Level Fault Injection Method for Evaluating Critical System Parameter Ranges, 27th IEEE International Conference on Electronics, Circuits and Systems (ICECS 2020), pp. 1-4, Glasgow, UNITED KINGDOM, DOI: 10.1109/ICECS49266.2020.9294821, 23 au 25 novembre 2020
 
  2 Portolan M., Silveira Feitoza R., Takam Tchendjou G., Reynaud V., Senthamarai Kannan K., Barragan M., Simeu E., Maistri P., Anghel L., Leveugle R., Mir S., A Comprehensive End-to-end Solution for a Secure and Dynamic Mixed-signal 1687 System, 2020 International Symposium on On-Line Testing and Robust System Design (IOLTS 2020), Naples (Napoli), ITALY, DOI: 10.1109/IOLTS50870.2020.9159721, 13 au 15 juillet 2020
 
  3 Portolan M., Reynaud V., Maistri P., Leveugle R., Dynamic Authentication-Based Secure Access to Test Infrastructure, European Test Symposium (ETS 2020), Tallin, ESTONIA, 25 mai au 1 juin 2020
 
  4 Roux J., Beroulle V., Morin-Allory K., Leveugle R., Bossuet L., Cezilly F., Berthoz F., Genevrier G., Cerisier F., Cross Layer Fault Simulations for Analyzing the Robustness of RTL Designs in Airborne Systems, 23rd International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS 2020), pp. 1-4, Novi Sad, SERBIE, DOI: 10.1109/DDECS50862.2020.9095559, 22 au 24 avril 2020
 
  5 Merandat M., Reynaud V., Valea E., Quévremont J., Maistri P., Leveugle R., Flottes M.-L., Dupuis S., Rouzeyre B., Di Natale G., A Comprehensive Approach to a Trusted Test Infrastructure, 4th International Verification and Security Workshop (IVSW 2019), Rhodes Island, GREECE, 1 au 3 juillet 2019
 
  6 Portolan M., Savino A., Leveugle R., Di Carlo S., Bosio A., Di Natale G., Alternatives to fault injections for early safety/security evaluations, 24th IEEE European Test Symposium (ETS 2019), Baden Baden, GERMANY, 27 au 31 mai 2019
 
  7 Savino A., Portolan M., Leveugle R., Di Carlo S., Approximate computing design exploration through data lifetime metrics, 24th IEEE European Test Symposium (ETS 2019), Baden Baden, GERMANY, 27 au 31 mai 2019
 
  8 Savino A., Portolan M., Di Carlo S., Leveugle R., Targeting approximation through data lifetime: a quest for optimization metrics, 4th Approximate Computing Workshop (AxC 2019), Florence, ITALY, 29 mars 2019
 
  9 Dutertre J.M., Beroulle V., Candelier P., De Castro S., Faber L.-B., Flottes M.-L., Gendrier P., Hély D., Leveugle R., Maistri P., Di Natale G., Papadimitriou A., Rouzeyre B., Laser Fault Injection at the CMOS 28 nm Technology Node: an Analysis of the Fault Model, Fourteenth Workshop on Fault Diagnosis and Tolerance in Cryptography (FDTC'2018), Amsterdam, NETHERLANDS, 13 septembre 2018
 
 10 Dutertre J.M., Beroulle V., Candelier P., De Castro S., Faber L.-B., Flottes M.-L., Gendrier P., Hély D., Leveugle R., Maistri P., Di Natale G., Papadimitriou A., Rouzeyre B., The case of using CMOS FD-SOI rather than CMOS bulk to harden ICs against laser attacks, 24th IEEE International Symposium on On-Line Testing and Robust System Design (IOLTS'2018), Platja d'Aro, SPAIN, 2 au 4 juillet 2018
 
 11 Mkhinini A., Maistri P., Leveugle R., Tourki R., HLS Design of a Hardware Accelerator for Homomorphic Encryption, IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS 2017), Dresden, GERMANY, DOI: 10.1109/DDECS.2017.7934578, 19 au 21 avril 2017
 
 12 Mkhinini A., Maistri P., Leveugle R., Tourki R., Machhout M., A flexible RNS-based large polynomial multiplier for Fully Homomorphic Encryption, 11th IEEE International Design & Test Symposium (IDT'16), pp. 131-136, Hammamet, TUNISIA, 18 au 20 décembre 2016
 
 13 Terras L., Teglia Y., Agoyan M., Leveugle R., Taking into account indirect jumps or calls in continuous Control-Flow Checking, 11th IEEE International Design & Test Symposium (IDT'16), pp. 125-130, Hammamet, TUNISIA, 18 au 20 décembre 2016
 
 14 Chibani K., Portolan M., Leveugle R., Application-aware soft error sensitivity evaluation without fault injections - Application to Leon3, European Conference on Radiation and its Effects on Components and Systems (RADECS'16), Bremen, GERMANY, 19 au 23 septembre 2016
 
 15 Pontié S., Bourge A., Prost-Boucle A., Maistri P., Muller O., Leveugle R., Rousseau F., HLS-based methodology for fast iterative development applied to Elliptic Curve arithmetic, Euromicro/IEEE Conference on Digital System Design (DSD'16), pp. 511-518, Limassol, CYPRUS, DOI: 10.1109/DSD.2016.51, 31 août au 2 septembre 2016
 
 16 Chibani K., Portolan M., Leveugle R., Evaluating Application-Aware Soft Error Effects in Digital Circuits Without Fault Injections or Probabilistic Computations, 22nd IEEE International Symposium on On-Line Testing and Robust System Design (IOLTS'16), pp. 54-59, St Feliu de Guixols, SPAIN, 4 au 6 juillet 2016
 
 17 Leveugle R., Chahed A., Maistri P., Papadimitriou A., Hély D., Beroulle V., Ammari A., On Fault Injections for Early Security Evaluation vs. Laser-based Attacks, 1st IEEE International Verification and Security Workshop, pp. 33-38, St Feliu de Guixols, SPAIN, 4 au 6 juillet 2016
 
 18 Backenstrass T., Blot M., Pontié S., Leveugle R., Protection of ECC Computations against Side-Channel Attacks for Lightweight Implementations, 1st IEEE International Verification and Security Workshop, pp. 2-7, St Feliu de Guixols, SPAIN, 4 au 6 juillet 2016
 
 19 Ananiadis C., Papadimitriou A., Hély D., Beroulle V., Maistri P., Leveugle R., On the development of a new countermeasure on a laser attack RTL fault model, Design, Automation and Test in Europe Conference (DATE'16), Dresden, GERMANY, 14 au 18 mars 2016
 
 20 Jayet-Griffon C., Cornelie M.-A., Maistri P., Elbaz-Vincent P., Leveugle R., Polynomial multipliers for Fully Homomorphic Encryption on FPGA, International Conference on ReConFigurable Computing and FPGAs (ReConFig'15), Mayan Riviera, MEXICO, 7 au 9 décembre 2015
 
 21 Papadimitriou A., Tampas M., Hély D., Beroulle V., Maistri P., Leveugle R., Validation of RTL laser fault injection model with respect to layout information, IEEE International Symposium on Hardware Oriented Security and Trust (HOST'15), pp. 78-81, McLean, VA, UNITED STATES, 5 au 7 mai 2015
 
 22 Papadimitriou A., Hély D., Beroulle V., Maistri P., Leveugle R., Analysis of laser-induced errors: RTL fault model versus layout locality characteristics, Third Workshop on Trustworthy Manufacturing and Utilization of Secure Devices (TRUDEVICE'15), Grenoble, FRANCE, 13 mars 2015
 
 23 Pontié S., Maistri P., Leveugle R., Tuning of randomized windows against simple power analysis for scalar multiplication on elliptic curves, Third Workshop on Trustworthy Manufacturing and Utilization of Secure Devices (TRUDEVICE'15), Grenoble, FRANCE, 13 mars 2015
 
 24 Chibani K., Bergaoui S., Portolan M., Leveugle R., Criticality evaluation of embedded software running on a pipelined microprocessor and impact of compilation options, IEEE International Conference on Electronics, Circuits and Systems (ICECS), pp. 778-781, Marseille, FRANCE, 7 au 10 décembre 2014
 
 25 Maistri P., Leveugle R., Bossuet L., Aubert A., Fischer V., Robisson B., Moro N., Maurine P., Dutertre J.M., Lisart M., Electromagnetic analysis and fault injection onto secure circuits, 22nd IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC'14), pp. 195-200, Playa del Carmen, MEXICO, DOI: 10.1109/VLSI-SoC.2014.7004182, 5 au 8 octobre 2014
 
 26 Chibani K., Ben Jrad M., Portolan M., Leveugle R., Fast accurate evaluation of register lifetime and criticality in a pipelined microprocessor, 22nd IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC'14), pp. 260-265, Playa del Carmen, MEXICO, DOI: 10.1109/VLSI-SoC.2014.7004158, 5 au 8 octobre 2014
 
 27 Leveugle R., Maistri P., Vanhauwaert P., Lu F., Di Natale G., Flottes M.-L., Rouzeyre B., Papadimitriou A., Hély D., Beroulle V., Hubert G., De Castro S., Dutertre J.M., Sarafianos A., Boher N., Lisart M., Damiens J., Candelier P., Tavernier C., Laser-induced fault effects in security-dedicated circuit, 22nd IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC'14), pp. 201-206, Playa del Carmen , MEXICO, DOI: 10.1109/VLSI-SoC.2014.7004184 , 5 au 8 octobre 2014
 
 28 Pontié S., Maistri P., Leveugle R., An Elliptic Curve Crypto-Processor Secured by Randomized Windows, Digital System Design (DSD), 2014 17th Euromicro Conference on, pp. 535 - 542, Verona, ITALY, DOI: 10.1109/DSD.2014.18, 27 au 28 août 2014
 
 29 Chibani K., Portolan M., Leveugle R., Fast register criticality evaluation in a SPARC microprocessor, 10th Conference on Ph.D Research in Microelectronics and Electronics (PRIME'14), pp. 1-4, Grenoble, FRANCE, DOI: 10.1109/PRIME.2014.6872674, 30 juin au 3 juillet 2014
 
 30 Alberto D., Maistri P., Leveugle R., Electromagnetic attacks on embedded devices: a model of probe-circuit power coupling, 9th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS'14), pp. 23-28 , Santorini, GREECE, DOI: 10.1109/DTIS.2014.6850648, 6 au 8 mai 2014
 
 31 Papadimitriou A., Hély D., Beroulle V., Maistri P., Leveugle R., A multiple fault injection methodology based on cone partitioning towards RTL modeling of laser attacks, Design, Automation and Test in Europe Conference (DATE'14) Germany, Dresden, GERMANY, DOI: 10.7873/DATE2014.219, 24 mars 2014
 
 32 Bergaoui S., Vanhauwaert P., Leveugle R., IDSM: an improved disjoint signature monitoring scheme for processor behavioral checking, 15th Latin-American Test Workshop (LATW'14), pp. 1-6, Fortaleza, BRAZIL, 12 au 15 mars 2014
 
 33 Ben Jrad M., Leveugle R., Automated design flow for no-cost configuration error detection in SRAM-based FPGAs, International Conference on ReConFigurable Computing and FPGAs (ReConFig'13), pp. 1-6, Cancun, MEXICO, DOI: 10.1109/ReConFig.2013.6732272, 9 au 11 décembre 2013
 
 34 Maistri P., Tiran S., Maurine P., Koren I., Leveugle R., Countermeasures against EM analysis for a secured FPGA-based AES implementation, International Conference on ReConFigurable Computing and FPGAs (ReConFig'13), pp. 1-6, Cancun, MEXICO, DOI: 10.1109/ReConFig.2013.6732274, 9 au 11 décembre 2013
 
 35 Leveugle R., Ben Jrad M., On improving at no cost the quality of products built with SRAM-based FPGAs, 5th Asia Symposium on Quality Electronic Design (ASQED'13), pp. 295-301, Penang, MALAYSIA, 26 au 28 août 2013
 
 36 Ben Jrad M., Leveugle R., Evaluating a low cost robustness improvement in SRAM-based FPGAs, IEEE International On-Line Testing symposium (IOLTS'13), pp. 173-174, Chania, CRETE, DOI: 10.1109/IOLTS.2013.6604072, 8 au 10 juillet 2013
 
 37 Maistri P., Tiran S., Maurine P., Koren I., Leveugle R., An evaluation of an AES implementation protected against EM analysis, 23rd ACM international conference on Great lakes symposium on VLSI (GLSVLSI'13), pp. 317-318 , Paris, FRANCE, DOI: 10.1145/2483028.2483120, 2 au 3 mai 2013
 
 38 Ben Jrad M., Leveugle R., Comparison of FPGA platforms for emulation-based fault injections using run-time reconfiguration, Conference on Design of Circuits and Integrated Systems (DCIS'12), pp. 184-188, Avignon, FRANCE, 28 au 30 novembre 2012
 
 39 Houssany S., Guibbaud N., Bougerol A. , Leveugle R., Miller F., Experimental Assessment of Cache Memory Soft Error Rate Prediction Technique, European Conference on Radiation and its Effects on Components and Systems (RADECS'12), Biarritz, FRANCE, 24 au 28 septembre 2012
 
 40 Wecxsteen A., Bergaoui S., Leveugle R., Detailed analysis of compilation options for robust software-based embedded systems, 13th Latin-American Test Workshop (LATW'12), pp. 188-193, Quito, ECUADOR, DOI: 10.1109/LATW.2012.6261261, 11 au 13 avril 2012
 
 41 Ben Jrad M., Leveugle R., Pattern-based injections in processors implemented on SRAM-based FPGAs, 13th Latin-American Test Workshop (LATW'12), pp. 200-203 , Quito, ECUADOR, DOI: 10.1109/LATW.2012.6261263, 11 au 13 avril 2012
 
 42 Ferron J.B., Anghel L., Leveugle R., Towards Low-cost Soft Error Mitigation in SRAM-based FPGAs: a Case Study on AT40K, 3rd IEEE Latin American Symposium on Circuits and Systems (LASCAS'12), Playa del Carmen, MEXICO, 29 février au 2 mars 2012
 
 43 Ferron J.B., Anghel L., Leveugle R., Analysis of configuration bit criticality in designs implemented with SRAM-based FPGAs, IEEE Symposium on Industrial Electronics & Applications (ISIEA('12), pp. 83-88 , Langkawi, MALAYSIA, 25 au 28 septembre 2011
 
 44 Maistri P., Masson F., Leveugle R., Implementation of the Advanced Encryption Standard on GPUs with the NVIDIA CUDA framework, IEEE Symposium on Industrial Electronics & Applications (ISIEA'11), pp. 213-217 , Langkawi, MALAYSIA, 25 au 28 septembre 2011
 
 45 Houssany S., Guibbaud N., Bougerol A. , Leveugle R., Miller F., Buard N., Microprocessor soft error rate prediction based on cache memory analysis, 12th European Conference on Radiation and its Effects on Components and Systems (RADECS'11), Sevilla, SPAIN, 19 au 23 septembre 2011
 
 46 Maistri P., Leveugle R., 10-gigabit throughput and low area for a hardware implementation of the Advanced Encryption Standard, 14th Euromicro/IEEE Conference on Digital System Design (DSD'11), pp. 266-269, Oulu, FINLAND, DOI: 10.1109/DSD.2011.37 , 31 août au 2 septembre 2011
 
 47 Clavel R., Pierre L., Leveugle R., Towards Robustness Analysis using PVS, Conference on Interactive Theorem Proving (ITP’11), pp. 71-86, Nijmegen, NETHERLANDS, DOI: 10.1007/978-3-642-22863-6_8, 22 au 25 août 2011
 
 48 Leveugle R., Ben Jrad M., Maistri P., Towards Virtual Fault-based Attacks for Security Validation, IARIA Fourth International Conference on Dependability (DEPEND'11), pp. 1-6, Nice, FRANCE, 21 au 27 août 2011
 
 49 Bergaoui S., Leveugle R., Impact of software optimization on variable lifetimes in a microprocessor-based system, IEEE International Symposium on Electronic Design, Test and Applications (DELTA'11), pp. 56-61, Queenstown, NEW ZEALAND, 17 au 19 janvier 2011
 
 50 Leveugle R., Ben Jrad M., A new methodology for accurate predictive robustness analysis of designs implemented in SRAM-based FPGAs, IEEE International Conference on Electronics, Circuits and Systems (ICECS), pp. 1179-1182 , Athens, GREECE, 12 au 15 décembre 2010
 
 51 Bougerol A. , Miller F., Guibbaud N., Leveugle R., Carriere T., Buard N., Experimental demonstration of pattern influence on DRAM SEU & SEFI radiation sensitivities, European Conference on Radiation and its Effects on Components and Systems (RADECS'10), Längelfeld, AUSTRIA, 20 au 24 septembre 2010
 
 52 Canivet G., Maistri P., Leveugle R., Valette F., Clédière J., Renaudin M., Dependability analysis of a countermeasure against fault attacks by means of laser shots onto a SRAM-based FPGA, International Conference on Application-specific Systems, Architectures and Processors (ASAP'10), pp. 115-122, Rennes, FRANCE, 7 au 9 juillet 2010
 
 53 Canivet G., Maistri P., Leveugle R., Valette F., Clédière J., Renaudin M., Robustness evaluation and improvements under laser-based fault attacks of an AES crypto-processor implemented on a SRAM-based FPGA, IEEE European Test Symposium (ETS'10), pp. 251, Prague, CZECH REPUBLIC, DOI: 10.1109/ETSYM.2010.5512740 , 24 au 28 mai 2010
 
 54 Leveugle R., Prost-Boucle A., A new automated instrumentation for emulation-based fault injection, 1st IEEE Latin American Symposium on Circuits and Systems (LASCAS'10), pp. 220-223, Iguaçu Falls, BRAZIL, 24 au 26 février 2010
 
 55 Bergaoui S., Leveugle R., Impact of compilation options on the criticality of registers in a microprocessor-based system, 1st IEEE Latin American Symposium on Circuits and Systems (LASCAS'10), pp. 216-219, Iguaçu Falls, BRAZIL, 24 au 26 février 2010
 
 56 Bergaoui S., Leveugle R., IDSM: An improved control flow checking approach with disjoint signature monitoring, Conference on Design of Circuits and Integrated Systems (DCIS'09), pp. 249-254, Zaragoza, SPAIN, 18 au 20 novembre 2009
 
 57 Ferron J.B., Anghel L., Leveugle R., Bocquillon A., Miller F., Mantelet G., A methodology and tool for predictive analysis of configuration bit criticality in SRAM-based FPGAs: experimental results, 3rd International Conference on Signals, Circuits & Systems (SCS'09), Djerba, TUNISIA, 6 au 8 novembre 2009
 
 58 Maingot V., Leveugle R., Influence of error detecting or correcting codes on the sensitivity to DPA of an AES S-Box, International Conference on Signals, Circuits & Systems (SCS'09), Djerba, TUNISIA, 6 au 8 novembre 2009
 
 59 Baarir S., Braunstein C., Clavel R., Encrenaz E., Ilié J.-M., Leveugle R., Mounier I., Pierre L., Poitrenaud D., Complementary formal approaches for dependability analysis, International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'09), pp. 331-339, Chicago, Illinois, UNITED STATES, DOI: 10.1109/DFT.2009.21, 7 au 9 octobre 2009
 
 60 Bergaoui S., Vanhauwaert P., Leveugle R., A new critical variable analysis in processor-based systems, European Conference on Radiation Effects on Components and Systems (RADECS'09), Bruges, BELGIUM, 14 au 18 septembre 2009
 
 61 Maistri P., Leveugle R., Toward automated fault pruning with Petri nets, International on-line Testing Symposium (IOLTS’09), pp. 41-46, Sesimbra-Lisbon, PORTUGAL, DOI: 10.1109/IOLTS.2009.5195981, 24 au 26 juin 2009
 
 62 Pierre L., Clavel R., Leveugle R., ACL2 for the Verification of Fault-Tolerance Properties: First Results, International Workshop on The ACL2 Theorem Prover and Its Applications, pp. 90-99, Boston, MA., UNITED STATES, 11 au 12 mai 2009
 
 63 Canivet G., Leveugle R., Clédière J., Valette F., Renaudin M., Characterization of effective laser spots during attacks in the configuration of a Virtex-II FPGA, IEEE VLSI Test Symposium (VTS'09), pp. 327-332, Santa Cruz, California, UNITED STATES, 3 au 7 mai 2009
 
 64 Leveugle R., Calvez A., Maistri P., Vanhauwaert P., Statistical Fault Injection: Quantified Error and Confidence , Design, Automation and Test in Europe (DATE '09), pp. 502-506 , Nice, FRANCE, 20 au 24 avril 2009
 
 65 Vanhauwaert P., Leveugle R., Efficiency of probabilistic testability analysis for soft error effect analysis: a case study, International conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS’09), pp. 236-240, Cairo, EGYPT, 6 au 7 avril 2009
 
 66 Leveugle R., Calvez A., Vanhauwaert P., Maistri P., Precisely Controlling the Duration of Fault Injection Campaigns: a Statistical View , International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS’09), pp. 149-154 , Cairo, EGYPT, 6 au 7 avril 2009
 
 67 Leveugle R., Pierre L., Maistri P., Clavel R., Soft Error Effect and Register Criticality Evaluations: Past, Present and Future, Workshop on Silicon Errors in Logic - System Effects (SELSE’09), pp. 15-20 , Stanford, Ca., UNITED STATES, 24 au 25 mars 2009
 
 68 Leveugle R., Calvez A., Vanhauwaert P., Maistri P., Statistical fault injection: how much is sufficient?, 2nd IFIP International Workshop on Dependable Circuit Design (DECIDE'08), Playa del Carmen, MEXICO, 27 au 29 novembre 2008
 
 69 Canivet G., Clédière J., Valette F., Renaudin M., Leveugle R., Intentional Attacks on SRAM-based FPGAs, 23rd International Conference on Design of Circuits and Integrated Systems (DCIS’08), Grenoble, FRANCE, 12 au 14 novembre 2008
 
 70 Maistri P., Excoffon C., Leveugle R., Software BIST capabilities of a symmetric cipher, International Conference on Electronics, Circuits and Systems (ICECS'08), pp. 414-417, Saint Julians, MALTA, 1 au 3 septembre 2008
 
 71 Vanhauwaert P., Portolan M., Leveugle R., Roche P., Usefulness and effectiveness of HW and SW protection mechanisms in a processor-based system, IEEE International Conference on Electronics, Circuits and Systems (ICECS'08)), pp. 113-116 , Saint Julians, MALTA, 1 au 3 septembre 2008
 
 72 Canivet G., Clédière J., Ferron J.B., Valette F., Renaudin M., Leveugle R., Detailed analyses of single laser shot effects in the configuration of a Virtex-II FPGA, 14th IEEE International On-Line Testing symposium (IOLT'08), pp. 289-294 , Rhodes, GREECE, DOI: 10.1109/IOLTS.2008.41, 6 au 9 juillet 2008
 
 73 Maistri P., Excoffon C., Leveugle R., Software self-testing of a symmetric cipher with error detection capability, 14th IEEE International On-Line Testing Symposium (IOLTS'08), pp. 79-84, Rhodes, GREECE, DOI: 10.1109/IOLTS.2008.33, 6 au 9 juillet 2008
 
 74 Excoffon C., Maistri P., Leveugle R., Software-based BIST capabilities of the Advanced Encryption Standard, Electronic Symposium Digest of 13th IEEE European Test Symposium (ETS'08), Verbania, ITALY, 25 au 29 mai 2008
 
 75 Maingot V., Leveugle R., Analysis of Laser-Based Attack Effects on a Synchronous Circuit, International Design and Test Workshop (IDT’07), pp. 99-104, Cairo, EGYPT, 16 au 18 décembre 2007
 
 76 Dang T.T., Anghel L., Pasca V., Leveugle R., CNTFET-based CMOS-like gates and dispersion of characteristics, International Design and Test Workshop (IDT’07), pp. 151-156, Cairo, EGYPT, 16 au 18 décembre 2007
 
 77 Maistri P., Leveugle R., Multi-cycle Fault Injections in Error Detecting Implementations of the Advanced Encryption Standard, International Design and Test Workshop (IDT’07), pp. 15-20, Cairo, EGYPT, 16 au 18 décembre 2007
 
 78 Smekens C., Leveugle R., On deratings to refine system-level failure rate estimations, International Conference on Electronics, Circuits and Systems (ICECS’07), pp. 326-329, Marrakech, MOROCCO, 11 au 14 décembre 2007
 
 79 Portolan M., Leveugle R., Effective checkpoint and rollback using hardware/OS collaboration, 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT'07), pp. 370-378, Rome, ITALY, 26 au 28 septembre 2007
 
 80 Maistri P., Vanhauwaert P., Leveugle R., Evaluation of register-level protection techniques for the Advanced Encryption Standard by multi-level fault injections, International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT’07), pp. 499-507, Rome, ITALY, 26 au 28 septembre 2007
 
 81 Maistri P., Vanhauwaert P., Leveugle R., A novel double-data-rate AES architecture resistant against fault injection, Workshop on Fault Diagnosis and Tolerance in Cryptography (FDTC’07), pp. 54-61, Vienna, AUSTRIA, DOI: 10.1109/FDTC.2007.4318985, 10 septembre 2007
 
 82 Bocquillon A., Foucard G., Miller F., Buard N., Leveugle R., Daniel C., Rakers S., Carriere T., Pouget V., Velazco R., Highlights of laser testing capabilities regarding the understanding of SEE in SRAM Based FPGAs, 9th European Conference on Radiation and its Effects on Components and Systems (RADECS’07), Deauville, FRANCE, DOI: 10.1109/RADECS.2007.5205500, 10 au 14 septembre 2007
 
 83 Monnet Y., Renaudin M., Leveugle R., Formal analysis of quasi delay insensitive circuits behavior in the presence of SEUs, 13th IEEE International On-Line Testing symposium (IOLTS’07), pp. 113 - 118, Hersonissos-Heraklion, CRETE, DOI: 10.1109/IOLTS.2007.33 IEEE, 8 au 11 juillet 2007
 
 84 Maingot V., Leveugle R., On the use of error correcting and detecting codes in secured circuits , PH.D Research in Microelectronics and Electronics conference (PRIME’07), pp. 245-248, Bordeaux, FRANCE, 2 au 5 juillet 2007
 
 85 Dang T.T., Anghel L., Leveugle R., CNTFET-based logic gates and characteristics, IEEE Silicon Nanoelectronics Workshop (SNW’07), pp. 131-132, Kyoto, JAPAN, 10 au 11 juin 2007
 
 86 Leveugle R., Ammari A., Maingot V., Teyssou E, Moitrel P., Mourtel C., Feyt N., Rigaud J.B., Tria A., Experimental Evaluation of Protections Against Laser-induced Faults and Consequences on Fault Modeling, Design, Automation & Test in Europe Conference & Exhibition (DATE '07), pp. 1587-1592, Nice, FRANCE, DOI: 10.1109/DATE.2007.364528, 16 au 20 avril 2007
 
 87 Maingot V., Leveugle R., On the use of error correcting codes in secured circuits, 8th Latin-American Test Workshop (LATW’07), pp. 209-214, Cuzco, PERU, 12 au 14 mars 2007
 
 88 Ammari A., Anghel L., Leveugle R., Lazzari C., Reis R., SET fault injection methods in analog circuits: case study, 8th Latin-American Test Workshop (LATW’07), pp. 155-160, Cuzco, PERU, 12 au 14 mars 2007
 
 89 Pouget V., Douin A., Lewis D., Fouillat P., Foucard G., Peronnard P., Maingot V., Ferron J.B., Anghel L., Leveugle R., Velazco R., Tools and methodology development for pulsed laser fault injection in SRAM-based FPGAs, 8th Latin-American Test Workshop (LATW’07), pp. 167-172, Cuzco, PERU, 12 au 14 janvier 2007
 
 90 Maingot V., Leveugle R., Error detection code efficiency for secure chips, International Conference on Electronics, Circuits and Systems (ICECS’06), pp. 561-564, Nice, FRANCE, 10 au 13 décembre 2006
 
 91 Dang T.T., Anghel L., Leveugle R., CNTFET-based logic gates and simulation, IEEE International Design and Test Workshop (IDT’06), Dubai, UNITED ARABIAN EMIRATES, 19 au 20 novembre 2006
 
 92 Vanhauwaert P., Leveugle R., Roche P., Reduced instrumentation and optimized fault injection control for dependability analysis, Conference on Very Large Scale Integration and System-on-Chip (VLSI-SoC’06), pp. 391-396, Nice, FRANCE, 16 au 18 octobre 2006
 
 93 Monnet Y., Renaudin M., Leveugle R., Clavier C., Moitrel P., Case Study of a Fault Attack on Asynchronous DES Crypto-Processors, 3rd Workshop on Fault Diagnosis and Tolerance in Cryptography (FDTC'06), pp. 88-97, Yokohama, JAPAN, 10 octobre 2006
 
 94 Dang T.T., Anghel L., Leveugle R., CNTFET basics and simulation, Design and Test of Integrated Systems (DTIS'06), pp. 28-33, Tunis, TUNISIA, 5 au 7 septembre 2006
 
 95 Vanhauwaert P., Leveugle R., Roche P., Dependability analysis : performance evaluation of environment configurations, International Conference on Design & Test of Integrated Systems in Nanoscale Technology (DTIS'06), pp. 335-340, Tunis, TUNISIA, 5 au 7 septembre 2006
 
 96 Monnet Y., Renaudin M., Leveugle R., Feyt N., Moitrel P., M'Buwa Nzenguet F., Practical evaluation of fault countermeasures on an asynchronous DES cryptoprocessor, 12th IEEE International On-Line Testing Symposium (IOLTS’06), pp. 125-130, Como, ITALY, DOI: 10.1109/IOLTS.2006.50, 10 au 12 juillet 2006
 
 97 Vanhauwaert P., Leveugle R., Roche P., A flexible SoPC-based fault injection environment, 9th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems (DDECS'06), pp. 192 - 197, Prague, CZECH REPUBLIC, 18 au 21 avril 2006
 
 98 Leveugle R., Maingot V., On the use of information redundancy when designing secure chips, 9th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems (DDECS’06), pp. 141-142 , Prague, CZECH REPUBLIC, 18 au 21 avril 2006
 
 99 Ammari A., Nicolescu B., Leveugle R., Savaria B.Y., Evaluation of a software-based error detection technique by RT-level fault injection, 3rd IEEE International Workshop on Electronic Design, Test & Applications (DELTA’06), pp. 488-493 , Kuala Lumpur,, MALAYSIA, 17 au 19 janvier 2006
 
100 Portolan M., Leveugle R., Towards a secure and reliable system, Embedded and ubiquitous computing (International Conference EUC 2005), pp. 1085-1098, Nagasaki, JAPAN, DOI: 10.1007/11596356_108, 6 au 9 décembre 2005
 
101 Monnet Y., Renaudin M., Leveugle R., Dumont S., Bouesse G.F., An Asynchronous DES Crypto-Processor Secured against Fault Attacks, 15th IFIP Int. Conf. on Very Large Scale Integration Systems (VLSI-SoC'05), pp. 21-26, Perth, AUSTRALIA, 1 octobre 2005
 
102 Portolan M., Leveugle R., A highly flexible hardened RTL processor core based on LEON, 8th European Conference on Radiation and its Effects on Components and Systems (RADECS'05), Cap d'Agde, FRANCE, 19 au 23 septembre 2005
 
103 Hadjiat K., Ammari A., Leveugle R., Early functional evaluation of SET effects, 8th European Conference on Radiation and its Effects on Components and Systems (RADECS'05), Cap d'Agde, FRANCE, 19 au 23 septembre 2005
 
104 Hadjiat K., Ammari A., Leveugle R., Injection of multiple bit-flips for counter measures validation, 2nd International Workshop on Fault Diagnosis and Tolerance in Cryptography (FDTC'05), pp. 152-162, Edinburg, UNITED KINGDOM, 2 septembre 2005
 
105 Leveugle R., A new approach for early dependability evaluation based on formal property checking and controlled mutations, 11th IEEE International On-Line Testing Symposium (IOLTS'05), pp. 260-5, St Raphael, FRANCE, DOI: 10.1109/IOLTS.2005.8, 6 au 8 juillet 2005
 
106 Monnet Y., Renaudin M., Leveugle R., Hardening techniques against transient faults for asynchronous circuits, 1th IEEE International On-Line Testing Symposium (IOLTS'05), pp. 129-134, St Raphael, FRANCE, DOI: 10.1109/IOLTS.2005.30, 6 au 8 juillet 2005
 
107 Leveugle R., Introduction to the special session on secure implementations, 11th IEEE international on-Line testing symposium, pp. 115, St Raphael, FRANCE, DOI: 10.1109/IOLTS.2005.40, 6 au 8 juillet 2005
 
108 Breveglieri L., Leveugle R., Nieuwland A., Rothbart K., Seifert J.-P., On-line testing for secure implementations: design and validation, 11th IEEE International On-Line Testing Symposium, pp. 211, St Raphael, FRANCE, DOI: 10.1109/IOLTS.2005.52, 6 au 8 juillet 2005
 
109 Portolan M., Leveugle R., On the Need for Common Evaluation Methods for Fault Tolerance Costs in Microprocessors, IEEE International On-Line Testing Symposium (IOLT'05), pp. 247- 252, St Raphael, FRANCE, DOI: 10.1109/IOLTS.2005.46, 6 au 8 juillet 2005
 
110 Monnet Y., Renaudin M., Leveugle R., Asynchronous circuits transient faults sensitivity evaluation, IEEE Design Automation Conference (DAC'05), pp. 863-868, Anaheim, CA, UNITED STATES, DOI: 10.1145/1065579.1065805, 13 au 17 juin 2005
 
111 Hadjiat K., Leveugle R., Early dependability evaluation: injection of multiple bit-flips, 6th IEEE Latin American Test Workshop (LATW'05), pp. 109-114, Salvador, BRAZIL, 30 mars au 2 avril 2005
 
112 Portolan M., Leveugle R., A context-switch based checkpoint and rollback scheme, 19th Conference on Design of Circuits and Integrated Systems (DCIS'04), pp. 423-428, Bordeaux, FRANCE, 24 au 26 novembre 2004
 
113 Leveugle R., Cimonnet D., Ammari A., System-level dependability analysis with RT-level fault injection accuracy, 19th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'04), pp. 451-458, Cannes, FRANCE, DOI: 10.1109/DFTVS.2004.1347870, 10 au 13 octobre 2004
 
114 Monnet Y., Renaudin M., Leveugle R., Asynchronous circuits sensitivity to fault injection, 10th IEEE International On-Line Testing Symposium (IOLTS'04), pp. 121-126, Madeira, PORTUGAL, 12 au 14 juillet 2004
 
115 Ammari A., Hadjiat K., Leveugle R., On combining fault classification and error propagation analysis in RT-Level dependability evaluation, 10th IEEE International On Line Testing Symposium (IOLTS'04), pp. 227-232, Madeira, PORTUGAL, 12 au 14 juillet 2004
 
116 Portolan M., Leveugle R., Operating system function reuse to achieve low-cost fault tolerance, 10th IEEE International On-Line Testing Symposium (IOLTS'04) , pp. 167- 172, Madeira, PORTUGAL, 12 au 14 juillet 2004
 
117 Leveugle R., Early analysis of fault-attack effects for cryptographic hardware, Workshop on Fault Diagnosis and Tolerance in Cryptography (FDTC'04), pp. 348-353, Florence, ITALY, 30 juin 2004
 
118 Leveugle R., Ammari A., Early SEU fault injection in digital, analog and mixed signal circuits: a global flow, Design, Automation and Test in Europe Conference and Exhibition (DATE'04), pp. 590-595, Dresden, GERMANY, DOI: 10.1109/DATE.2004.1268909, 16 au 20 février 2004
 
119 Ammari A., Leveugle R., Sonza Reorda M., Violante M., Detailed comparison of dependability analyses performed at RT and gate levels, 18th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, pp. 336-343, Boston, MA., UNITED STATES, DOI: 10.1109/DFTVS.2003.1250129, 3 au 5 novembre 2003
 
120 Leveugle R., Antoni L., Feher B., Dependability analysis: a new application for run-time reconfiguration, International Parallel and Distributed Processing Symposium (IPDPS'03), pp. 173, Nice, FRANCE, DOI: 10.1109/IPDPS.2003.1213319, 22 au 26 avril 2003
 
121 Antoni L., Leveugle R., Feher B., Using run-time reconfiguration for fault injection in hardware prototypes, 17th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'02), pp. 245-253, Vancouver, CANADA, DOI: 10.1109/DFTVS.2002.1173521, 6 au 8 novembre 2002
 
122 Leveugle R., Hadjiat K., Multi-level fault injection experiments based on VHDL descriptions: a case study, Eighth IEEE International On Line Testing Workshop (IOLTW'02), pp. 107-11, Isle of Bendor, FRANCE, DOI: 10.1109/OLT.2002.1030192, 8 au 10 juillet 2002
 
123 Leveugle R., Automatic modifications of high level VHDL descriptions for fault detection or tolerance, Design, Automation and Test in Europe Conference and Exhibition (DATE'02), pp. 837-841, Paris, FRANCE, DOI: 10.1109/DATE.2002.998396, 8 mars 2002
 
124 Leveugle R., A low-cost hardware approach to dependability validation of IPs, IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'01), pp. 242-249, San Francisco, CA, UNITED STATES, DOI: 10.1109/DFTVS.2001.966776, 24 au 26 octobre 2001
 
125 Leveugle R., Cercueil R., High level modifications of VHDL descriptions for on-line test or fault tolerance, IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'01), pp. 84-91, San Francisco, CA, UNITED STATES, DOI: 10.1109/DFTVS.2001.966756, 24 au 26 octobre 2001
 
126 Velazco R., Leveugle R., Calvo O., Upset-like fault injection in VHDL descriptions: A method and preliminary results, IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'01), pp. 259-267, San Francisco, CA, UNITED STATES, DOI: 10.1109/DFTVS.2001.966778, 24 au 26 octobre 2001
 
127 Antoni L., Leveugle R., Feher B., Using run-time reconfiguration for fault injection applications, 18th IEEE Instrumentation and Measurement Technology Conference (IMTC'01). Rediscovering Measurement in the Age of Informatics (Cat. No.01CH 37188) , pp. 1773-1777, Budapest, HUNGARY, DOI: 10.1109/IMTC.2001.929505, 21 au 23 mai 2001
 
128 Leveugle R., Fault injection in VHDL descriptions and emulation, IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'00), pp. 414-419, Yamanashi, JAPAN, DOI: 10.1109/DFTVS.2000.887182, 25 au 27 octobre 2000
 
129 Antoni L., Leveugle R., Feher B., Using run-time reconfiguration for fault injection in hardware prototypes, IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'00), pp. 405-413, Yamanashi, JAPAN, DOI: 10.1109/DFTVS.2000.887181, 25 au 27 octobre 2000
 
130 Leveugle R., Hadjiat K., Optimized generation of VHDL mutants for injection of transition errors, 13th Symposium on Integrated Circuits and Systems Design (SBCCI '00), pp. 243-248, Manaus, BRAZIL, DOI: 10.1109/SBCCI.2000.876037, 18 au 24 septembre 2000
 
131 Chagoya A., Leveugle R., Experiments on multimedia support of VLSI design teaching in the MODEM project, IEEE International Conference on Microelectronic Systems Education (MSE'99), pp. 82-83, Arlington, Virginia, UNITED STATES, DOI: 10.1109/MSE.1999.787049, 19 au 21 juillet 1999
 
132 Leveugle R., Towards modeling for dependability of complex integrated circuits, 5th IEEE International On-Line Testing workshop (IOLTW'99), pp. 194-198, Rhodes, GREECE, 5 au 7 juillet 1999
 
133 Leveugle R., Brahic P., Analysis of defect tolerant crossbar network implementations [MCM], 6th Biennial Conference on Electronics and Microsystems Technology (BEC '98), pp. 37-40, Tallinn, ESTONIA, 7 au 9 octobre 1998
 
134 Leveugle R., Behavior modeling of faulty complex VLSIs: why and how?, 6th Biennial Conference on Electronics and Microsystems Technology (BEC '98), pp. 191-194, Tallinn, ESTONIA, 7 au 9 octobre 1998
 
135 Leveugle R., Saucier G., Ubar R., Compaction of decision diagrams for describing multi-process VHDL descriptions, 6th Biennial Conference on Electronics and Microsystems Technology (BEC '98), pp. 195-198, Tallinn, ESTONIA, 7 au 9 octobre 1998
 
136 Leveugle R., Ubar R., Synthesis of decision diagrams from clock-driven multi-process VHDL descriptions for test generation, 5th International Conference on Mixed Design of Integrated Circuits and Systems (MIXDES'98), pp. 353-358, Lodz, POLAND, 18 au 20 juin 1998
 
137 Wending X., Chauvet H., Reveret L., Rochet R., Leveugle R., Automatic and optimized synthesis of dataparts with fault detection or tolerance capabilities, IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems 'DFT'97), pp. 195-203, Paris, FRANCE, DOI: 10.1109/DFTVS.1997.628325, 20 au 22 octobre 1997
 
138 Wending X., Rochet R., Leveugle R., ROM-based synthesis of fault-tolerant controllers, IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'96), pp. 304-308, Boston, MA., UNITED STATES, DOI: 10.1109/DFTVS.1996.572037, 6 au 8 novembre 1996
 
139 Wending X., Rochet R., Leveugle R., Standard and ROM-based synthesis of FSMs with control flow checking capabilities, 14th IEEE VLSI Test Symposium (VTS'96), pp. 81-86, Princeton, New Jersey, UNITED STATES, DOI: 10.1109/VTEST.1996.510839, 28 avril au 1 mai 1996
 
140 Brahic P., Leveugle R., Saucier G., Design of defect-tolerant scan chains for MCMs with an active substrate, IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems (DFT'95), pp. 252-260, Lafayette, LA, UNITED STATES, DOI: 10.1109/DFTVS.1995.476959, 13 au 15 novembre 1995
 
141 Rochet R., Leveugle R., Saucier G., Efficiency comparison of signature monitoring schemes for FSMs, International Conference on Very Large Scale Integration (VLSI'95), pp. 705-710, Chiba, JAPAN, DOI: 10.1109/ASPDAC.1995.486391, 29 août au 1 septembre 1995
 
142 Rochet R., Leveugle R., Saucier G., Efficient synthesis of fault-tolerant controllers, The European Design and Test Conference (ED&TC'95), pp. 593, Paris, FRANCE, DOI: 10.1109/EDTC.1995.470316, 6 au 9 mars 1995
 
143 Leveugle R., Rochet R., Saucier G., Alternative approaches to fault detection in FSMs, IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems (DFT'94), pp. 271-279, Montréal, Québec, CANADA, DOI: 10.1109/DFTVS.1994.630040, 17 au 19 octobre 1994
 
144 Michel T., Leveugle R., Saucier G., Doucet R., Chapier P., Taking advantage of ASICs to improve dependability with very low overheads, The European Design and Test Conference (ED&TC'94), pp. 14-18, Paris, FRANCE, DOI: 10.1109/EDTC.1994.326905, 28 février au 3 mars 1994
 
145 Safinia C., Leveugle R., Saucier G., Taking advantage of high level functional information to refine timing analysis and timing modeling, The European Design and Test Conference (ED&TC'94), pp. 349-353, Paris, FRANCE, DOI: 10.1109/EDTC.1994.326853, 28 février au 3 mars 1994
 
146 Rochet R., Saucier G., Leveugle R., Analysis and comparison of fault tolerant FSM architecture based on SEC codes, International Workshop on Defect and Fault Tolerance in VLSI Systems (DFTVS'93), pp. 9-16, Venice, ITALY, DOI: 10.1109/DFTVS.1993.595604, 27 au 29 octobre 1993
 
147 Leveugle R., Delord X., Saucier G., Influence of error correlations on the signature analysis aliasing, IEEE International Conference on Computer Design: VLSI in Computers and Processors (ICCD'93), pp. 584-587, Cambridge, MA , UNITED STATES, DOI: 10.1109/ICCD.1993.393310, 3 au 6 octobre 1993
 
148 Leveugle R., Rochet R., Saucier G., Martinez L., Pitot C., A synthesis tool for fault-tolerant finite state machines, The Twenty Third International Symposium on Fault Tolerant Computing (FTCS'93) Digest of Papers , pp. 502-511, Toulouse, FRANCE, DOI: 10.1109/FTCS.1993.627353, 22 au 24 juin 1993
 
149 Leveugle R., Optimized state assignment of single fault tolerant FSMs based on SEC codes, 30th IEEE Design Automation Conference (DAC'93), pp. 14-18, Dallas, TX, UNITED STATES, 14 au 18 juin 1993
 
150 Michel T., Leveugle R., Gaume F., Roane R., An application specific microprocessor with two-level built-in control flow checking capabilities, Euro-ASIC-'92, pp. 310-313, Paris, FRANCE, DOI: 10.1109/EUASIC.1992.228013, 1 au 5 juin 1992
 
151 Leveugle R., Safinia C., Magarshack P., Sponga L., Datapath implementation: bit-slice structure versus standard cells, Euro-ASIC-'92, pp. 83-88, Paris, FRANCE, DOI: 10.1109/EUASIC.1992.228054, 1 au 5 juin 1992
 
152 Leveugle R., Martinez L., Design methodology of FSMs with intrinsic fault tolerance and recovery capabilities, Euro-ASIC'92, pp. 201-206, Paris, FRANCE, DOI: 10.1109/EUASIC.1992.228024, 1 au 5 juin 1992
 
153 Abouzeid F., Leveugle R., Saucier G., Jamier R., Logic synthesis for automatic layout, Euro-ASIC'92, pp. 146-151, Paris, FRANCE, DOI: 10.1109/EUASIC.1992.228033, 1 au 5 juin 1992
 
154 Karam M., Leveugle R., Saucier G., Hierarchical test generation based on delayed propagation, IEEE International Test Conference (ITC'91), pp. 739-747, Nashville, TN, UNITED STATES, DOI: 10.1109/TEST.1991.519739, 26 au 30 octobre 1991
 
155 Michel T., Leveugle R., Saucier G., A new approach to control flow checking without program modification, 21th International Symposium on Fault Tolerant Computing (FTCS'91), pp. 334-341, Montreal, CANADA, DOI: 10.1109/FTCS.1991.146682, 25 au 27 juin 1991
 
156 Lestrat P., Leveugle R., Magarshack P., Comprehensive CAD support for boundary scan implementation in ASICs, Euro-ASIC'91, pp. 278-283, Paris, FRANCE, DOI: 10.1109/EUASIC.1991.212852, 27 au 31 mai 1991
 
157 Delord X., Leveugle R., Saucier G., Extended duplex fault tolerant system with integrated control flow checking, International Workshop of the Defect and Fault Tolerance in VLSI Systems (DFT'90), pp. 123-134, Tampa, Florida, UNITED STATES, 22 au 24 octobre 1990
 
158 Leveugle R., Michel T., Saucier G., Design of microprocessors with built-in on-line test, 20th International Symposium Fault Tolerant Computing (FTCS'90), pp. 450-456, Newcastle Upon Tyne, UNITED KINGDOM, DOI: 10.1109/FTCS.1990.89381, 26 au 28 juin 1990
 
159 Leveugle R., Saucier G., A synthesis method for concurrently checked controllers, 7th International Conference on Reliability and Maintainability, pp. 496-501, Brest, FRANCE, 18 au 22 juin 1990
 
160 Delord X., Leveugle R., Saucier G., Improved duplex fault tolerant architecture based on integrated information compaction devices, 7th International Conference on Reliability and Maintainability, pp. 514-519, Brest, FRANCE, 18 au 22 juin 1990
 
161 Leveugle R., Soueidan M., Design of an application specific microprocessor, International Workshop of the Logic and Architecture Synthesis for Silicon Compilers, pp. 255-268, Grenoble, FRANCE, 1 novembre 1989
 
162 Leveugle R., Saucier G., Highly wireable multilevel synthesis with compiled cells, International Workshop of the Logic and Architecture Synthesis for Silicon Compilers, pp. 37-52, Grenoble, FRANCE, 1 novembre 1989
 
163 Saucier G., Leveugle R., Abouzeid F., A channelless layout for multilevel synthesis with compiled cells, IEEE International Conference on Computer Design: VLSI in Computers and Processors, pp. 35-38, Cambridge, MA, UNITED STATES, DOI: 10.1109/ICCD.1989.63323, 2 au 4 octobre 1989
 
164 Leveugle R., Saucier G., Concurrent checking in dedicated controllers, IEEE International Conference on Computer Design: VLSI in Computers and Processors (ICCD'89), pp. 124-127, Cambridge, MA, UNITED STATES, DOI: 10.1109/ICCD.1989.63341, 2 au 4 octobre 1989
 
165 Leveugle R., Saucier G., Optimized synthesis of dedicated controllers with concurrent checking capabilities, International Test Conference (ITC'89), pp. 355-363, Washington, D.C, UNITED STATES, DOI: 10.1109/TEST.1989.82319, 29 au 31 août 1989
 
166 Crastes-De-Paulet M., Duff C., Leveugle R., Poirot F., Saucier G., Sicard P., ASYL: a logic and architecture design automation system, Euro-ASIC'89, pp. 182-209, Grenoble, FRANCE, 25 au 27 janvier 1989
 
167 Delord X., Leveugle R., Saucier G., Built-in concurrent checking of ASICs, Euro-ASIC-89, pp. 481-501, Grenoble, FRANCE, 25 au 27 janvier 1989
 
remonter

9 Chapitres de livre

1 Beroulle V., Candelier P., De Castro S., Di Natale G., Dutertre J.M., Flottes M.-L., Hély D., Hubert G., Leveugle R., Lu F., Maistri P., Papadimitriou A., Rouzeyre B., Tavernier C., Vanhauwaert P., Laser-induced fault effects in security-dedicated circuits, VLSI-SoC: Internet of Things Foundations, L. Claesen, M.-T. Sanz-Pascual, R. Reis, A. Sarmiento-Reyes (Eds.) , Ed. Elsevier, pp. 220-240, Vol. 464, 2015
 
2 Leveugle R., Test des circuits intégrés numériques - Conception orientée testabilité, Techniques de l'Ingénieur, Ed. , pp. article E 2461, 2002
 
3 Leveugle R., Test des circuits intégrés numériques - Notions de base. Génération de vecteurs, Techniques de l'Ingénieur, Ed. , pp. article E 2460, 2002
 
4 Leveugle R., Test des circuits intégrés numériques - Pour en savoir plus, Techniques de l'Ingénieur , Ed. , pp. article E 2462, 2002
 
5 Leveugle R., Test of single fault tolerant controllers in VLSI circuits, IFIP Transactions A Computer Science and Technology, Ed. , pp. 123-132, Vol. A-42, 1994
 
6 Safinia C., Leveugle R., Clocking scheme selection for circuits made up of a controller and a datapath, IFIP Transactions A Computer Science and Technology, Ed. , pp. 293-308, Vol. A-22, 1993
 
7 Leveugle R., Safinia C., Generation of optimized datapaths: bit-slice versus standard cells, IFIP Transactions A Computer Science and Technology, Ed. , pp. 153-166, Vol. A-22, 1993
 
8 Abouzeid F., Leveugle R., Saucier G., Logic synthesis for automatic layout, IFIP Transactions A Computer Science and Technology, Ed. , pp. 335-343, Vol. A-22, 1993
 
9 Gerbaux L., Leveugle R., Synthesis of large controllers using ROM or PLA generators, IFIP Transactions A Computer Science and Technology, Ed. , pp. 47-59, Vol. A-22, 1993
 
remonter

2 Livres & Éditions Ouvrages

1 Metra C., Leveugle R. (Eds.) On-Line Test and Fault Tolerance, Journal of Electronic Testing: Theory and Applications (JETTA), Vol. 21, No.4, Ed. Kluwer Academic Publishers, 2005
 
2 Leveugle R., Chapman G. (Eds.) Defect and Fault Tolerance in VLSI Systems, Microelectronics Journal, Vol. 34, No1, Ed. Elsevier, 2003
 
remonter

3 Revues nationales

1 Rochet R., Leveugle R., Saucier G., Synthesis for dependability of finite state machines, Technique et Science Informatiques (TSI), Vol. 15, No. 4, pp. 379-404, 1996
 
2 Leveugle R., Synthesis of controllers with concurrent checking: method and case studies, L'Onde Electrique, Vol. 71, No. 3, pp. 69-75, mai-juin 1991
 
3 Leveugle R., Soueidan M., Design of a microprocessor with integrated on-line test for highly dependable systems, L'Onde Electrique, Vol. 68, No. 6, pp. 59-66, novembre-décembre 1988
 
remonter

21 Conférences nationales

 1 Reynaud V., Maistri P., Leveugle R., Accès autorisé au réseau reconfigurable de test par ensemble de segments, 13ème Colloque du GDR SoC/SiP, Paris, FRANCE, 13 au 15 juin 2018
 
 2 Mkhinini A., Maistri P., Leveugle R., Chiffrement homomorphique : entre développements théoriques et implantations pratiques, 8ème Colloque du GdR SoC-SiP, Paris, FRANCE, 11 au 13 juin 2014
 
 3 Chibani K., Portolan M., Leveugle R., Analyse de criticité des registres dans un microprocesseur SPARC, 17èmes Journées Nationales du Réseau Doctoral en Microélectronique (JNRDM'14), pp. 4, Lille, FRANCE, 26 au 28 mai 2014
 
 4 Papadimitriou A., Hély D., Beroulle V., Maistri P., Leveugle R., FPGA emulation of laser attacks against secure deep submicron integrated circuits, 7ème Colloque du GdR SoC-SiP, Lyon, FRANCE, 10 au 12 juin 2013
 
 5 Leveugle R., Evaluation prédictive de robustesse de systèmes intégrés numériques, Journées SoCKET, Grenoble, FRANCE, 14 au 15 octobre 2010
 
 6 Ben Jrad M., Leveugle R., Injection de fautes par reconfiguration partielle - Application à un FPGA Virtex II Pro, 13èmes Journées Nationales du Réseau Doctoral en Microélectronique (JNRDM'10), Montpellier, FRANCE, 7 au 9 juin 2010
 
 7 Bergaoui S., Leveugle R., Nouvelle méthode de vérification de flot de contrôle avec signatures disjointes, 13èmes Journées Nationales du Réseau Doctoral en Microélectronique (JNRDM'10), Montpellier, FRANCE, 7 au 9 juin 2010
 
 8 Ferron J.B., Anghel L., Leveugle R., Predictive analysis of configuration bit criticality in SRAM-based FPGAs – Methodology, tools, and results, 3ème Colloque du GdR SoC-SiP, Paris, FRANCE, 10 au 12 juin 2009
 
 9 Clavel R., Pierre L., Leveugle R., Premiers résultats sur l'utilisation d'ACL2 pour l'évaluation de la conséquence des erreurs logiques, 2ème Colloque du GdR SoC-SiP, Paris, FRANCE, 4 au 6 juin 2008
 
10 Canivet G., Clédière J., Leveugle R., Renaudin M., Valette F., Injection de fautes sur composant Virtex-II XC2V1000, 11ème Journées Nationales du Réseau Doctoral en Microélectronique (JNRDM’08), pp. 26, Bordeaux, FRANCE, 14 au 16 mai 2008
 
11 Dang T.T., Anghel L., Leveugle R., Structures robustes pour circuits logiques à base de CNTFET, 11ème Journées Nationales du Réseau Doctoral en Microélectronique (JNRDM’08), pp. 66, Bordeaux, FRANCE, 14 au 16 mai 2008
 
12 Vanhauwaert P., Leveugle R., Environnement d’analyse de sûreté sur SoPC, 9èmes Journées Nationales du Réseau Doctoral en Microélectronique (JNRDM’06), Rennes, FRANCE, 10 au 12 mai 2006
 
13 Maingot V., Leveugle R., Redondance d’information : une sécurité suffisante ?, 9ème Journées Nationales du Réseau Doctoral en Microélectronique (JNRDM’06), Rennes, FRANCE, 10 au 12 mai 2006
 
14 Monnet Y., Renaudin M., Leveugle R., Analyse du comportement des circuits asynchrones en présence de fautes, 8èmes Journées Nationales du Réseau Doctoral en Microélectronique (JNRDM'05), pp. 455-457, Paris, FRANCE, 10 au 12 mai 2005
 
15 Hadjiat K., Ammari A., Leveugle R., Modélisation de fautes et génération de mutants pour analyse de robustesse de circuits sécurisés, 8èmes Journées Nationales du Réseau Doctoral en Microélectronique (JNRDM'05), pp. 472-474, Paris, FRANCE, 10 au 12 mai 2005
 
16 Hadjiat K., Ammari A., Leveugle R., Application et combinaison de deux approches d'analyse de sûreté, VIIème Journées Nationales du Réseau Doctoral en Microélectronique (JNRDM'04), pp. 410-412, Marseille, FRANCE, 4 au 6 mai 2004
 
17 Monnet Y., Renaudin M., Leveugle R., Etude et modélisation de circuits résistants aux attaques par injection de fautes, VIIème Journées Nationales du Réseau Doctoral en Microélectronique (JNRDM'04), pp. 507-509, Marseille, FRANCE, 4 au 6 mai 2004
 
18 Ammari A., Leveugle R., Injections de fautes transitoires dans une PLL, VIIème Journées Nationales du Réseau Doctoral en Microélectronique (JNRDM'04), pp. 295-297, Marseille, FRANCE, 4 au 6 mai 2004
 
19 Portolan M., Leveugle R., Réalisation d'une tolérance aux fautes à bas coût dans les SoCs en utilisant le système d'exploitation, VIIème Journées Nationales du Réseau Doctoral en Microélectronique (JNRDM'04), pp. 454-456, Marseille, FRANCE, 4 au 6 mai 2004
 
20 Hadjiat K., Leveugle R., Expériences d'injection de fautes multi-niveaux dans des descriptions VHDL, Colloque CAO de circuits et systèmes intégrés, Paris, FRANCE, 15 au 17 mai 2002
 
21 Hadjiat K., Leveugle R., Évaluation prédictive de la sûreté de fonctionnement d'un circuit intégré, Journées Nationales du Réseau Doctoral en Microélectronique (JNRDM'02), Grenoble, FRANCE, 23 au 25 avril 2002
 
remonter

7 Autres communications

1 Maistri P., Dutertre J.M., Leveugle R., Laser Attacks against DDR Redundancy, Workshop on SecURity, REliAbiLity, test, prIvacy, Safety and Trust of Future Devices (SURREALIST'2018), Bremen, GERMANY, 2018
 
2 Papadimitriou A., Hély D., Beroulle V., Maistri P., Leveugle R., FPGA emulation of laser attacks against secure deep submicron integrated circuits, Second Workshop on Trustworthy Manufacturing and Utilization of Secure Devices (TRUDEVICE'14), Paderborn, GERMANY, 2014
 
3 Alberto D., Maistri P., Leveugle R., Investigation of Electromagnetic Fault Injection Effects on Embedded Cryptosystems, First Workshop on Trustworthy Manufacturing and Utilization of Secure Devices (TRUDEVICE'13), pp. 1-2, Avignon, FRANCE, 2013
 
4 Leveugle R., Natural and malicious soft errors: dependability and security issues in ASICs and reconfigurable platforms, Ecole Nationale d'Ingénieurs de Sousse (ENISo), Sousse, TUNISIA, 2013
 
5 Maistri P., Leveugle R., Early pruning of soft errors and transient faults with Petri netS, Electronic Symposium Digest of European Test Symposium (ETS'09), Sevilla, SPAIN, 2009
 
6 Vanhauwaert P., Leveugle R., Evaluating soft error effects using probabilistic testability analysis: a case study, 2nd IFIP International Workshop on Dependable Circuit Design (DECIDE'08), Playa del Carmen, MEXICO, 2008
 
7 Leveugle R., Soueidan M., Saucier G., Wehn N., Glesner M., Trilhe J., Reconfiguration in a microprocessor: practical results, 6th Annual ESPRIT Conference (ESPRIT '89) , pp. 126-137, Brussels, BELGIUM, 1989
 
remonter

5 Rapports

1 Monnet Y., Leveugle R., Bouesse G.F., Renaudin M., Dumont S., An Asynchronous DES Crypto-Processor Secured against Fault Attacks, ISRN: TIMA-RR--06/02-04--FR, 1 janvier 2005
 
2 Renaudin M., Monnet Y., Leveugle R., Asynchronous Circuits Sensitivity To Transient Faults, ISRN: TIMA-RR--05/04-02--FR, 1 janvier 2005
 
3 Renaudin M., Monnet Y., Leveugle R., Asynchronous Circuits Transient Faults Sensitivity Evaluation, ISRN: TIMA-RR--06/02-02--FR, 1 janvier 2005
 
4 Renaudin M., Monnet Y., Leveugle R., Hardening Techniques against Transient Faults for Asynchronous Circuits , ISRN: TIMA-RR--06/02-05--FR, 1 janvier 2005
 
5 Velazco R., Leveugle R., Calvo O., Upset-like Fault Injection in VHDL Descriptions:, ISRN: TIMA-RR--01/10-6--FR, 1 janvier 2001
 
remonter

2 Logiciels

1 Leveugle R., Chibani K., Portolan M., EARS (Evaluation Avancée de Robustesse de Systèmes intégrés / Early Analysis of Robustness for integrated Systems), Logiciel, 30 décembre 2016
 
2 Leveugle R., AMfoRS' TIMA Emulation-based Fault Injection plaTform on Virtex-5, Plateforme, 26 juin 2015
 
remonter