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64 résultats

   9 Revues internationales
   6 Conférences invitées
  38 Conférences internationales
   1 Chapitres de livre
   3 Conférences nationales
   6 Autres communications
   1 Rapports

9 Revues internationales

1 Dutertre J.M., Beroulle V., Candelier P., De Castro S., Faber L.-B., Flottes M.-L., Gendrier P., Hély D., Leveugle R., Maistri P., Di Natale G., Papadimitriou A., Sensitivity to Laser Fault Injection: CMOS FD-SOI vs. CMOS bulk (Early Access), IEEE Transactions on Device and Materials Reliability, Vol. , DOI: 10.1109/TDMR.2018.2886463, décembre 2018
 
2 Leveugle R., Mkhinini A., Maistri P., Hardware Support for Security in the Internet of Things: From Lightweight Countermeasures to Accelerated Homomorphic Encryption, Information - Open Access Journal of Information Science, Ed. MDPI, Vol. 9, No. 5, pp. 114, DOI: 10.3390/info9050114, mai 2018
 
3 Mkhinini A., Maistri P., Leveugle R., Tourki R., Co-designed accelerator for homomorphic encryption applications, Advances in Science, Technology and Engineering Systems Journal (ASTESJ), Vol. 3, No. 1, pp. 426-433, DOI: 10.25046/aj030152, février 2018
 
4 Pontié S., Maistri P., Leveugle R., Dummy operations in scalar multiplication over elliptic curves: a tradeoff between security and performance, Microprocessors and Microsystems, Ed. Elsevier, Vol. 47, No. Part A, pp. 23-36, DOI: 10.1016/j.micpro.2016.02.016, novembre 2016
 
5 Papadimitriou A., Hély D., Beroulle V., Maistri P., Leveugle R., Analysis of laser-induced errors: RTL fault models versus layout locality characteristics, Microprocessors and Microsystems, Ed. Elsevier, Vol. 47, No. Part A, pp. 64-73, DOI: 10.1016/j.micpro.2016.01.018, novembre 2016
 
6 Alberto D., Maistri P., Leveugle R., Forecasting the effects of electromagnetic fault injections on embedded cryptosystems, Information Security Journal: A Global Perspective, Ed. taylor & francis group, Vol. 22, No. 5-6, pp. 237-243, DOI: 10.1080/19393555.2014.891278, mai-juin 2013
 
7 Canivet G., Maistri P., Leveugle R., Clédière J., Valette F., Renaudin M., Glitch and laser fault attacks onto a secure AES implementation on a SRAM-based FPGA, Journal of Cryptology, Ed. Springer , Vol. 24, No. 2, pp. 247-268, DOI: 10.1007/s00145-010-9083-9, avril 2011
 
8 Maistri P., Leveugle R., Double-Data-Rate computation as a countermeasure against fault analysis, IEEE Transactions on Computers, Ed. IEEE, Vol. 57, No. 11, pp. 1528-1539, DOI: 10.1109/TC.2008.149 , novembre 2008
 
9 Breveglieri L., Koren I., Maistri P., An operation-centered approach to fault detection in symmetric cryptography ciphers, IEEE Transactions on Computers, Ed. IEEE, Vol. Vol. 56, No. 5, pp. 635-649, DOI: 10.1109/TC.2007.1015, janvier 2007
 
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6 Conférences invitées

1 Maistri P., Secure Test Architectures in IoT, Invited Talk, European Nanoelectronics Applications, Design & Technology Conference (ADTC 2019), Dresden, GERMANY, 14 au 16 mai 2019
 
2 Maistri P., Countermeasures against Implementation Attacks on Private- and Public-Key Cryptosystems, Keynote in the Opening Session, International Conference on Applications and Techniques in Information Security, Cairns, AUSTRALIA, 26 au 28 octobre 2016
 
3 Bhasin S., Maistri P., Regazzoni F., Malicious Wave: a Survey on Actively Tampering Using Electromagnetic Glitch, International Symposium on Electromagnetic Compatibility (EMC'14), Raleigh, NC, UNITED STATES, 4 au 8 août 2014
 
4 Vanhauwaert P., Maistri P., Leveugle R., Papadimitriou A., Hély D., Beroulle V., On error models for RTL security evaluations, 9th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS'14), pp. 115-120, Santorini, GREECE, DOI: 10.1109/DTIS.2014.6850666, 6 au 7 mai 2014
 
5 Maistri P., Countermeasures against fault attacks: The good, the bad, and the ugly, IEEE International On-line Testing Symposium (IOLTS'11), pp. 134-137 , Athens, GREECE, DOI: 10.1109/IOLTS.2011.5993825 , 13 au 15 juillet 2011
 
6 Di Natale G., Flottes M.-L., Rouzeyre B., Maistri P., Leveugle R., Ensuring High Testability without Degrading Security, Embedded tutorial, European Test Symposium (ETS’09), Sevilla, SPAIN, 25 au 29 mai 2009
 
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38 Conférences internationales

 1 Dutertre J.M., Beroulle V., Candelier P., De Castro S., Faber L.-B., Flottes M.-L., Gendrier P., Hély D., Leveugle R., Maistri P., Di Natale G., Papadimitriou A., Rouzeyre B., Laser Fault Injection at the CMOS 28 nm Technology Node: an Analysis of the Fault Model, Fourteenth Workshop on Fault Diagnosis and Tolerance in Cryptography (FDTC'2018), Amsterdam, NETHERLANDS, 13 septembre 2018
 
 2 Dutertre J.M., Beroulle V., Candelier P., De Castro S., Faber L.-B., Flottes M.-L., Gendrier P., Hély D., Leveugle R., Maistri P., Di Natale G., Papadimitriou A., Rouzeyre B., The case of using CMOS FD-SOI rather than CMOS bulk to harden ICs against laser attacks, 24th IEEE International Symposium on On-Line Testing and Robust System Design (IOLTS'2018), Platja d'Aro, SPAIN, 2 au 4 juillet 2018
 
 3 Mkhinini A., Maistri P., Leveugle R., Tourki R., HLS Design of a Hardware Accelerator for Homomorphic Encryption, IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS 2017), Dresden, GERMANY, DOI: 10.1109/DDECS.2017.7934578, 19 au 21 avril 2017
 
 4 Mkhinini A., Maistri P., Leveugle R., Tourki R., Machhout M., A flexible RNS-based large polynomial multiplier for Fully Homomorphic Encryption, 11th IEEE International Design & Test Symposium (IDT'16), pp. 131-136, Hammamet, TUNISIA, 18 au 20 décembre 2016
 
 5 Pontié S., Bourge A., Prost-Boucle A., Maistri P., Muller O., Leveugle R., Rousseau F., HLS-based methodology for fast iterative development applied to Elliptic Curve arithmetic, Euromicro/IEEE Conference on Digital System Design (DSD'16), pp. 511-518, Limassol, CYPRUS, DOI: 10.1109/DSD.2016.51, 31 août au 2 septembre 2016
 
 6 Leveugle R., Chahed A., Maistri P., Papadimitriou A., Hély D., Beroulle V., Ammari A., On Fault Injections for Early Security Evaluation vs. Laser-based Attacks, 1st IEEE International Verification and Security Workshop, pp. 33-38, St Feliu de Guixols, SPAIN, 4 au 6 juillet 2016
 
 7 Ananiadis C., Papadimitriou A., Hély D., Beroulle V., Maistri P., Leveugle R., On the development of a new countermeasure on a laser attack RTL fault model, Design, Automation and Test in Europe Conference (DATE'16), Dresden, GERMANY, 14 au 18 mars 2016
 
 8 Jayet-Griffon C., Cornelie M.-A., Maistri P., Elbaz-Vincent P., Leveugle R., Polynomial multipliers for Fully Homomorphic Encryption on FPGA, International Conference on ReConFigurable Computing and FPGAs (ReConFig'15), Mayan Riviera, MEXICO, 7 au 9 décembre 2015
 
 9 Papadimitriou A., Tampas M., Hély D., Beroulle V., Maistri P., Leveugle R., Validation of RTL laser fault injection model with respect to layout information, IEEE International Symposium on Hardware Oriented Security and Trust (HOST'15), pp. 78-81, McLean, VA, UNITED STATES, 5 au 7 mai 2015
 
10 Papadimitriou A., Hély D., Beroulle V., Maistri P., Leveugle R., Analysis of laser-induced errors: RTL fault model versus layout locality characteristics, Third Workshop on Trustworthy Manufacturing and Utilization of Secure Devices (TRUDEVICE'15), Grenoble, FRANCE, 13 mars 2015
 
11 Pontié S., Maistri P., Leveugle R., Tuning of randomized windows against simple power analysis for scalar multiplication on elliptic curves, Third Workshop on Trustworthy Manufacturing and Utilization of Secure Devices (TRUDEVICE'15), Grenoble, FRANCE, 13 mars 2015
 
12 Bollo M., Maistri P., Composite Fields against Side Channel Analysis for the Advanced Encryption Standard, 21st IEEE International Conference on Electronics Circuits and Systems (ICECS'14), pp. 542-545, Marseille, FRANCE, 7 au 10 décembre 2014
 
13 Maistri P., Leveugle R., Bossuet L., Aubert A., Fischer V., Robisson B., Moro N., Maurine P., Dutertre J.M., Lisart M., Electromagnetic analysis and fault injection onto secure circuits, 22nd IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC'14), pp. 195-200, Playa del Carmen, MEXICO, DOI: 10.1109/VLSI-SoC.2014.7004182, 5 au 8 octobre 2014
 
14 Leveugle R., Maistri P., Vanhauwaert P., Lu F., Di Natale G., Flottes M.-L., Rouzeyre B., Papadimitriou A., Hély D., Beroulle V., Hubert G., De Castro S., Dutertre J.M., Sarafianos A., Boher N., Lisart M., Damiens J., Candelier P., Tavernier C., Laser-induced fault effects in security-dedicated circuit, 22nd IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC'14), pp. 201-206, Playa del Carmen , MEXICO, DOI: 10.1109/VLSI-SoC.2014.7004184 , 5 au 8 octobre 2014
 
15 Pontié S., Maistri P., Leveugle R., An Elliptic Curve Crypto-Processor Secured by Randomized Windows, Digital System Design (DSD), 2014 17th Euromicro Conference on, pp. 535 - 542, Verona, ITALY, DOI: 10.1109/DSD.2014.18, 27 au 28 août 2014
 
16 Pontié S., Maistri P., Design of a secure architecture for scalar multiplication on elliptic curves, 10th Conference on Ph.D Research in Microelectronics and Electronics (PRIME'14), Grenoble, FRANCE, DOI: 10.1109/PRIME.2014.6872655, 30 juin au 3 juillet 2014
 
17 Pontié S., Maistri P., Randomized Windows for a Secure Crypto-Processor on Elliptic Curves, 25th IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP 2014), Zurich, SWITZERLAND, 18 au 20 juin 2014
 
18 Alberto D., Maistri P., Leveugle R., Electromagnetic attacks on embedded devices: a model of probe-circuit power coupling, 9th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS'14), pp. 23-28 , Santorini, GREECE, DOI: 10.1109/DTIS.2014.6850648, 6 au 8 mai 2014
 
19 Papadimitriou A., Hély D., Beroulle V., Maistri P., Leveugle R., A multiple fault injection methodology based on cone partitioning towards RTL modeling of laser attacks, Design, Automation and Test in Europe Conference (DATE'14) Germany, Dresden, GERMANY, DOI: 10.7873/DATE2014.219, 24 mars 2014
 
20 Maistri P., Tiran S., Maurine P., Koren I., Leveugle R., Countermeasures against EM analysis for a secured FPGA-based AES implementation, International Conference on ReConFigurable Computing and FPGAs (ReConFig'13), pp. 1-6, Cancun, MEXICO, DOI: 10.1109/ReConFig.2013.6732274, 9 au 11 décembre 2013
 
21 Maistri P., Tiran S., Maurine P., Koren I., Leveugle R., An evaluation of an AES implementation protected against EM analysis, 23rd ACM international conference on Great lakes symposium on VLSI (GLSVLSI'13), pp. 317-318 , Paris, FRANCE, DOI: 10.1145/2483028.2483120, 2 au 3 mai 2013
 
22 Maistri P., Masson F., Leveugle R., Implementation of the Advanced Encryption Standard on GPUs with the NVIDIA CUDA framework, IEEE Symposium on Industrial Electronics & Applications (ISIEA'11), pp. 213-217 , Langkawi, MALAYSIA, 25 au 28 septembre 2011
 
23 Maistri P., Leveugle R., 10-gigabit throughput and low area for a hardware implementation of the Advanced Encryption Standard, 14th Euromicro/IEEE Conference on Digital System Design (DSD'11), pp. 266-269, Oulu, FINLAND, DOI: 10.1109/DSD.2011.37 , 31 août au 2 septembre 2011
 
24 Leveugle R., Ben Jrad M., Maistri P., Towards Virtual Fault-based Attacks for Security Validation, IARIA Fourth International Conference on Dependability (DEPEND'11), pp. 1-6, Nice, FRANCE, 21 au 27 août 2011
 
25 Canivet G., Maistri P., Leveugle R., Valette F., Clédière J., Renaudin M., Dependability analysis of a countermeasure against fault attacks by means of laser shots onto a SRAM-based FPGA, International Conference on Application-specific Systems, Architectures and Processors (ASAP'10), pp. 115-122, Rennes, FRANCE, 7 au 9 juillet 2010
 
26 Canivet G., Maistri P., Leveugle R., Valette F., Clédière J., Renaudin M., Robustness evaluation and improvements under laser-based fault attacks of an AES crypto-processor implemented on a SRAM-based FPGA, IEEE European Test Symposium (ETS'10), pp. 251, Prague, CZECH REPUBLIC, DOI: 10.1109/ETSYM.2010.5512740 , 24 au 28 mai 2010
 
27 Maistri P., Leveugle R., Toward automated fault pruning with Petri nets, International on-line Testing Symposium (IOLTS’09), pp. 41-46, Sesimbra-Lisbon, PORTUGAL, DOI: 10.1109/IOLTS.2009.5195981, 24 au 26 juin 2009
 
28 Leveugle R., Calvez A., Maistri P., Vanhauwaert P., Statistical Fault Injection: Quantified Error and Confidence , Design, Automation and Test in Europe (DATE '09), pp. 502-506 , Nice, FRANCE, 20 au 24 avril 2009
 
29 Leveugle R., Calvez A., Vanhauwaert P., Maistri P., Precisely Controlling the Duration of Fault Injection Campaigns: a Statistical View , International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS’09), pp. 149-154 , Cairo, EGYPT, 6 au 7 avril 2009
 
30 Leveugle R., Pierre L., Maistri P., Clavel R., Soft Error Effect and Register Criticality Evaluations: Past, Present and Future, Workshop on Silicon Errors in Logic - System Effects (SELSE’09), pp. 15-20 , Stanford, Ca., UNITED STATES, 24 au 25 mars 2009
 
31 Maistri P., Pruning Single Event Upset Faults with Petri Nets, Latin-American Test Workshop (LATW’09), pp. 1-6, Armacao de Buzios, BRAZIL, DOI: 10.1109/LATW.2009.4813785, 2 au 5 mars 2009
 
32 Leveugle R., Calvez A., Vanhauwaert P., Maistri P., Statistical fault injection: how much is sufficient?, 2nd IFIP International Workshop on Dependable Circuit Design (DECIDE'08), Playa del Carmen, MEXICO, 27 au 29 novembre 2008
 
33 Maistri P., Excoffon C., Leveugle R., Software BIST capabilities of a symmetric cipher, International Conference on Electronics, Circuits and Systems (ICECS'08), pp. 414-417, Saint Julians, MALTA, 1 au 3 septembre 2008
 
34 Maistri P., Excoffon C., Leveugle R., Software self-testing of a symmetric cipher with error detection capability, 14th IEEE International On-Line Testing Symposium (IOLTS'08), pp. 79-84, Rhodes, GREECE, DOI: 10.1109/IOLTS.2008.33, 6 au 9 juillet 2008
 
35 Excoffon C., Maistri P., Leveugle R., Software-based BIST capabilities of the Advanced Encryption Standard, Electronic Symposium Digest of 13th IEEE European Test Symposium (ETS'08), Verbania, ITALY, 25 au 29 mai 2008
 
36 Maistri P., Leveugle R., Multi-cycle Fault Injections in Error Detecting Implementations of the Advanced Encryption Standard, International Design and Test Workshop (IDT’07), pp. 15-20, Cairo, EGYPT, 16 au 18 décembre 2007
 
37 Maistri P., Vanhauwaert P., Leveugle R., Evaluation of register-level protection techniques for the Advanced Encryption Standard by multi-level fault injections, International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT’07), pp. 499-507, Rome, ITALY, 26 au 28 septembre 2007
 
38 Maistri P., Vanhauwaert P., Leveugle R., A novel double-data-rate AES architecture resistant against fault injection, Workshop on Fault Diagnosis and Tolerance in Cryptography (FDTC’07), pp. 54-61, Vienna, AUSTRIA, DOI: 10.1109/FDTC.2007.4318985, 10 septembre 2007
 
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1 Chapitres de livre

1 Beroulle V., Candelier P., De Castro S., Di Natale G., Dutertre J.M., Flottes M.-L., Hély D., Hubert G., Leveugle R., Lu F., Maistri P., Papadimitriou A., Rouzeyre B., Tavernier C., Vanhauwaert P., Laser-induced fault effects in security-dedicated circuits, VLSI-SoC: Internet of Things Foundations, L. Claesen, M.-T. Sanz-Pascual, R. Reis, A. Sarmiento-Reyes (Eds.) , Ed. Elsevier, pp. 220-240, Vol. 464, 2015
 
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3 Conférences nationales

1 Reynaud V., Maistri P., Leveugle R., Accès autorisé au réseau reconfigurable de test par ensemble de segments, 13ème Colloque du GDR SoC/SiP, Paris, FRANCE, 13 au 15 juin 2018
 
2 Mkhinini A., Maistri P., Leveugle R., Chiffrement homomorphique : entre développements théoriques et implantations pratiques, 8ème Colloque du GdR SoC-SiP, Paris, FRANCE, 11 au 13 juin 2014
 
3 Papadimitriou A., Hély D., Beroulle V., Maistri P., Leveugle R., FPGA emulation of laser attacks against secure deep submicron integrated circuits, 7ème Colloque du GdR SoC-SiP, Lyon, FRANCE, 10 au 12 juin 2013
 
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6 Autres communications

1 Maistri P., Dutertre J.M., Leveugle R., Laser Attacks against DDR Redundancy, Workshop on SecURity, REliAbiLity, test, prIvacy, Safety and Trust of Future Devices (SURREALIST'2018), Bremen, GERMANY, 2018
 
2 Maistri P., Hardware Design of Error Detection Schemes for Symmetric Ciphers, Séminaire sécurité des systèmes électroniques embarqués, Rennes, FRANCE, 2016
 
3 Papadimitriou A., Hély D., Beroulle V., Maistri P., Leveugle R., FPGA emulation of laser attacks against secure deep submicron integrated circuits, Second Workshop on Trustworthy Manufacturing and Utilization of Secure Devices (TRUDEVICE'14), Paderborn, GERMANY, 2014
 
4 Alberto D., Maistri P., Leveugle R., Investigation of Electromagnetic Fault Injection Effects on Embedded Cryptosystems, First Workshop on Trustworthy Manufacturing and Utilization of Secure Devices (TRUDEVICE'13), pp. 1-2, Avignon, FRANCE, 2013
 
5 Maistri P., Leveugle R., Early pruning of soft errors and transient faults with Petri netS, Electronic Symposium Digest of European Test Symposium (ETS'09), Sevilla, SPAIN, 2009
 
6 Maistri P., AES Secured Architecture and Auto-Test Capabilities, PAca Security Trends In embedded Security (PASTIS’08), Gardanne, FRANCE, 2008
 
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1 Rapports

1 Maistri P., Pruning Single Event Upset Faults with Petri Nets , ISRN: TIMA-RR--09/03-02-FR, 1 janvier 2009
 
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