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159 résultats

   14 Revues internationales
   16 Conférences invitées
  105 Conférences internationales
    5 Chapitres de livre
    2 Livres & Éditions Ouvrages
    6 Conférences nationales
    1 Autres communications
    8 Rapports
    2 Thèses

14 Revues internationales

 1 Anghel L., Benabdenbi M., Bosio A., Traiola M., Vatajelu I., Test and Reliability in Approximate Computing, Journal of Electronic Testing: Theory and Applications, Ed. Springer , Vol. 34, No. 4, pp. 375-387, DOI: 10.1007/s10836-018-5734-9, août 2018
 
 2 Alexandrescu D., Altun M., Anghel L., Ciriani V., Tahoori M., Bernasconi A., Logic synthesis and testing techniques for switching nano-crossbar arrays, Microprocessors and Microsystems, Ed. Elsevier, Vol. 54, pp. 14-25, DOI: 10.1016/j.micpro.2017.08.004, octobre 2017
 
 3 Deng E., Prenat G., Anghel L., Non-Volatile Magnetic Decider Based on Magnetic Tunnel Junctions, Electronics Letters, Ed. IEEE, Vol. , 2016
 
 4 Ottavi M., Pontarelli S., Gizopoulos D., Bolchini C., Michael M.K., Anghel L., Tahoori M., Paschalis A., Reviriego P., Bringmann O., Izosimov V., Manhaeve H., Strydis C., Hamdioui S., Dependable Multicore Architectures at Nanoscale: The View From Europe , IEEE Design & Test, Ed. IEEE, Vol. 32, No. 2, pp. 17-28, DOI: 10.1109/MDAT.2014.2359572, avril 2015
 
 5 Dimopoulos M., Gang Yi, Anghel L., Benabdenbi M., Zergainoh N.-E., Nicolaidis M., Fault-Tolerant Adaptive Routing under an Unconstrained Set of Node and Link Failures for Many-Core Systems-on-Chip, Microprocessors and Microsystems, Ed. Elsevier, Vol. 38, No. 6, pp. 620–635, DOI: 10.1016/j.micpro.2014.04.003, août 2014
 
 6 Frank T., Moreau S., Chappaz C., Leduc P., Arnaud L., Thuaire A., Chery E., Lorut F., Anghel L., Poupon G., Reliability of TSV interconnects: Electromigration, thermal cycling, and impact on above metal level dielectric, Microelectronics Reliability, Ed. Elsevier, Vol. 53, No. 1, pp. 17-29, DOI: 10.1016/j.microrel.2012.06.021, janvier 2013
 
 7 Pasca V., Anghel L., Benabdenbi M., Kth-Aggressor Fault (KAF)-based Thru-Silicon-Via Interconnect Built-In Self-Test and Diagnosis, Journal of Electronic Testing: Theory and Applications, Ed. Springer , Vol. 28 , No. 6, pp. 817-829, DOI: 10.1007/s10836-012-5322-3, décembre 2012
 
 8 Pasca V., Anghel L., Nicolaidis M., Benabdenbi M., CSL: Configurable Fault Tolerant Serial Links for Inter-die Communication in 3D Systems , Journal of Electronic Testing: Theory and Applications, Ed. Springer , Vol. 28, No. 1, pp. 137-150, DOI: 10.1007/s10836-011-5260-5, février 2012
 
 9 Rusu C., Anghel L., Avresky D., Adaptive inter-layer message routing in 3D networks-on-chip, Microprocessors and Microsystems, Ed. Elsevier, Vol. 35, No. 7, pp. 613-631, DOI: 10.1016/j.micpro.2011.06.008, octobre 2011
 
10 O'Connor I., Liu J., Gaffiot F., Pregaldiny F., Manneux C., Lallement C., Goguet J., Fregonese S., Zimmer T., Anghel L., Leveugle R., Dang T., CNTFET modeling and reconfigurable logic circuit design, IEEE Transactions on Circuits and Systems, Ed. IEEE, Vol. 54, No. 11, pp. 2365-2379, DOI: 10.1109/TCSI.2007.907835 , novembre 2007
 
11 Lazzari C., Anghel L., Reis R., A Case Study on Phase-Locked Loop Automatic Layout Generation and Transient Fault Injection Analysis, Journal of Electronic Testing: Theory and Applications, Ed. Springer , Vol. 23, No. 6, pp. 625-633, DOI: 10.1007/s10836-007-5055-x, juin 2007
 
12 Nicolaidis M., Anghel L., Achouri M.N., Memory Defect Tolerance Architectures for Nanotechnologies, Journal of Electronic Testing: Theory and Applications, Ed. Springer , Vol. 21, No. 4, pp. 445 - 455, DOI: 10.1007/s10836-005-0971-0, janvier 2005
 
13 Alexandrescu D., Anghel L., Nicolaidis M., Simulating single event transients in VDSM ICs for ground level radiation, Journal of Electronic Testing: Theory and Applications, Ed. Springer , Vol. 20, No. 4, pp. 413-21, DOI: 10.1023/B:JETT.0000039608.48856.33, août 2004
 
14 Nicolaidis M., Anghel L., Concurrent checking for VLSI, Microelectronic Engineering, Ed. Elsevier, Vol. 49, No. 1-2, pp. 139-156, DOI: 10.1016/S0167-9317(99)00435-9, novembre 1999
 
remonter

16 Conférences invitées

 1 Anghel L., Run-time Age Induced Reliability Prediction for SOC, Invited Talk, IEEE Latin America Test Symposium (LATS 2019), Santiago de Chile, CHILI, 11 au 13 mars 2019
 
 2 Anghel L., Benabdenbi M., Bosio A., Vatajelu I., Test and reliability in approximate computing, Invited paper, Mixed Signals Testing Workshop (IMSTW 2017), Thessaloniki, GREECE, DOI: 10.1109/IMS3TW.2017.7995210, 3 au 5 juillet 2017
 
 3 Anghel L., Portolan M., Managing Wear out and Variability Monitors: IEEE 1687 to the Rescue, Keynote talk, East West Design and test Symposium, Yerevan, ARMENIA, 13 au 16 octobre 2016
 
 4 Anghel L., System Failure Prediction with On-Chip Monitors, Plenary talk, Colloque National 2016 de GDR SOC-SIP, Nantes, FRANCE, 7 au 8 mai 2016
 
 5 Anghel L., Moniteurs de fiabilité embarqués en technologie FDSOI: Implémentation et Applications, Invited Talk, Ecole d'hiver Francophone sur les Technologies de Conception des Systèmes Embarqués Hétérogènes (FETCH'16), Vilard de Lans, FRANCE, 4 au 7 janvier 2016
 
 6 Anghel L., Reliability Measurements with In Situ Aging Monitors in FDSOI Technology, Invited talk (Elevator talk), International Test Conference (ITC'15), Anaheim, UNITED STATES, 6 au 8 octobre 2015
 
 7 Anghel L., New Approaches in Soft Errors Fault Tolerant Design for digital circuits based on Double Sampling Techniques, Invited Talk, Ecole d'hiver Francophone sur les Technologies de Conception des Systèmes embarqués Hétérogènes (FETCH'14), Ottawa, CANADA, 8 au 10 janvier 2014
 
 8 Anghel L., On the Dependability of 3D Interconnects, Ecole d'hiver Francophone sur les Technologies de Conception des Systèmes embarqués Hétérogènes (FETCH'12), Alpes d'Huez, FRANCE, 9 au 12 janvier 2012
 
 9 Anghel L., Huard V., Designing cost-effective robust systems by accurate reliability modeling, IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT’11), Vancouver, CANADA, 3 octobre 2011
 
10 Nicolaidis M., Anghel L., Pasca V., On the dependability of 3D interconnects, Keynote in the Opening Session, Deep-submicron Technologies Workshop (DDT’11), European Test Symposium (ETS), Trondheim, NORWAY, 27 au 28 mai 2011
 
11 Anghel L., Ferron J.B., Leveugle R., Criticality of Configuration Bits in SRAM-based FPGAs: Predictive Analysis and Experimental Results, Workshop on Design for Reliability and Variability (DRVW’11), Dana Point, CA, UNITED STATES, 4 au 5 mai 2011
 
12 Anghel L., Technology roadmap and evolutions: challenge and criticality, Invited Talk, RADPRED Workshop, Toulouse, FRANCE, 14 au 15 janvier 2010
 
13 Anghel L., Rusu C., Multi-level Fault Tolerance in 2D and 3D NoCs, Invited Talk, Workshop international “NOC in Space Applications Round Table”, European Space Agency, Noordwijk, NETHERLANDS, 17 au 18 septembre 2009
 
14 Anghel L., Nicolaidis M., Defects Tolerant Logic Gates for Unreliable Future Nanotechnologies, Invited talk (Special Session), International Work-Conference on Artificial Neural Networks (IWANN’07), San Sebastian, SPAIN, 20 au 22 juin 2007
 
15 Anghel L., SET and SEU effects at multiple abstraction levels, Single Event Effects Symposium (SEE'06), Long Beach, CA, UNITED STATES, 1 au 2 juin 2006
 
16 Anghel L., Leveugle R., Vanhauwaert P., Evaluation of SET and SEU effects at multiple abstraction levels, 11th IEEE International On Line Testing Symposium (IOLTS'05), pp. 309-12, St Raphael, FRANCE, DOI: 10.1109/IOLTS.2005.28, 6 au 8 juillet 2005
 
remonter

105 Conférences internationales

  1 Shah R., Cacho F., Anghel L., Aging Investigation of Digital Circuits using In-Situ Monitors, IEEE International Integrated Reliability Workshop (IIRW 2019), Stanford Sierra, Fallen Leaf Lake, UNITED STATES, 13 au 17 octobre 2019
 
  2 Vatajelu I., Di Natale G., Anghel L., Special Session: Reliability of Hardware-Implemented Spiking Neural Networks (SNN), IEEE VLSI Test Symposium (VTS 2019), Monterey, UNITED STATES, 23 au 25 avril 2019
 
  3 Di Natale G., Vatajelu I., Senthamarai Kannan K., Anghel L., Hidden-Delay-Fault Sensor for Test, Reliability and Security, IEEE Design Automation and Test Conference in Europe (DATE 2019), Florence, ITALY, 25 au 29 mars 2019
 
  4 Anghel L., Di Natale G., Miramond B., Vatajelu I., Vianello E., Neuromorphic Computing - From Robust Hardware Architectures to Testing Strategies, 26th IFIP IEEE International Conference on Very Large Scale Integration (VLSI SOC 2018), Verona, ITALY, 8 au 10 octobre 2018
 
  5 Morgül Muhammed Ceylan, Frontini L., Vatajelu I., Anghel L., Integrated Synthesis Methodology for Crossbar Arrays, IEEE NANOARCH'2018, Athens, GREECE, 18 au 19 juillet 2018
 
  6 Vatajelu I., Anghel L., Portal J.-M., Bocquet M., Prenat G., Resistive and Spintronic RAMs: Device, Simulation, and Applications, IEEE International On Line Testing (IOLTS'2018), Platja d'Aro, SPAIN, 2 au 4 juillet 2018
 
  7 Sivadasan A., Shah R., Cacho F., Anghel L., NBTI aged cell rejuvenation with back biasing and resulting critical path reordering for digital circuits in 28nm FDSOI, Design Automation and Test in Europe (DATE'2018), Dresden, GERMANY, 19 au 23 mars 2018
 
  8 Shah R., Cacho F., Anghel L., Investigation of speed sensors accuracy for process and aging compensation, IEEE International reliability Physics Symposium (IRPS'2018), San Francisco, UNITED STATES, 11 au 15 mars 2018
 
  9 Vatajelu I., Anghel L., Fully-Connected Single-Layer STT-MTJ-based Spiking Neural Network under Process Variability, ACM/IEEE International Symposium on Nanoscale Architectures (NANOARCH 2017), Newport, RI, UNITED STATES, 25 au 29 juillet 2017
 
 10 Cacho F., Benhassain A., Shah R., Huard V., Anghel L., Investigation of critical path selection for in-situ monitors insertion, 23rd International Symposium on On-Line Testing and Robust System Design (IOLTS 2017), pp. 247-252, Thessaloniki, GREECE, 3 au 5 juillet 2017
 
 11 Vatajelu I., Anghel L., Reliability Analysis of MTJ-based Functional Module for Neuromorphic Computing, International Symposium on On-Line Testing and Robust System Design (IOLTS 2017), Thessaloniki, GREECE, 3 au 5 juin 2017
 
 12 Sivadasan A., Benhassain A., Huard V., Cacho F., Anghel L., Architecture and Workload Dependant Digital Failure Rate, IEEE International Reliability for Physics of Semiconductors (IRPS 2017), Monterey, UNITED STATES, 2 au 6 avril 2017
 
 13 Sivadasan A., Huard V., Anghel L., Worload Dependent Reliability Timing Analysis Flow, DATE 2017, Lausanne, SWITZERLAND, 27 au 29 mars 2017
 
 14 Alexandrescu D., Altun M., Anghel L., Bernasconi A., Ciriani V., Frontini L., Tahoori M., Synthesis and Performance Optimization of a Switching Nano-crossbar Computer, Euromicro Conference on Digital System Design (Euromicro DSD/SEAA'16), Limassol, CYPRUS, 31 août au 2 septembre 2016
 
 15 Deng E., Prenat G., Anghel L., Zhao W., Multi-context Non-volatile Content Addressable Memory Using Magnetic Tunnel Junctions, 12th ACM/IEEE International Symposium on Nanoscale Architectures (NANOARCH'16), Beijing, CHINA, 18 au 20 juillet 2016
 
 16 Benhassain A., Mhira S., Cacho F., Huard V., Anghel L., In-Situ Slack Monitors : Taking up the Challenge of On-die Monitoring of Variability and Reliability, International Verification and Security Workshop, Sant Feliu de Guixols, SPAIN, 4 au 7 juillet 2016
 
 17 Thole N., Anghel L., Fey G., A Hybrid Algorithm to Conservatively Check the Robustness of Circuits, IEEE European Test Symposium (ETS'16), Amsterdam, NETHERLANDS, 23 au 26 mai 2016
 
 18 Anghel L., Benhassain A., Sivadasan A., Early system failure prediction by using aging in situ monitors: Methodology of implementation and application results, IEEE 34th VLSI Test Symposium (VTS'16), Las Vegas, NE, UNITED STATES, DOI: 10.1109/VTS.2016.7477316, 25 au 27 avril 2016
 
 19 Benhassain A., Cacho F., Huard V., Mhira S., Anghel L., Parthasarathy C., Jain A., Sivadasan A., Robustness of Timing in-situ Monitors for AVS Management, IEEE International Reliability Physics Semiconductor (IRPS'16), Passadena, UNITED STATES, 17 au 21 avril 2017
 
 20 Benhassain A., Cacho F., Huard V., Anghel L., Early failure prediction by using in-situ monitors: Implementation and application results, Workshop on Early Reliability Modeling for Aging and Variability in Silicon Systems, Dresden, GERMANY, 18 mars 2016
 
 21 Sivadasan A., Cacho F., Benhassain A., Huard V., Anghel L., Workload Impact on BTI HCI Induced Aging of Digital Circuits: A System level Analysis, Workshop on Early Reliability Modeling for Aging and Variability in Silicon Systems, Dresden, GERMANY, 18 mars 2016
 
 22 Sivadasan A., Cacho F., Benhassain A., Huard V., Anghel L., Study of workload impact on BTI HCI induced aging of digital circuits, Design Automation and Test in Europe (DATE'16), Dresden, GERMANY, 14 au 17 mars 2016
 
 23 Benhassain A., Cacho F., Huard V., Saliva M., Anghel L., Parthasarathy C., Jain A., Giner F., Timing in-situ monitors: Implementation strategy and applications results, IEEE Custom Integrated Circuits Conference (ICICC'16), San Jose, CA, UNITED STATES, 28 au 30 septembre 2015
 
 24 Rehman Saif-Ur, Benabdenbi M., Anghel L., Application-independent testing of multilevel interconnect in mesh-based FPGAs, IEEE 10th International Conference on Design and Technologies for Integrated System in Nanoscale (DTIS'15), pp. 1-6, Naples, ITALY, DOI: 10.1109/DTIS.2015.7127383, 21 au 23 avril 2015
 
 25 Saliva M., Cacho F., Ndiaye C., Huard V., Angot D., Bravaix A. , Anghel L., Impact of Gate Oxide Breakdown in Logic Gates from 28nm FDSOI CMOS technology, IEEE International Reliability Physics Symposium (IRPS'15), pp. CA.4.1 - CA.4.6 , Monterrey, CA, UNITED STATES, DOI: 10.1109/IRPS.2015.7112782, 19 au 23 avril 2015
 
 26 Saliva M., Cacho F., Huard V., Federspiel X., Angot D., Benhassain A., Bravaix A. , Anghel L., Digital circuits reliability with in-situ monitors in 28nm fully depleted SOI, Design, Automation & Test in Europe Conference & Exhibition (DATE'15), pp. 441-446, Grenoble, FRANCE, 9 au 13 mars 2015
 
 27 Steininger A., Veeravalli V.S., Alexandrescu D., Costenaro E., Anghel L., Exploring the state dependent SET sensitivity of asynchronous logic - The muller-pipeline example, 32nd IEEE International Conference on Computer Design (ICCD'14), pp. 61-67, Seoul, KOREA, DOI: 10.1109/ICCD.2014.6974663, 19 au 22 octobre 2014
 
 28 Rehman Saif-Ur, Blanchardon A., Ben Dhia A., Benabdenbi M., Chotin-Avot R., Naviner L., Anghel L., Mehrez H., Amouri E., Marrakchi Z., Impact of Cluster Size on Routability, Testability and Robustness of a Cluster in a Mesh FPGA, IEEE Computer Society Annual Symposium on VLSI (ISVLSI'14), pp. 553-558, Tampa, FL, UNITED STATES, DOI: 10.1109/ISVLSI.2014.66, 9 au 11 juillet 2014
 
 29 Rehman Saif-Ur, Benabdenbi M., Anghel L., Cost-efficient of a cluster in a mesh SRAM-based FPGA, IEEE 20th International On-Line Testing Symposium (IOLTS'14), pp. 75-80, Platja d'Aro, Girona, SPAIN, DOI: 10.1109/IOLTS.2014.6873675, 7 au 9 juillet 2014
 
 30 Saliva M., Cacho F., Huard V., Angot D., Durand M., Federspiel X., Parra M., Bravaix A. , Anghel L., Blanc-Benon P., New Insight about Oxide Breakdown Occurrence at Circuit Level, IEEE International Reliability Physics Symposium (IRPS'14), Waikoloa, HI, UNITED STATES, 1 au 5 juin 2014
 
 31 Anghel L., Veeravalli V.S., Alexandrescu D., Steininger A., Schneider-Hornstein K., Costenaro E., Single Event Effects in Muller C-Elements and Asynchronous Circuits Over a Wide Energy Spectrum, The 10th IEEE Workshop on Silicon Errors in Logic - System Effects (SELSE'14), Stanford, UNITED STATES, 1 au 2 avril 2014
 
 32 Dimopoulos M., Gang Yi, Benabdenbi M., Anghel L., Efficient Fault-Tolerant Adaptive Routing under an unconstrained Set of Node and Link Failures for Many Cores System On Chip, Workshop on Dependable Multicore and Transactional Memory Systems (DMTM'14), (joint to HIPEAC event), pp. 1-2, Vienna, AUSTRIA, 22 janvier 2014
 
 33 Rehman Saif-Ur, Benabdenbi M., Anghel L., BIST for Logic and Local Interconnect Resources in a Novel Mesh of Cluster FPGA, IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT'13), pp. 296 - 301 , New York, NY, UNITED STATES, DOI: 10.1109/DFT.2013.6653622, 2 au 4 octobre 2013
 
 34 Gang Yi, Dimopoulos M., Benabdenbi M., Anghel L., Zergainoh N.-E., Nicolaidis M., Fault-tolerant adaptive routing under static and run-time, permanent and transient failures for many-core systems-on-chip, IEEE International On-Line Testing symposium (IOLTS'13), pp. 7 - 12 , Chania, CRETE, DOI: 10.1109/IOLTS.2013.6604043, 8 au 10 juillet 2013
 
 35 Nicolaidis M., Pasca V., Anghel L., Through-Silicon-Via Built-In Self-Repair for Aggressive 3D Integration, International On-Line Testing Symposium (IOLTS’12), pp. 91-96, Sitges, SPAIN, DOI: 10.1109/IOLTS.2012.6313847, 27 au 29 juin 2012
 
 36 Frank T., Chappaz C., Arnaud L., Moreau S., Leduc P., Thuaire A., Anghel L., Electromigration Behavior of 3D-IC TSV Interconnects, 62nd Electronic Components and Technology Conference (ECTC'12), pp. 326 - 330, San Diego, CA, UNITED STATES, DOI: 10.1109/ECTC.2012.6248850, 29 mai au 2 juin 2012
 
 37 Pasca V., Rehman Saif-Ur, Anghel L., Benabdenbi M., Efficient link-level error resilience in 3D NoCs , IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS'12) , pp. 127 - 132 , Tallinn , ESTONIA, DOI: 10.1109/DDECS.2012.6219038, 18 au 20 avril 2012
 
 38 Huard V., Pion E., Cacho F., Croain D., Robert V., Delater R., Mergault P., Engels S., Anghel L., Ruiz Amador N., A predictive bottom-up hierarchical approach to digital system reliability , IEEE International Reliability Physics Symposium (IRPS'12), Anaheim, CA, UNITED STATES, DOI: 10.1109/IRPS.2012.6241830, 15 au 19 avril 2012
 
 39 Frank T., Chappaz C., Arnaud L., Federspiel X., Colella F., Petitprez E., Anghel L., Electromigration degradation mechanism analysis of SnAgCu interconnects for eWLB package , International Reliability Physics Symposium (IRPS'12), Anaheim, CA, UNITED STATES, DOI: 10.1109/IRPS.2012.6241792, 15 au 19 avril 2012
 
 40 Nicolaidis M., Anghel L., Zergainoh N.-E., Zorian Y., Karnik T., Bowman K., Tschanz J., Lu S.-L., Tokunaga C., Raychowdhury A., Khellah M., Kulkarini J., Vivek De, Avresky D., Design for Test and Reliability in Ultimate CMOS, Design, Automation and Test in Europe (DATE'12), pp. 677-682, Dresden, GERMANY, 12 au 16 mars 2012
 
 41 Nicolaidis M., Anghel L., Zergainoh N.-E., Avresky D., Designing Single Chip Massively Parallel Processors Affected by Extreme Failure Rates, Design, Automation & Test in Europe Conference & Exhibition (DATE'12), Dresden, GERMANY, 12 au 16 mars 2012
 
 42 Ferron J.B., Anghel L., Leveugle R., Towards Low-cost Soft Error Mitigation in SRAM-based FPGAs: a Case Study on AT40K, 3rd IEEE Latin American Symposium on Circuits and Systems (LASCAS'12), Playa del Carmen, MEXICO, 29 février au 2 mars 2012
 
 43 Ferron J.B., Anghel L., Leveugle R., Analysis of configuration bit criticality in designs implemented with SRAM-based FPGAs, IEEE Symposium on Industrial Electronics & Applications (ISIEA('12), pp. 83-88 , Langkawi, MALAYSIA, 25 au 28 septembre 2011
 
 44 Ruiz Amador N., Huard V., Pion E., Cacho F., Croain D., Robert V., Engels S., Flatresse P., Anghel L., Bottom-up digital system-level reliability modeling , Custom Integrated Circuits Conference (CICC'11), pp. 1 - 4 , San Jose, CA, UNITED STATES, DOI: 10.1109/CICC.2011.6055343 , 19 au 21 septembre 2011
 
 45 Frank T., Chappaz C., Leduc P., Arnaud L., Moreau S., Thuaire A., Lorut F., Anghel L., Electromigration Behavior of 3D-IC TSV, Second IEEE International Workshop on Testing Three-Dimensional Stacked Integrated Circuits (3D IC'11), in conjuction with ITC, Anaheim, UNITED STATES, 18 au 23 septembre 2011
 
 46 Fradi A., Nicolaidis M., Anghel L., Memory BIST with address programmability , IEEE international On Line Testing Symposium (IOLTS'11), pp. 79 - 85 , Athenes, GREECE, DOI: 10.1109/IOLTS.2011.5993815 , 13 au 15 juillet 2011
 
 47 Yu H., Nicolaidis M., Anghel L., Zergainoh N.-E., Efficient Fault Detection Architecture Design of Latch-Based Low Power DSP/MCU Processor , 16th IEEE European Test Symposium (ETS'11), pp. 93 - 98 , Trondheim, NORWAY, DOI: 10.1109/ETS.2011.20 , 23 au 27 mai 2011
 
 48 Nicolaidis M., Pasca V., Anghel L., Interconnect Built-In Self-Repair and Adaptive Serialization (I-BIRAS) in 3D Integrated Systems, 16th IEEE European Test Symposium (ETS'11), pp. 208 - 208 , Trondheim, NORWAY, DOI: 10.1109/ETS.2011.37 , 23 au 27 mai 2011
 
 49 Frank T., Chappaz C., Leduc P., Arnaud L., Moreau S., Thuaire A., El Farhane R., Lorut F., Anghel L., Resistance Increase Due to Electromigration Induced Depletion Under TSV , IEEE International Reliability Physics Symposium (IRPS’11), Monterey, CA, UNITED STATES, DOI: 10.1109/IRPS.2011.5784499 , 10 au 14 avril 2011
 
 50 Pasca V., Anghel L., Benabdenbi M., Configurable Thru-Silicon-Via interconnect Built-In Self-Test and diagnosis , IEEE Latin America Test Symposium Workshop (LATW’11), pp. 1-6, Porto de Galinhas (PE), BRAZIL, DOI: 10.1109/LATW.2011.5985896 , 27 au 30 mars 2011
 
 51 Frank T., Chappaz C., Leduc P., Arnaud L., Moreau S., Thuaire A., El Farhane R., Anghel L., Reliability approach of high density Through Silicon Via (TSV), 12th Electronics Packaging Technology Conference (EPTC’10), pp. 321 - 324 , Singapore, SINGAPORE, DOI: 10.1109/EPTC.2010.5702655 , 8 au 10 décembre 2010
 
 52 Nicolaidis M., Anghel L., Pasca V., I-BIRAS: « Interconnect Built-In Self-Repair and Adaptive-Serialization, International Test Conference Workshop on Test of 3D Stacked Systems (3D-TEST), Austin, TX, UNITED STATES, 4 au 5 novembre 2010
 
 53 Nicolaidis M., Pasca V., Anghel L., Interconnect Built-In Self-Repair and Adaptive-Serialization (I-BIRAS) for 3D integrated systems, IEEE International On-Line Testing Symposium (IOLTS’10), pp. 218 - 218 , Corfu, GREECE, DOI: 10.1109/IOLTS.2010.5560198 , 5 juillet 2010
 
 54 Pasca V., Anghel L., Rusu C., Benabdenbi M., Configurable Serial Fault-Tolerant Link for Communication in 3D Integrated Systems, International On-Line Test Symposium (IOLTS'10), pp. 115-120, Corfu, GREECE, 3 au 7 juillet 2010
 
 55 Rusu C., Anghel L., Avresky D., RILM: Reconfigurable inter-layer routing mechanism for 3D multi-layer networks-on-chip, International On-Line Test Symposium (IOLTS’10), pp. 121-125, Corfu, GREECE, 3 au 7 juillet 2010
 
 56 Pasca V., Anghel L., Benabdenbi M., Fault Tolerant Communication in 3D Integrated Systems, DSN Workshop on Dependable Systems and Networks (WDSN'10), pp. 131-135, Chicago, UNITED STATES, 28 juin 2010
 
 57 Pasca V., Anghel L., Rusu C., Benabdenbi M., Non-regular 3D mesh Networks-on-Chip, DAC Workshop on Diagnostic Services in Network-on-Chips (DSNoC'10), Anaheim, UNITED STATES, 13 juin 2010
 
 58 Pasca V., Anghel L., Rusu C., Benabdenbi M., Configurable Fault-Tolerant Link for Inter-die Communication in 3D on-Chip Networks, European Test Symposium (ETS'10), pp. 258, Prague, CZECH REPUBLIC, 24 au 28 mai 2010
 
 59 Pasca V., Anghel L., Rusu C., Locatelli R., Coppola M., Error Resilience of Inter-Die and Intra-Die Communication with 3D Spidergon STNoC, Design Automation and Test in Europe Conference, (DATE'10), , Germany, pp. 275-278, Dresden, GERMANY, 8 au 12 mars 2010
 
 60 Rusu C., Anghel L., Checkpoint and rollback recovery in network-on-chip based systems, Asia and South Pacific Design Automation Conference (ASP-DAC’10), Taipei, TAIWAN, 18 au 21 janvier 2010
 
 61 Rusu C., Anghel L., Avresky D., Message routing in 3D networks-on-chip, NORCHIP Conference 2009, Trondheim, NORWAY, 16 au 17 novembre 2009
 
 62 Ferron J.B., Anghel L., Leveugle R., Bocquillon A., Miller F., Mantelet G., A methodology and tool for predictive analysis of configuration bit criticality in SRAM-based FPGAs: experimental results, 3rd International Conference on Signals, Circuits & Systems (SCS'09), Djerba, TUNISIA, 6 au 8 novembre 2009
 
 63 Yu H., Nicolaidis M., Anghel L., An Effective Approach to Detect Logic Soft Errors in Digital Circuits Based on GRAAL , International Symposium on Quality of Electronic Design (ISQED’09), pp. 236-240, San Jose, CA, UNITED STATES, DOI: 10.1109/ISQED.2009.4810300, 16 au 18 mars 2009
 
 64 Rusu C., Grecu C., Anghel L., Efficient Coordinated Checkpointing Recovery Schemes for Network-on-Chip based Systems, 2nd International Workshop on Dependable Circuit Design (DECIDE’08), Playa del Carmen, MEXICO, 27 au 29 novembre 2008
 
 65 Grecu C., Ivanov A., Saleh S., Rusu C., Anghel L., Pande P.P., Nuca V., A flexible network-on-chip simulator for early design space exploration , 1st Microsystems and Nanoelectronics Research Conference (MNRC'08), pp. 33-36 , Ottawa, CANADA, DOI: 10.1109/MNRC.2008.4683371, 15 octobre 2008
 
 66 Lazzari C., Assis T., Kastensmidt F., Wirth G., Anghel L., Reis R., An Analysis and Design Technique to Reduce SET Sensitivity in Combinational Integrated Circuits, 16th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-Soc'08), pp. 114-117, Rhodes Island, GREECE, 13 au 15 octobre 2008
 
 67 Rusu C., Grecu C., Anghel L., Communication Aware Recovery Configurations for Networks-on-Chip, 14th IEEE International Symposium On-Line Testing (IOLT’08), pp. 201-206, Rhodes, GREECE, DOI: 10.1109/IOLTS.2008.44 , 7 au 9 juillet 2008
 
 68 Rusu C., Grecu C., Anghel L., Blocking and Non-blocking Checkpointing for Networks-on-Chip, 2nd IEEE Workshop on Dependable and Secure Nanocomputing (WDSN’08), Anchorage, Alaska, UNITED STATES, 27 juin 2008
 
 69 Lazzari C., Assis T., Kastensmidt F., Wirth G., Anghel L., Reis R., SET-Factor: An Analysis and Design Tool to Reduce SET Sensitivity in Integrated Circuits, 13th IEEE European Test Symposium (ETS'08), Verbania, ITALY, 25 au 29 mai 2008
 
 70 Rusu C., Grecu C., Anghel L., Improving the Scalability of Checkpoint Recovery for Networks-on-Chip, IEEE International Symposium on Circuits and Systems (ISCAS’08), pp. 2793-2796, Seattle, Washington, UNITED STATES, DOI: 10.1109/ISCAS.2008.4542037, 18 au 21 mai 2008
 
 71 Rusu C., Grecu C., Anghel L., Coordinated versus Uncoordinated Checkpoint Recovery for Network-on-Chip based Systems, 4th IEEE International Symposium on Electronic Design, Test and Applications (DELTA’08), pp. 32-37, Hong Kong, CHINA, DOI: 10.1109/DELTA.2008.75, 23 au 25 janvier 2008
 
 72 Dang T., Anghel L., Pasca V., Leveugle R., CNTFET-based CMOS-like gates and dispersion of characteristics, International Design and Test Workshop (IDT’07), pp. 151-156, Cairo, EGYPT, 16 au 18 décembre 2007
 
 73 Lazzari C., Lima F., Anghel L., Reis R., Efficient Transistor Sizing for Soft Error Protection in Combinational Logic Circuits, 2nd International Workshop on Dependable Circuit Design (DECIDE’07), Buenos Aires, ARGENTINA, 6 au 7 décembre 2007
 
 74 Lazzari C., Santos Cr., Ziesemer A., Anghel L., Reis R., Efficient Timing Closure with a Transistor Level Design Flow, IFIP International Conference on Very Large Scale Integration (VLSI-SoC'07), pp. 312-315, Atlanta, GA, UNITED STATES, DOI: 10.1109/VLSISOC.2007.4402520, 15 au 17 octobre 2007
 
 75 Grecu C., Anghel L., Pande P.P., Ivanov A., Saleh R., Essential Fault-Tolerance Metrics for NoC Infrastructures, IEEE International On-Line Test Symposium (IOLT’07), pp. 37-42 , Hersonissos-Heraklion, CRETE, DOI: 10.1109/IOLTS.2007.31, 8 au 11 juillet 2007
 
 76 Rusu C., Bougerol A. , Anghel L., Weulerse C., Buard N., Benhammadi S., Renaud N., Wrobel F. , Carriere T., Multiple Event Transient Induced by Nuclear Reactions in CMOS Logic Cells , IEEE International On-Line Testing symposium (IOLTS’07), pp. 137-145, Hersonissos-Heraklion, CRETE, DOI: 10.1109/IOLTS.2007.46, 8 au 11 juillet 2007
 
 77 Anghel L., Nicolaidis M., Defect Tolerant Logic Gates for Unreliable Future Nanotechnologies, International Conference on Artificial Neural Networks (IWANN'07), pp. 422-429, San Sebastian, SPAIN, DOI: 10.1007/978-3-540-73007-1, 20 au 22 juin 2007
 
 78 Dang T., Anghel L., Leveugle R., CNTFET-based logic gates and characteristics, IEEE Silicon Nanoelectronics Workshop (SNW’07), pp. 131-132, Kyoto, JAPAN, 10 au 11 juin 2007
 
 79 Ammari A., Anghel L., Leveugle R., Lazzari C., Reis R., SET fault injection methods in analog circuits: case study, 8th Latin-American Test Workshop (LATW’07), pp. 155-160, Cuzco, PERU, 12 au 14 mars 2007
 
 80 Pouget V., Douin A., Lewis D., Fouillat P., Foucard G., Peronnard P., Maingot V., Ferron J.B., Anghel L., Leveugle R., Velazco R., Tools and methodology development for pulsed laser fault injection in SRAM-based FPGAs, 8th Latin-American Test Workshop (LATW’07), pp. 167-172, Cuzco, PERU, 12 au 14 janvier 2007
 
 81 Dang T., Anghel L., Leveugle R., CNTFET-based logic gates and simulation, IEEE International Design and Test Workshop (IDT’06), Dubai, UNITED ARABIAN EMIRATES, 19 au 20 novembre 2006
 
 82 Dang T., Anghel L., Leveugle R., CNTFET basics and simulation, Design and Test of Integrated Systems (DTIS'06), pp. 28-33, Tunis, TUNISIA, 5 au 7 septembre 2006
 
 83 Lazzari C., Reis R., Anghel L., Phase-Locked Loop Automatic Layout Generation and Transient Fault Injection Analysis: A Case Study, 12th IEEE International On-Line Testing Symposium (IOLT’06), pp. 165-172, Como, ITALY, DOI: 10.1109/IOLTS.2006.48, 10 au 12 juillet 2006
 
 84 Hubert G., Bougerol A. , Miller F., Buard N., Anghel L., Carriere T., Wrobel F. , Gaillard R., Prediction of transients induced by neutrons/protons in CMOS combinational logic cells, 12th IEEE International On-Line Testing Symposium (IOLTS'06) , pp. 1-9, Lake of Como, ITALY, DOI: 10.1109/IOLTS.2006.51, 10 au 12 juillet 2006
 
 85 Lazzari C., Anghel L., Nicolaidis M., Multiple Defects Tolerant Devices for Unreliable Future Nanotechnologies, IEEE Latin American Test Workshop (LATW'06), Buenos Aires, ARGENTINA, 26 au 29 mars 2006
 
 86 Lazzari C., Anghel L., Reis R., On implementing a soft error hardening technique by using an automatic layout generator: case study, 11th IEEE International On Line Testing Symposium (IOLTS'05), pp. 29-34, Saint-Raphaël, FRANCE, DOI: 10.1109/IOLTS.2005.45, 6 au 8 juillet 2005
 
 87 Anghel L., Nicolaidis M., Simulation and mitigation of single event effects, 11th IEEE International On Line Testing Symposium (IOLTS'05), pp. 81, St Raphael, FRANCE, DOI: 10.1109/IOLTS.2005.65, 6 au 8 juillet 2005
 
 88 Lazzari C., Anghel L., Reis R., Soft error circuit hardening techniques implementation using an automatic layout generator , IEEE Latin American Test Workshop (LATW'05), pp. 175-180, Salvador Bahia, BRAZIL, 30 mars au 2 avril 2005
 
 89 Anghel L., Kolonis E., Nicolaidis M., Transient and permanent fault tolerance memory cells for unreliable future nanotechnologies, IEEE Latin American Test Workshop (LATW'05), pp. 187-192, Salvador Bahia, BRAZIL, 30 mars au 2 avril 2005
 
 90 Anghel L., Velazco R., Sanchez E., Sonza Reorda M., Squillero G., Coupling Different Methodologies to Validate Obsolete Microprocessors, 19th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'04), pp. 250-255, Cannes, FRANCE, DOI: 10.1109/DFT.2004.21, 10 au 13 octobre 2004
 
 91 Nicolaidis M., Achouri M.N., Anghel L., A Diversified Memory Built-In Self-Repair Approach for Nanotechnologies, 22nd IEEE VLSI Test Symposium (VTS'04), pp. 313-318, Napa Valley, CA, UNITED STATES, DOI: 10.1109/VTEST.2004.1299258, 25 au 29 avril 2004
 
 92 Anghel L., Nicolaidis M., Achouri M.N., Evaluation of Memory Built-in Self Repair Techniques for High Defect Density Technologies, 10th IEEE Pacific Rim International Symposium on Dependable Computing (PRDC'04), pp. 315-320, Papeete, Tahiti, FRENCH PORYNESIA, DOI: 10.1109/PRDC.2004.1276581, 3 au 5 mars 2004
 
 93 Nicolaidis M., Achouri M.N., Anghel L., A Memory Built-In Self-Repair for High Defect Densities Based on Error Polarities, 18th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'03), pp. 459-466, Boston, MA., UNITED STATES, DOI: 10.1109/DFTVS.2003.1250144, 3 au 5 novembre 2003
 
 94 Anghel L., Velazco R., Saleh S., Deswaertes S., El Moucary A., Preliminary Validation of an Approach Dealing with Processor Obsolescence, 18th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'03), pp. 493-500, Boston, MA, UNITED STATES, DOI: 10.1109/DFTVS.2003.1250148, 3 au 5 novembre 2003
 
 95 Nicolaidis M., Achouri M.N., Anghel L., Memory Built-In Self-Repair for Nanotechnologies, 9th IEEE International On-Line Testing Symposium, pp. 94-98, Kos Island, GREECE, DOI: 10.1109/OLT.2003.1214373, 7 au 9 juillet 2003
 
 96 Velazco R., Anghel L., Saleh S., A Methodology for Test Replacement Solutions of Obsolete Processors, 9th IEEE International On-Line Testing Symposium (IOLTS'03), pp. 209-213, Kos Island, GREECE, DOI: 10.1109/OLT.2003.1214400, 7 au 9 janvier 2003
 
 97 Alexandrescu D., Anghel L., Nicolaidis M., New methods for evaluating the impact of single event transients in VDSM ICs, 17th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'02), pp. 99-107, Vancouver, BC, CANADA, DOI: 10.1109/DFTVS.2002.1173506, 6 au 8 novembre 2002
 
 98 Alexandrescu D., Nicolaidis M., Anghel L., Simulating single event transients in DVSM ICs for ground level radiation, 3rd IEEE Latin American Test Workshop (LATW'02), Montevideo, URUGUAY, 10 au 13 février 2002
 
 99 Anghel L., Nicolaidis M., Alzaher-Noufal I., Self-checking circuits versus realistic faults in very deep submicron, 18th IEEE VLSI Test Symposium, pp. 55-63, Montréal, CANADA, DOI: 10.1109/VTEST.2000.843827, 30 avril au 4 mai 2000
 
100 Anghel L., Nicolaidis M., Cost reduction and evaluation of a temporary faults detecting technique, Design Automation and Test in Europe Conference and Exhibition (DATE'00), pp. 591-598, Paris, FRANCE, DOI: 10.1109/DATE.2000.840845, 27 au 30 mars 2000
 
101 Anghel L., Alexandrescu D., Nicolaidis M., Evaluation of a Soft Error Tolerance Technique Based on Time and/or Space Redundancy, 13th Symposium on Integrated Circuits and Systems Design (SBCCI'00), pp. 237-242, Manaos, BRAZIL, DOI: 10.1109/SBCCI.2000.876036, 1 janvier 2000
 
102 Anghel L., Nicolaidis M., Implementation and evaluation of a soft error detecting technique, The 5th IEEE International On-Line Testing Workshop (IOLTW'99), Rhodes, GREECE, 5 au 7 juillet 1999
 
103 Nicolaidis M., Anghel L., Concurrent Checking for VLSI, Third session on Reliability in VLSI circuits: operation, manufacturing and design: operation, manufacturing and design, pp. 139 - 156 , Austrans, FRANCE, 28 juin au 4 juillet 1999
 
104 Calin T., Anghel L., Nicolaidis M., Built-In Current Sensor for IDDQ Testing in Deep Submicron CMOS, 17TH IEEE VLSI Test Symposium (VTS'99), pp. 135-142, Dana Point, CA , UNITED STATES, DOI: 10.1109/VTEST.1999.766657, 25 au 29 avril 1999
 
105 Calin T., Anghel L., Nicolaidis M., Asynchronous Current Monitors for Transient Fault Detection in Deep Submicron CMOS, 4th IEEE International On-Line Testing Workshop (IOLTW'98), Capri, ITALY, 6 au 8 juillet 1998
 
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5 Chapitres de livre

1 Benabdenbi M., Anghel L., Dimopoulos M., Gang Yi, Adaptive Routing for Fault Tolerance and Congestion Avoidance for 2D Mesh and Torus NoCs in Many-Core Systems-on-Chip, Advances in Microelectronics: Reviews, Sergei Y. Yurish (Eds.) , Ed. IFSA, International Frequency Sensor Association, pp. 405-435, Vol. 1, 2017
 
2 Anghel L., Nicolaidis M., Defects Tolerant Logic Gates for Unreliable Future Nanotechnologies, Computational and Ambient Intelligence , Ed. Springer , pp. 422-429, DOI: DOI 10.1007/978-3-540-73007-1_52, 2007
 
3 Anghel L., Nicolaidis M., Cost Reduction and Evaluation of a Temporary Faults Detecting Technique, Design, Automation, and Test in Europe (DATE) “The Most Influential Papers of 10 Years”, Rudy Lauwereins and Jan Madsen (Eds.) , Ed. Springer , pp. 423-438 , DOI: 10.1007/978-1-4020-6488-3_31, 2007
 
4 Lazzari C., Anghel L., Reis R., A Transistor Placement Technique Using Genetic Algorithm And Analytical Programming , VLSI-SOC: From Systems to Silicon, (selected contributions from VLSI-SoC’05) , Ed. Springer , pp. 331-344, Vol.240, DOI: DOI 10.1007/978-0-387-73661-7_21, 2007
 
5 Anghel L., Rebaudengo M., Sonza Reorda M., Violante M., Multilevel Fault Effects Evaluation, Radiation Effects on Embedded Systems, RAOUL VELAZCO, PASCAL FOUILLAT and RICARDO REIS (Eds.) , Ed. Springer , pp. 69-88, DOI: DOI 10.1007/978-1-4020-5646-8, 2007
 
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2 Livres & Éditions Ouvrages

1 Anghel L., Bolchini C., Pontarelli S. (Eds.) Editorial, Microprocessors and Microsystems, Vol. 38, No.6, pp. 565-566, Ed. Elsevier, 2014
 
2 Nicolaidis M., Anghel L. (Eds.) Proceedings of 11th IEEE International On-Line Testing Symposium (IOLT 2005) Saint Raphael, French Riviera, France, July 6-8, 2005, pp. 330 pages, Ed. IEEE, 2005
 
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6 Conférences nationales

1 Rehman Saif-Ur, Benabdenbi M., Anghel L., Cost-efficient Testing of LUT and Intra-cluster Interconnect of a Novel SRAM-based FPGA, Colloque National System-On-Chip System-In-Package (SoC-SiP'13), Lyon, FRANCE, 10 au 12 juin 2013
 
2 Pasca V., Anghel L., Benabdenbi M., Fault Resilient Intra-die and Inter-die Communication in 3D Integrated Systems, PhD Research in Microelectronics and Electronics Conference (PRIME'10), Berlin, GERMANY, 18 au 21 juillet 2010
 
3 Ferron J.B., Anghel L., Leveugle R., Predictive analysis of configuration bit criticality in SRAM-based FPGAs – Methodology, tools, and results, 3ème Colloque du GdR SoC-SiP, Paris, FRANCE, 10 au 12 juin 2009
 
4 Anghel L., Fesquet L., Morin-Allory K., Initiation à la conception de VLSI numériques, 10èmes Journées Pédagogiques CNFM (JPCNFM'08), Saint-Malo, FRANCE, 26 au 28 novembre 2008
 
5 Rusu C., Grecu C., Anghel L., Network-on-Chip Fault Tolerance through Checkpoint and Rollback Recovery, National Symposium on System-on-Chip - System-in-Package (GdR SoC-SiP’08), Paris, FRANCE, 4 au 6 juin 2008
 
6 Dang T., Anghel L., Leveugle R., Structures robustes pour circuits logiques à base de CNTFET, 11ème Journées Nationales du Réseau Doctoral en Microélectronique (JNRDM’08), pp. 66, Bordeaux, FRANCE, 14 au 16 mai 2008
 
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1 Autres communications

1 Anghel L., Paradigm shift in the level of Quality and Reliability in semiconductors to a level smaller than 10ppb, Automotive Reliability and Test Workshop, Fort Worth, UNITED STATES, 2016
 
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8 Rapports

1 Yu H., Nicolaidis M., Anghel L., Zergainoh N.-E., Efficient Fault Dectection Architecture Design of Latch-based Low Power DSP/MCU Processor, ISRN: TIMA-RR--2011/01--FR, 1 janvier 2011
 
2 Nicolaidis M., Anghel L., Achouri M.N., A Memory Built-In Self-Repair for High Defect Densities Based on Error Polarities , ISRN: TIMA-RR--03/08-02--FR, 1 janvier 2003
 
3 Anghel L., Velazco R., Saleh S., A methodology for test replacement solutions of obsolete processors, ISRN: TIMA-RR--03/08-05--FR, 1 janvier 2003
 
4 Nicolaidis M., Anghel L., Achouri M.N., Memory Built-In Self-repair for Nanotechnologies, ISRN: TIMA-RR--03/08-02--FR, 1 janvier 2003
 
5 Anghel L., Saleh S., Velazco R., Preliminary validation of an approach dealing with processor obsolescence, ISRN: TIMA-RR--03/08-03--FR, 1 janvier 2003
 
6 Alexandrescu D., Nicolaidis M., Anghel L., Simulating Single Event Transients in VDSM ICs for Ground Level, ISRN: TIMA-RR--03/08-05--FR, 1 janvier 2003
 
7 Alexandrescu D., Anghel L., Nicolaidis M., Simulating Single Event Transients in VDSM ICs for Ground Level Radiation, ISRN: TIMA--RR-02/01/2--FR, 1 janvier 2002
 
8 Anghel L., Nicolaidis M., Cost Reduction and Evaluation of a Temporary Faults Detecting technique, ISRN: TIMA-RR-01/02-02--FR, 1 janvier 2001
 
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2 Thèses

1 Anghel L., CMOS and post CMOS Robust Design, HDR, 24 septembre 2007
 
2 Anghel L., Fault tolerance versus technological limitations of silicon, These de Doctorat, 15 décembre 2001
 
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