Laboratoire TIMA


Best Paper Award, student 2nd place at NEWCAS'2017 (Strasbourg, FRANCE)

Distinction : Best Paper Award, student 2nd place at NEWCAS 2017

Title: On-the-fly and sub-gate-delay resolution TDC based on self-timed ring: A proof of concept.


Abstract: A new fully digital high resolution time-to-digital converter (TDC) based on a self-timed ring oscillator (STR) is presented. The proposed TDC can virtually achieve as fine as desired time resolution by simply increasing its number of stages thanks to the STR unique features. Moreover, the proposed technique allows on-the-fly time measurement on fast non-periodic signals. The TDC has been implemented using 28 nm FDSOI technology to provide a proof of concept of the proposed method. Simulation results point out

June 25- 28, 2017


Best Paper Award at the SNUG (Synopsys User Group) Conference

Distinction : Titre : Conclusive Formal Verification of Clock Domain Crossings using SpyGlass-CDC

Auteurs : Mejid Kebaili (STMicroelectronics) & Guillaume Plassan (Synopsys) (deux doctorants de TIMA/AMFORS en thèse CIFRE:
Guillaume Plassan: CIFRE avec Synopsys
Mejid Kebaili:CIFRE avec STMicroelectronics
Récompense : “Best Paper Award” from the Technical Committee

Abstract :
In modern designs, the correct propagation of data through clock domains is ensured by implementing specific synchronizer protocols.
Then, to guarantee the absence of metastability, data loss or incoherence, the functional correctness of each CDC (Clock Domain Crossing) must be verified by using formal techniques.
However, flat verification of large designs often leads to an inconclusive status (neither proved nor failed) with limited debug capabilities.
In order to ease the formal analysis, an enhanced solution, called the Reactive flow, has been developed in the context of ST / Synopsys collaboration.
It consists of automatically abstracting irrelevant parts of the design in order to provide at least a local cause for a fail.
Also, our flow generates potential missing constraints to setup the design and to guide the formal analysis.
This methodology has been performed on large CPU 64 bits Sub-Systems with positive results.

le 28/06/2016 au World Trade Center de Grenoble


Best Paper Award at the Rapido workshop (joint work with Kalray)

Distinction : Titre : Virtual prototyping of floating point units

Auteurs : Sarrazin G. (TIMA - SLS), Brunie N. (Kalray), Pétrot F. (TIMA - SLS)

Récompense: 2016 : Best paper award at the Rapido workshop (joint work with Kalray), circuit presented at ISSCC implementing our patented asynchronous serdes for 3D-Chips

18-20 janvier 2016


Best Paper Award at NANOARCH 2016 symposium

Distinction : Title: Multi-contex Non-volatile Content Adressable Memory using Magnetic Tunnel Junctions

Authors: E. Deng (TIMA, AMfoRS), L. Anghel (TIMA, AMfoRS), G. Prenat (TIMA, RMS), W. Zhao (TIMA, AMfoRS)

Award: 2016 Best Paper Award at the 12th IEEE/ACM International Symposium on Nanoscale Architectures, July 18-20, 2016, Beijing, China

July 18-20, 2016


Best Paper Award Nominee at SMACD'2017 (Taormina, ITALY)

Distinction : Best Paper Award Nominee in lnternational Conference on Synthesis, Modeling, Analysis, and Simulation Methods and Applications to Circuit Design (SMACD) 2017

Project: Importance of IR Drops on the Modeling of Laser-Induced Transient Faults


Abstract: Laser fault injection attacks induce transient faults by locally generating transient currents capable of temporarily flip the outputs of several gates. Many models used to simulate transient faults induced by laser consider several elements to better represent the effects of the laser on ICs. However, a laser-induced current between VDD and GND, which provokes significant IR drops, has been neglected. This paper highlights the importance of the induced IR drops on the modeling of laserinduced transient faults by using IR drop CAD tools. It also shows that laser-induced IR drops can be sufficiently strong to produce alone transient faults. As a result, the number of faults on a case-study circuit is accentuated whether IR drop effects are taken into account.

June 12-15, 2017


Guillaume Plassan vainqueur régional de "Ma thèse en 180 secondes"

Distinction : Guillaume Plassan, doctorant TIMA en CIFRE chez Synopsys, a été très brillant pour présenter en 3 minutes au grand public, de manière imagée et théatrale, ses travaux sur la vérification des synchronisations dans les circuits multi-horloges.

Il a gagné le premier prix du Collège Doctoral de Grenoble, et le droit de poursuivre la compétition au niveau national fin mai.

Voir la vidéo

Accéder au reportage

Le 25 avril 2016


Dominique BORRIONE est membre d'honneur de la société informatique de France 2017

Distinction : Dominique BORRIONE

Professeur émérite à l’Université Grenoble Alpes, Dominique BORRIONE a été Professeur à l’Université de Provence, Marseille (Déc. 1983 – Août 1988) avant de muter à l’Université de Grenoble en 1988. Elle a assuré la direction des laboratoires IMAG-ARTEMIS (Jan. 1992-Déc 1995) et TIMA (janv 2007 à déc 2014) à Grenoble. Ses domaines d’expertise portent sur les langages de description et de simulation des systèmes matériels numériques, les méthodes formelles et semi-formelles pour la description, la spécification, la vérification, la synthèse de systèmes intégrés numériques.


Le 28 janvier 2017


Best Paper Award at 48th International Symposium on Microelectronics (ISM'2015)

Distinction : "48th International Symposium on Microelectronics"

Authors: Abdelaziz Goulahsen¹, Julien Saadé², Frédéric Pétrot²
¹STMicroelectronics, Grenoble, France
²TIMA Laboratory, Université Grenoble-Alpes, Grenoble, France

Title: Line coding methods for high speed serial links

October 26-29, 2015, Orlando, Florida


Best Paper Award at DATE'2015

Distinction : Authors: Marine Saliva1, Florian Cacho1, Vincent Huard1, Xavier Federspiel1, Damien Angot1, Ahmed Benhassain1, Alain Bravaix2 and Lorena Anghel3
1STMicroelectronics, FR; 2IM2NP-ISEN, FR; 3TIMA, FR

Title: Digital circuits reliability with in-situ monitors in 28 nm fully depleted SOI

at the Design Automation and Test in Europe (DATE'2015) Conference

Grenoble, France

March 9–13, 2015