Laboratoire TIMA

Actualités


Le prochain Conseil de Laboratoire aura lieu le

27/06/2018 à 09 h 00, Laboratoire TIMA - Salle T312, FRANCE

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Conférences

28rd International Workshop on Power And Timing Modeling, Optimization and Simulation

PATMOS
Venue: Costa Brava, SPAIN
Date: July 2-4, 2018

Summary: PATMOS has a history of 30 years, being one of the first conferences focusing on low power. Starting 2018, PATMOS will be collocated with two complementary conferences, IOLTS and IVSW, forming FEDfRo, the federative event on Design for Robustness. The traditional scope of PATMOS has mainly been about the design of circuits and architectures optimized for highest performance at lowest power consumption. But meanwhile, power-efficiency has become extremely important for many more areas spreading far beyond this traditional R&D niche. Energy efficiency has become a must in the connected network of battery-operated nodes known as Internet-of-Things (IoT). Wearable devices, home appliances, vehicles and security surveillance systems mostly rely on small sensors that should ideally operate on battery charge for days or even weeks. However, current battery efficiencies do not keep up with the growing demands of IoT nodes for power, forcing us to seek novel techniques for energy harvesting and power optimization. Additionally, energy-efficient ICT (Information and Communication Technology) infrastructures are a key issue for local and global economies. Some predict that, if current trends continue, the electricity consumption caused by the Internet will increase up to 30 times in the year 2030. The strong increase of wireless communication and the growth of cloud computing require orders of magnitude more computational power. PATMOS 2018 aims to find solutions for both, small-scaled integrated circuits in IoT nodes, and large-scale ICT infrastructures that require massive energy consumption.

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3rd International Verification and Security Workshop

IVSW
Venue: Costa Brava, SPAIN
Date: July 2-4, 2018

Summary: Issues related to verification and security are increasingly important in modern electronic systems. In particular, the huge complexity of electronic systems has led to growth in quality, reliability and security needs in several application domains as well as pressure for low cost products. There is a corresponding increasing demand for cost-effective verification techniques and security solutions. These needs have increased dramatically with the increased complexity of complex electronic systems and the fast adoption of these systems in all aspects of our daily lives. The goal of IVSW is to bring industry practitioners and researchers from the fields of security, verification, validation, test, and reliability to exchange innovative ideas and to develop new methodologies for solving the difficult challenges facing us today in various SOC design environments. IVSW 2018 is sponsored by IEEE Council on Electronic Design Automation (CEDA).

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24th IEEE International Symposium on On-Line Testing and Robust System Design

IOLTS
Venue: Costa Brava, SPAIN
Date: July 2-4, 2018

Summary: Issues related to On-line testing techniques, and more generally to design for robustness, are increasingly important in modern electronic systems. In particular, the huge complexity of electronic systems has led to growth in reliability needs in several application domains as well as pressure for low cost products. There is a corresponding increasing demand for cost-effective design for robustness techniques. These needs have increased dramatically with the introduction of nanometer technologies, which impact adversely noise margins; process, voltage and temperature variations; aging and wear-out; soft error and EMI sensitivity; power density and heating; and make mandatory the use of design for robustness techniques for extending, yield, reliability, and lifetime of modern SoCs. Design for reliability becomes also mandatory for reducing power dissipation, as voltage reduction, often used to reduce power, strongly affects reliability by reducing noise margins and thus the sensitivity to soft-errors and EMI, and by increasing circuit delays and thus the severity of timing faults. There is also a strong relation between Design for Reliability and Design for Security, as security attacks are often fault-based. The International Symposium on On-Line Testing and Robust System Design (IOLTS), is an established forum for presenting novel ideas and experimental data on these areas. The Symposium is sponsored by the IEEE Council on Electronic Design Automation (CEDA) and the 2018 edition is organized by the IEEE Computer Society Test Technology Technical Council, the University of Athens, and the TIMA Laboratory.

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Thèses soutenances

« Conception et Simulation des Circuits Numériques en 28nm FDSOI pour la Haute Fiabilité ».

Candidat : A. Sivadasan

Directeur de thèse : L. Anghel

Président du jury : I. O'Connor

Thèse de Doctorat : These de Doctorat, Université de Grenoble

Spécialité : Microélectronique

Soutenance : Le 29/06/2018 à 10 h 00, GRENOBLE INP (Viallet) - Amphi Gosse

Résumé

Scaling of classical CMOS technology provides an increase in performance of digital circuits owing to the possibility of incorporation of additional circuit components within the same silicon area. 28nm FDSOI technology from ST Microelectronics is an innovative scaling strategy maintaining a planar transistor structure and thus providing a better performance with no increase in silicon chip fabrication costs for low power applications. It is important to ensure that the increased functionality and performance is not at the expense of decreased reliability, which can be ensured by meeting the requirements of international standards like ISO26262 for critical applications in the automotive and industrial settings. Semiconductor companies, to conform to these standards, are thus required to exhibit the capabilities for reliability estimation at the design conception stage most of which, currently, is done only after a digital circuit has been taped out. This work concentrates on aging of standard cells and digital circuits with time, under the influence of NBTI degradation mechanism for a wide range of Process, Voltage and Temperature (PVT) variations and aging compensation using body-biasing. One of the principal aims of this thesis is the establishment of a reliability analysis infrastructure consisting of software tools and gate level aging model in an industrial framework for failure rate estimation of digital circuits at the design conception stage for circuits developed using ST 28nm FDSOI technology.

 

Distinctions


Best Paper Award at ASYNC'2018 (Vienna, AUSTRIA)

Project: Best Paper Award at ASYNC'2018 (24th IEEE International Symposium on Asynchronous Circuits and Systems)
Date: May 13-16, 2018
Place: Vienna (AUSTRIA)
Title: "Static Timing Analysis of Asynchronous Bundled-data Circuits"
Authors: Grégoire GIMENEZ (TIMA-CDSI), Abdelkarim CHERKAOUI (TIMA-CDSI), Guillaume COGNIARD, Laurent FESQUET (TIMA-CDSI)

 

Best Poster at JNRDM'2017 (Strasbourg, FRANCE)

Project: Best Poster at JNRDM'2017 (Journées Nationales du Réseau Doctoral en Micro-nanoélectronique 2017)
Date: November 6-8, 2017
Place: Strasbourg (FRANCE)
Title: "Conception en vue du test d’un amplificateur de puissance à 60 GHz"
Authors: Florent CILICI (TIMA-RMS), Manuel BARRAGAN (TIMA-RMS), Estelle LAUGA-LARROZE, Sylvain BOURDEL, Salvador MIR (TIMA-RMS)

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Best Presentation and Paper Award at JNRSE'2017 (Lyon, FRANCE)

Project: Best Presentation and Paper Award at JNRSE 2017 (7èmes Journées Nationales sur la Récupération et le Stockage d'Energie)

Title: "Modeling and operating temperature tuning of a thermally activated piezoelectric generator"

Authors: Adrian RENDON-HERNANDEZ and Skandar BASROUR

Abstract: This paper deals with the finite element model of a thermally activated piezoelectric generator. Furthermore, it presents an experimentally validated temperature tuning technique based on the gap distance of the triggering system. The working principle of proposed generator relies on the multi step thermal-to-mechanical-to-electrical energy conversion, overcoming inconveniences related to fast temporal temperatura variations and large temperature differences for efficient operating of classical direct thermal energy conversion. Performance optimization can be done in the form of temperature span tuning by changing the gap distance. By increasing this parameter, it is possible to maximize the Energy up to 10 times. Experimental data suggests that output energy up to 67 μW is possible when optimal gap distance is set. This corresponds to a power density of 103 μWcm-3

May 9-10, 2017

 

Jobs

Administrateur des systèmes d'information

Équipe : Service Informatique

Date de début : 01/10/2018

Durée : 18 mois

Profil :
MISSION :
L'administrateur systèmes et réseaux du Laboratoire TIMA met en place, administre et exploite les moyens informatiques, matériels et logiciels, d'un laboratoire de 120 personnes. Il assure la sécurité, la disponibilité et l'évolution du réseau et des serveurs.
L’ingénieur devra après analyse de l’existant, proposer des axes d’amélioration. Il devra mettre en œuvre les solutions retenues et entreprendre la migration d’une partie de l’infrastructure dans des datacentres mutualisés.

ACTIVITES :
• Etudier l'infrastructure, le réseau, les services actuels du laboratoire
• Etablir une cartographie du système d’informations et rédiger les documents nécessaires à son exploitation
• Proposer un plan de diminution, rationalisation, externalisation de services, afin d'en assurer la pérennité
• Garantir la sécurité du système d’information en appliquant les normes et standards de sécurité
• Procéder, après analyse, à la migration de services actuellement hébergés au laboratoire vers les Datacenter des tutelles
• Animer et coordonner l'activité d'une équipe de 2 techniciens et assurer le transfert de compétences
L’ensemble de ces actions se fera en partenariat avec les responsables systèmes et réseaux de l’INP, de l’UGA et du CNRS

COMPETENCES :
Compétences générales :
• Connaissance approfondie des concepts et techniques d'architecture des systèmes et réseaux
• Connaissance des différentes architectures matérielles
• Savoir gérer les situations d'urgence et hiérarchiser les priorités
• Connaissance des technologies, protocoles et outils des systèmes et réseaux (il est entre autre nécessaire de maîtriser la notion de vlan et son application sous Linux)
• Connaissance générale des procédures de sécurité informatique (architecture réseau sécurisée, sécurisation des services)
• Etre en capacité de communiquer et d’expliquer ses choix notamment auprès de la direction et des utilisateurs et de dialoguer avec les ingénieurs systèmes et réseaux des différentes tutelles
• Lire couramment les notices techniques en anglais

Compétences spécifiques :
• Administrer les hyperviseurs (VMware) et les baies de stockage (isci)
• Utiliser des outils d'administration, d'audit et d'analyse des systèmes (logs système, nessus, nmap, snort)
• Maîtriser Linux (FAI, NFS, Kerberos, firewall, bridge, cryptsetup, ...)

See complete information to : Follow the link

Personne à contacter : Frédéric PETROT et Anne-Laure FOURNERET