Laboratoire TIMA

Actualités


MIAI GRENOBLE ALPES - TIMA a obtenu deux chaires MIAI et encadrera des thèses

, FRANCE

TIMA MIAI CHAIRS
(Multidisciplinary Institute in Artificial Intelligence)

Chair title: Digital Hardware AI Architectures
Chair holder(s): Frédéric PETROT (TIMA - SLS team)
Financed by: ANR - PIA
In short:
According to a recent Facebook analysis, AI tasks need a 100x power reduction in the coming years to be sustainable. This chair focuses on highly energy efficient hardware/software architectures integration of AI and deep-learning to take up this challenge.
Partners:
• Google France
• Kalray
• STMicroelectronics
• Upmem
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Chair title: Hardware for spike-coded neural networks exploiting hybrid CMOS non-volatile technologies
Chair holder(s): Lorena ANGHEL (TIMA - AMfoRS team)
Financed by: ANR - PIA
In short:
Spiking Neural Networks are seen as a Key building block for strongly improving the energy efficiency of current AI applications and opening up new possibilities (in terms of unsupervised learning, recurrent networks, probabilistic inference, etc.). In that respect, the Grenoble R&D ecosystem has key strengths, especially its capability to design and manufacture embedded systems in advanced hybrid CMOS-Non Volatile Memory (NVM) technology. The scientific challenges to be tackled are the following. The first one is to define power-constrained learning and inference algorithms (online, supervised, unsupervised, probabilistic, etc.). The second one is to design a scalable and flexible SNN architecture, adaptable to the different above-mentioned algorithms, and fabricate that circuit in hybrid nanoscale CMOS and NVM technology, enabling very dense synaptic density. The last objective is to derive a principled toolchain for the algorithm, design, development, and integration of spiking neural networks for future adoption in industrial health and automotive embedded applications.
Partners:
• CEA LETI (Alexandre VALERIAN)


Conférences

28th IFIP/IEEE International Conference on Very Large Scale Integration

VLSI-SoC
Venue: Salt Lake City, USA
Date: October 5-7, 2020

steering committee member : MIR S.

4th International Conference on Control, Automation and Diagnosis

ICCAD (Control Automation and Diagnosis)
Venue: Paris, FRANCE
Date: October 7-9, 2020

industry liaison : SIMEU E. technical program committee : SIMEU E.

33rd IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems

DFT
Venue: Roma, ITALY
Date: October 19-21, 2020

technical program committee : ANGHEL L., DI NATALE Giorgio

Summary: DFT is an annual Symposium providing an open forum for presentations in the field of defect and fault tolerance in VLSI and nanotechnology systems inclusive of emerging technologies. One of the unique features of this symposium is to combine new academic research with state-of-the-art industrial data, necessary ingredients for significant advances in this field. All aspects of design, manufacturing, test, reliability, and availability that are affected by defects during manufacturing and by faults during system operation are of interest.

IEEE International Test Conference

ITC
Venue: Washington DC, USA
Date: November 3-5, 2020

steering committee member : DI NATALE Giorgio technical program committee : VATAJELU E.I.

Summary: International Test Conference, the cornerstone of TestWeek™ events, is the world’s premier conference dedicated to the electronic test of devices, boards and systems-covering the complete cycle from design verification, test, diagnosis, failure analysis and back to process and design improvement. At ITC, test and design professionals can confront the challenges the industry faces, and learn how these challenges are being addressed by the combined efforts of academia, design tool and equipment suppliers, designers, and test engineers.

Thèses soutenances

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Distinctions


Winner of PhD Forum at VLSI-SoC'2019 (Cuzco, PERU)

Distinction : Winner of PhD Forum at VLSI-SoC'2019 (27th IFIP/IEEE International Conference on Very Large Scale Integration)
Date: October 6-9, 2019
Place: Cuzco (PERU)
Title: A Digital Event-Based Strategy for ASK demodulation
Authors:
- Rodrigo IGA JADUE (TIMA - CDSI team)
- Sylvain ENGELS (TIMA - CDSI team)
- Laurent FESQUET (TIMA - CDSI team)

 

Best Paper Award at DDECS'2019 (Cluj Napoca, ROMANIA)

Distinction : Best Paper Award at DDECS'2019 (22nd International Symposium on Design and Diagnostics of Electronics Circuits and Systems)
Date : April 24-26, 2019
Place : Cluj Napoca (ROMANIA)
Title : "Encryption-Based Secure JTAG"
Authors :
- Emanuele VALEA (LIRMM, Montpellier)
- Mathieu DA SILVA (LIRMM, Montpellier)
- Marie-Lise FLOTTES (LIRMM, Montpellier)
- Giorgio DI NATALE (TIMA, AMfoRS team, Grenoble)
- Bruno ROUZEYRE (LIRMM, Montpellier)

 

IFIP WG 10.5 Meritorious Service Award at VLSI-SoC'2018 (Verona, ITALY)

Distinction : The IFIP WG 10.5 Meritorious Service Award has been given to Mrs Dominique BORRIONE "for continued services to IFIP ans the Working Group on Design and Engineering of Electronic Systems"
She was awarded during VLSI-SoC'2018 (26th IFIP/IEEE International Conference on Very Large Scale Integration)
Date: October 8-10, 2018
Place: Verona (ITALY)

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Jobs

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