Laboratoire TIMA



30th International Conference on Microelectronics

Venue: Sousse,
Date: December 16-19, 2018

special session organizer : SIMEU E.
technical program committee : MIR S.

Summary: The International Conference on Microelectronics (ICM) has been held in numerous countries across the Southern Europe and Western and Southern Asia for the past 29 years. The 30th edition of the conference will be hosted by Computer and Embedded Systems Laboratory (CES lab) in Tunisia. In ICM 2018, several topics will be discussed such as Circuits and Systems, CAD Tools and Design and Micro/Nano electronics and special topics. It will include oral, poster sessions and tutorials given by experts in state-of-the-art topics. The regular technical program will run for three days. Moreover tutorial sessions will be held on the first day of the conference.

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6th Workshop on Cryptography and Security in Computing Systems

Venue: Valencia,
Date: January 21, 2019

program committee : MAISTRI P.

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20th IEEE Latin American Test Symposium

Venue: Santiago,
Date: March 11-13, 2019

co-general chair : VELAZCO R.
finance chair : FOURNERET-ITIÉ A.-L.

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Design, Automation & Test in Europe

Venue: Firenze,
Date: March 25-29, 2019

interactive presentations chair : PETROT F.
University Booth Co-Chair : VATAJELU E.I.

Summary: DATE is the top scientific event in Design, Automation, and Test of microelectronics and embedded systems for the academic and industrial research communities worldwide. It provides a unique networking opportunity, bringing together designers and design automation users, researchers and vendors, as well as specialists in hardware and software design, test and manufacturing of electronic circuits and systems.

In 2019, the conference will take place for the first time in Florence, Italy. Florence is the capital of Tuscany Region, centrally located and very easy to reach via an international airport hub. Art, culture, modernity and vibrancy: Florence is much more than the cradle of Renaissance. Vaunting an unparalleled past of incredible accomplishments, Florence is a contemporary city that offers year-round entertainment. Striking architecture and monuments, museums of masterpieces, as well as fashion, theatres, gardens, modern art exhibitions, excellent places to eat and drink, and an international flair that has always set this city apart. It is time to fall in love with Florence. It is situated on the plain of the Arno River between the hills that made this region famous, surrounded by towns, villages and enchanting landscapes. Due to its history, today Florence can offer a lot of astonishing venues like the Palazzo Pitti or Palazzo Vecchio, the Town Hall of Florence, many churches like the Basilica di Santa Croce, the Basilica di Santa Maria Novella and also some open-air museums such as Giardino delle Rose and Giardino di Boboli. Florence is also a modern destination that offers many opportunities for events and activities for guests. In 2019, all over Italy but particularly Florence and the nearby hometown Vinci will be celebrating the 500th anniversary of the death of the genius Leonardo da Vinci.

The five-day event covers the design process, test, and automation tools for electronics, ranging from integrated circuits to distributed embedded systems. The conference scope includes both hardware and embedded software design issues. It also includes the elaboration of design requirements and new architectures for challenging application fields such as internet of things, multimedia, healthcare, smart energy, and automotive systems.

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Theme: Nonlinear phenomena in M/NEMS and their applications
Date: December 18th, 2018, TIMA Laboratory - Room T312

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Sungjoo YOO, Seoul National University (Full professor)

Theme: Low precision in neural network training and inference
Date: January 7th, 2019 - 10:30-12:00, Viallet - Amphi Gosse

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Thèses soutenances

« Actuellement il n’y aucune soutenance prévue »


IFIP WG 10.5 Meritorious Service Award at VLSI-SoC'2018 (Verona, ITALY)

Distinction : The IFIP WG 10.5 Meritorious Service Award has been given to Mrs Dominique BORRIONE "for continued services to IFIP ans the Working Group on Design and Engineering of Electronic Systems"
She was awarded during VLSI-SoC'2018 (26th IFIP/IEEE International Conference on Very Large Scale Integration)
Date: October 8-10, 2018
Place: Verona (ITALY)

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Best Paper Award at ETS'2018 (Bremen, GERMANY)

Distinction : Best Paper Award at ETS'2018 (23rd IEEE European Test Symposium)
Date: May 28 - June 01, 2018
Place: Bremen (GERMANY)
Title: "Assisted test design for non-intrusive machine learning indirect test of millimeter-wave circuits"
Authors: Authors: Florent CILICI (TIMA-RMS), Manuel BARRAGAN (TIMA-RMS), Salvador MIR (TIMA-RMS), Estelle LAUGA-LARROZE (RFIC-Lab), Sylvain BOURDEL (RFIC-Lab)


Best Paper Award at SIGNAL'2018 (Nice, FRANCE)

Distinction : Best Paper Award at SIGNAL'2018 (3rd International Conference on Advances in Signal, Image and Video)
Date: May 20 - 24, 2018
Place: Nice (FRANCE)
Title: "Shaping Electromagnetic Emissions of Event-Driven Circuits Thanks to Genetic Algorithms"

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Best Paper Award at ASYNC'2018 (Vienna, AUSTRIA)

Distinction : Best Paper Award at ASYNC'2018 (24th IEEE International Symposium on Asynchronous Circuits and Systems)
Date: May 13-16, 2018
Place: Vienna (AUSTRIA)
Title: "Static Timing Analysis of Asynchronous Bundled-data Circuits"
Authors: Grégoire GIMENEZ (TIMA-CDSI), Abdelkarim CHERKAOUI (TIMA-CDSI), Guillaume COGNIARD, Laurent FESQUET (TIMA-CDSI)


Best Poster at JNRDM'2017 (Strasbourg, FRANCE)

Distinction : Best Poster at JNRDM'2017 (Journées Nationales du Réseau Doctoral en Micro-nanoélectronique 2017)
Date: November 6-8, 2017
Place: Strasbourg (FRANCE)
Title: "Conception en vue du test d’un amplificateur de puissance à 60 GHz"
Authors: Florent CILICI (TIMA-RMS), Manuel BARRAGAN (TIMA-RMS), Estelle LAUGA-LARROZE, Sylvain BOURDEL, Salvador MIR (TIMA-RMS)

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Best Paper Award at WCO'2016

Distinction : Title: "Formulation and practical solution for the optimization of memory accesses in embedded vision systems" at 9th International Workshop on Computational Optimization (WCO'2016 - Gdansk, POLAND - September 11-14, 2016)
Authors: K. Hadj Salem, Y. Kieffer, S. Mancini

September 11-14, 2016


Raoul VELAZCO senior member IEEE

Distinction : Raoul VELAZCO senior member IEEE
IEEE Senior member grade is offered in recognition of professional standing and significant performance.


Frédéric PETROT: member of the jury delivering the EDAA Outstanding Dissertations

Distinction : Award for a PhD defended in 2015.


Runner-up Best Paper Award in SBCCI'2016 (Belo Horizonte, BRAZIL)

Distinction : Runner-up Best Paper Award in lnternational Symposium on Integrated Circuits and Systems Design (SBCCI) 2016

Project: New Asynchronous Protocols for Enhancing Area and Throughput in Bundled-Data Pipelines


Abstract: This paper presents two new area-reduced controllers for bundled-data asynchronous pipelines in which the stages have long critical paths. The proposed protocols allow to reduce the number of required delay elements by using the falling edge of the asynchronous request to indicate data validity. For critical path lengths of 25 gates, the first presented scheme decreases the controller area by 48% and slightly increases the maximum throughput (2%) in comparison to a standard micropipeline implementation. The other more-concurrent scheme proposition leads to a 25% area reduction and a 40% improvement of the maximum pipeline throughput.

August 29 - September 3, 2016



Design of low-power analog and mixed-signal IPs in 28 nm FDSOI technology

Équipe : TIMA Laboratory - RMS team - 46 avenue Félix Viallet - 38031 GRENOBLE Cedex

Date de début : January 2019

Durée : 1 year

Profil :
In collaboration with: CMP (Multi-Project Circuits), Grenoble, France

Context and description: The integration capabilities offered by current nanoscale CMOS technologies enable the fabrication of complete and very complex mixed-signal systems on a single die. The design of complex mixed-signal systems relies on the reuse of Intellectual Property blocks, the so-called IPs, as basic building blocks. In this line, this post-doc project envisages the design and validation of a library of basic analog and mixed-signal IPs in STMicroelectronics 28 nm FDSOI technology. The final goal of the project is to open this IP library to CMP customers around the world, so the developed IPs can be freely used to enable high-performance mixed-signal designs. The intended IP library will contain basic blocks such as operational amplifiers, comparators, reference generators, switches, etc.
Analog and mixed-signal design in state-of-the-art 28 nm FDSOI technology is a challenging task, but at the same time, FDSOI technologies open the door to low-power and high-performance applications that were unachievable in previous CMOS technologies. Indeed, the ability to adapt the body bias voltage may enable significant power savings if properly optimized. In the context of this post-doc project, we intend to explore optimization techniques for low-power and high performance analog and mixed-signal circuits in FDSOI technologies.

Skills: The prospective candidate should be highly motivated, have a PhD in Electrical and Electronics Engineering, Microelectronics or equivalent subject, have a good publication track in related fields, should be proficient in analog and mixed-signal integrated circuit design, and have experience with computer-aided design tools (e.g. Cadence). Experience on FDSOI technologies is also a plus.

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Personne à contacter : Manuel J?? BARRAGAN