Laboratoire TIMA

Actualités


Le prochain Conseil Scientifique aura lieu le

18/10/2017 à 14 h 00, Laboratoire TIMA - Salle T312, FRANCE

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Le prochain Conseil de Laboratoire aura lieu le

16/10/2017 à 14 h 00, Laboratoire TIMA - Salle T312, FRANCE

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Conférences

2nd IEEE Federative Event on Design for Robustness

FEDfRo
Venue: Hotel Macedonia Palace, Thessaloniki, GREECE
Date: July 3-5, 2017

Summary: Nanometer scaling and the related aggressive reduction of device geometries steadily worsens noise margins; process, voltage and temperature variations; aging and wear-out; soft error and EMI sensitivity; power density and heating; and make mandatory the use of efficient techniques for improving yield and reliability, extending lifespan, and reducing power dissipation of modern SoCs. Additionally, the rapidly increasing complexity of modern SoCs further aggravates these issues, and makes it extremely difficult to guarantee that the design of these chips meet their specifications. Furthermore, the pervasiveness of electronic systems in modern societies, and their ubiquitous implication in all aspects of our everyday lives, drastically raises the requirements to protect modern electronic systems against all these threats, as well as versus those induced by intentional attacks against their security. These trends have made mandatory the development of efficient Design for Robustness approaches for mitigating these pluralities of threats. However, as DfX techniques are proliferating (Design for Test, Design for Debug, Design for Yield, Design for Reliability, Design for Low-Power, Design for Security, Design for Verification, …), it becomes mandatory to address these issues holistically, in order to moderate their impact on area, power, and/or performance, and increase their global efficiency. There is therefore a related need for an international consolidated forum bringing together specialists from all these domains to enhance interactions and cross-fertilization. The IEEE Federative Event on Design for Robustness (FEDfRo), sponsored by the IEEE Council on Electronic Design Automation (CEDA), was initiated on 2016 to meet this goal by bringing together: - IOLTS: International Symposium on On-Line Testing and Robust System Design http://tima.imag.fr/conferences/iolts/iolts17/ a well-established IEEE forum on Design for Quality, Design for Yield, Design for Reliability, and Low-Power design based on Design for Reliability approaches, mostly addressing digital systems; - IMSTW: the International Mixed-Signal Testing Workshop http://tima.imag.fr/conferences/imstw/imstw17/ a well-established IEEE forum addressing these techniques in the context of mixed-signal circuits;- - IVSW: the International Verification and Security Workshop http://tima.imag.fr/conferences/ivsw/ivsw17/ a new IEEE forum started on 2016 and addressing all Verification and Security issues associated with electronic systems. Starting from 2018, a fourth event, PATMOS, will also be part of FEDfRo. The above events are soliciting papers in their respective areas. Those events will be held in the same location and will run in parallel. To encourage interactions, anyone registered in one of the events can freely attend sessions of the other two events. All social activities will also be done jointly to increase interaction and cross fertilization among attendees.

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Thèses soutenances

« Hiérarchie mémoire dans les systèmes intégrés multiprocesseurs construits autour de réseaux sur puce ».

Candidat : H. Bel Hadj Amor

Directeur de thèse : F. Pétrot

Président du jury : S. Niar

Thèse de Doctorat : These de Doctorat, Université de Grenoble

Spécialité : informatique

Soutenance : 05/10/2017 à 10 h 00, GRENOBLE INP - Amphi Gosse

Résumé

Les systèmes parallèles de type multi/pluri-cœurs permettant d’obtenir une grande puissance de calcul à bas coût énergétique sont de nos jours une réalité. Néanmoins, l’exploitation des performances de ces architectures dépend de l’efficacité du système à gérer les accès aux données. Le but de nos travaux est d’améliorer l’efficacité de ces accès en exploitant les caractéristiques de l’architecture matérielle. Dans une première partie, nous proposons une nouvelle organisation de la hiérarchie des mémoires caches qui maximise l’utilisation de l’espace de stockage disponible à chaque niveau. Cette solution, basée sur les architectures à accès non uniforme au cache (NUCA), supporte les transferts inter et intra-niveau de la hiérarchie. Elle requiert un protocole de cohérence de cache qui s’adapte à ses spécifications. Certes, le transfert des données au niveau de la hiérarchie est aussi un déterminant de la performance du système. Dans une seconde partie, nous prenons en compte les besoins de communication spécifiques du protocole. Nous proposons un réseau virtualisé comme support de communication ad-hoc afin de gérer le trafic de cohérence à moindre coût. Ce dernier relie les caches d’un même niveau pour supporter les transferts intra-niveaux, qui sont une spécificité de notre protocole, en vue de réduire la latence moyenne d’accès.

 

Distinctions


Runner-up Best Paper Award in SBCCI 2016 conference (Belo Horizonte, BRAZIL)

Project: Runner-up Best Paper Award in lnternational Symposium on Integrated Circuits and Systems Design (SBCCI) 2016

Project: New Asynchronous Protocols for Enhancing Area and Throughput in Bundled-Data Pipelines

Authors: Jean Simatic (TIMA, CDSI), Abdelkarim Cherkaoui (TIMA, CDSI), Rodrigo Possamai Bastos (TIMA, CDSI), and Laurent Fesquet (TIMA, CDSI)

Abstract: This paper presents two new area-reduced controllers for bundled-data asynchronous pipelines in which the stages have long critical paths. The proposed protocols allow to reduce the number of required delay elements by using the falling edge of the asynchronous request to indicate data validity. For critical path lengths of 25 gates, the first presented scheme decreases the controller area by 48% and slightly increases the maximum throughput (2%) in comparison to a standard micropipeline implementation. The other more-concurrent scheme proposition leads to a 25% area reduction and a 40% improvement of the maximum pipeline throughput.

August 29 - September 3, 2016

 

Best Presentation and Paper Award at JNRSE 2017 conference (Lyon, FRANCE)

Project: Best Presentation and Paper Award at JNRSE 2017 (7èmes Journées Nationales sur la Récupération et le Stockage d'Energie)

Title: "Modeling and operating temperature tuning of a thermally activated piezoelectric generator"

Authors: Adrian Rendon-Hernandez and Skandar Basrour

Abstract: This paper deals with the finite element model of a thermally activated piezoelectric generator. Furthermore, it presents an experimentally validated temperature tuning technique based on the gap distance of the triggering system. The working principle of proposed generator relies on the multi step thermal-to-mechanical-to-electrical energy conversion, overcoming inconveniences related to fast temporal temperatura variations and large temperature differences for efficient operating of classical direct thermal energy conversion. Performance optimization can be done in the form of temperature span tuning by changing the gap distance. By increasing this parameter, it is possible to maximize the Energy up to 10 times. Experimental data suggests that output energy up to 67 μW is possible when optimal gap distance is set. This corresponds to a power density of 103 μWcm-3

May 9-10, 2017

 

Best Paper Award Nominee at SMACD 2017 conference (Taormina, ITALY)

Project: Best Paper Award Nominee in lnternational Conference on Synthesis, Modeling, Analysis, and Simulation Methods and Applications to Circuit Design (SMACD) 2017

Project: Importance of IR Drops on the Modeling of Laser-Induced Transient Faults

Authors: R.A. Camponogara Viera (TIMA, CDSI), P. Maurine (LIRMM, SYSMIC), J.M. Dutertre (ENSMSE, CMP), R. Possamai Bastos (TIMA, CDSI)

Abstract: Laser fault injection attacks induce transient faults by locally generating transient currents capable of temporarily flip the outputs of several gates. Many models used to simulate transient faults induced by laser consider several elements to better represent the effects of the laser on ICs. However, a laser-induced current between VDD and GND, which provokes significant IR drops, has been neglected. This paper highlights the importance of the induced IR drops on the modeling of laserinduced transient faults by using IR drop CAD tools. It also shows that laser-induced IR drops can be sufficiently strong to produce alone transient faults. As a result, the number of faults on a case-study circuit is accentuated whether IR drop effects are taken into account.

June 12-15, 2017

 

Jobs

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