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695 résultats

   80 Revues internationales
    5 Brevets
   20 Conférences invitées
  320 Conférences internationales
   42 Chapitres de livre
   17 Livres & Éditions Ouvrages
   21 Revues nationales
   35 Conférences nationales
   29 Autres communications
   32 Rapports
   94 Thèses

80 Revues internationales

 1 Bruant J., Horrein P.H., Muller O., Groleat T., Pétrot F., Towards Agile Hardware Designs with Chisel: a Network Use-case, IEEE Design & Test, Ed. IEEE, Vol. , DOI: 10.1109/MDAT.2021.3063339, mars 2021
 
 2 France-Pillois M., Martin J., Rousseau F., A Non-intrusive Tool Chain to Optimize MPSoC End-to-end Systems, ACM Transactions on Architecture and Code Optimization , Ed. ACM IEEE, Vol. 18, No. 2, DOI: 10.1145/3445030, février 2021
 
 3 Perais A., A Case for Speculative Strength Reduction, IEEE Computer Architecture Letters, Ed. IInstitute of Electrical and Electronics Engineers, Vol. 20, No. 1, pp. 22-25, DOI: 10.1109/LCA.2020.3048694, janvier 2021
 
 4 Pierre L., Refinement rules for the automatic TLM-to-RTL conversion of temporal assertions, Integration, the VLSI Journal, Ed. Elsevier, Vol. 76, pp. 190-204, DOI: 10.1016/j.vlsi.2020.06.003, janvier 2021
 
 5 Fernandez-Mesa B.J., Andrade Porras L.L., Pétrot F., Synchronization of Continuous Time and Discrete Events Simulation in SystemC, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Ed. IEEE, Vol. , DOI: 10.1109/TCAD.2020.3019204, 2020
 
 6 Muller O., Prost-Boucle A., Bourge A., Pétrot F., Efficient Decompression of Binary Encoded Balanced Ternary Sequences (Early Access), Transactions on Very Large Scale Integration (VLSI) Systems, Ed. IEEE, Vol. , DOI: 10.1109/TVLSI.2019.2906678, avril 2019
 
 7 Matoussi O., Pétrot F., Loop aware CFG matching strategy for accurate performance estimation in IR-level native simulation, Integration, the VLSI Journal, Ed. Elsevier, Vol. , mars 2019
 
 8 Prost-Boucle A., Bourge A., Pétrot F., High-Efficiency Convolutional Ternary Neural Networks with Custom Adder Trees and Weight Compression, ACM Transactions on Reconfigurable Technology and Systems (TRETS) , Ed. ACM IEEE, Vol. 31, No. 3, pp. Article No. 15, DOI: 10.1145/3270764, décembre 2018
 
 9 Prost-Boucle A., Pétrot F., Leroy V., Alemdar H., Efficient and versatile FPGA acceleration of support counting for stream mining of sequences and frequent itemsets, ACM Transactions on Reconfigurable Technology and Systems (TRETS) , Ed. ACM IEEE, Vol. , No. in print, 2017
 
10 Michel L., Pétrot F., Dynamic Binary Translation of VLIW Codes on Scalar Architectures, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Ed. IEEE, Vol. 36, No. 5, pp. 789-800, DOI: 10.1109/TCAD.2016.2604294, mai 2017
 
11 Cunha M., Matoussi O., Pétrot F., Detecting Software Cache Coherence Violations in MPSoC Using Traces Captured on Virtual Platforms, Transactions on Embedded Computing Systems (TECS), Ed. ACM, NY, USA, Vol. 16, No. 2, pp. 30:1-30:21, DOI: 10.1145/2990193, avril 2017
 
12 Vivet P., Thonnard Y., Lemaire R., Santos Cr., Beigné E., Bernard Ch., Darve F., Lattard D., Miro-Panades I., Dutoit D., Clermidy F., Cheramy S., Sheibanyrad H., Pétrot F., Flamand E., Michailos J., Arriordaz A., Wang L., Schloeffel J., A 4 × 4 × 2 Homogeneous Scalable 3D Network-on-Chip Circuit With 326 MFlit/s 0.66 pJ/b Robust and Fault Tolerant Asynchronous 3D Links, IEEE Journal of Solid State Circuits, Vol. 52, No. 1, pp. 33-49, DOI: 10.1109/JSSC.2016.2611497, janvier 2017
 
13 Bourge A., Muller O., Rousseau F., Generating Efficient Context-Switch Capable Circuits Through Autonomous Design Flow, ACM Transactions on Reconfigurable Technology and Systems (TRETS) , Ed. ACM IEEE, Vol. 10, No. 1, pp. 9, DOI: 10.1145/2996199, 2016
 
14 Alcantara O., Fresse V., Rousseau F., Sheibanyrad H., Synthesis of Dependency-aware Traffic Gererators from NoC Simulation Traces, Journal of Systems Architecture (JSA), Ed. Elsevier, Vol. 71, pp. 102-113, DOI: 10.1016/j.sysarc.2016.10.004, novembre 2016
 
15 Paolucci P.S., Biagoni A., Murillo L.G., Rousseau F., Schor L., Tosoratto L., Bacivarov I., Buecs R.L., Deschamps Cl., El-Antably A., Ammendola R., Fournel N., Frezza O., Leupers R., Lo Cicero F., Lonardo A., Martinelli M., Pastorelli E., Rai D., Rossetti D., Simula F., Thiele L., Vicini P., Weinstock J.H., Dynamic many-process applications on many-tile embedded systems and HPC clusters: The EURETILE programming environment and execution platfor, Journal of Systems Architecture (JSA), Ed. Elsevier, Vol. 69, pp. 29-53, DOI: 10.1016/j.sysarc.2015.11.008, septembre 2016
 
16 Fresse V., Combes C., Payet M., Rousseau F., Mathematical Modeling for NoC resources Estimation on FPGA, International Journal of Computing and Digital Systems, Ed. University of Bahrain, Vol. 5, No. 2, pp. 1-4, DOI: 10.12785/ijcds/05 0 2 0 4, mars 2016
 
17 Cunha M., Fournel N., Pétrot F., Deterministic reversible MPSoC debugger based on virtual platform execution traces, Design Automation for Embedded Systems, Ed. Springer , Vol. 20, No. 1, pp. 47-63, DOI: 10.1007/s10617-015-9167-8, janvier 2016
 
18 Butt S., Mancini S., Rousseau F., Lavagno L., Design of a pseudo-log image transform hardware accelerator in a high-level synthesis-based memory management framework, Journal of Electronic Imaging, Ed. SPIE, Vol. 23, No. 2, pp. 053012, DOI: 10.1117/1.JEI.23.5.053012, septembre 2014
 
19 Foroutan S., Sheibanyrad H., Pétrot F., Assignment of Vertical-Links to Routers in Vertically-Partially-Connected 3-D-NoCs , IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Ed. IEEE, Vol. 33, No. 8, pp. 1208-1218, DOI: 10.1109/TCAD.2014.2323219, août 2014
 
20 Mancini S., Larabi Z., Mathieu Y., Toczek T., Pierrefeu L., Exploration of 3D grid caching strategies for ray-shooting, Journal of Real Time Image Processing, Ed. Springer , Vol. 7, No. 1, pp. 3-19, DOI: 10.1007/s11554-010-0176-3, mars 2014
 
21 Prost-Boucle A., Muller O., Rousseau F., Fast and Standalone Design Space Exploration for High-Level Synthesis under Resource Constraints, Journal of Systems Architecture (JSA), Ed. Elsevier, Vol. 60, No. 1, pp. 79-93, DOI: 10.1016/j.sysarc.2013.10.002, janvier 2014
 
22 Foroutan S., Thonnard Y., Pétrot F., An Iterative Computational Technique for Performance Evaluation of Networks-on-Chip, IEEE Transactions on Computers, Ed. IEEE, Vol. 62, No. 8, pp. 1641-1655, DOI: 10.1109/TC.2012.85, août 2013
 
23 Dubois F., Sheibanyrad H., Pétrot F., Bahmani M., Elevator-First: A Deadlock-Free Distributed Routing Algorithm for Vertically Partially Connected 3D-NoCs, IEEE Transactions on Computers, Ed. IEEE, Vol. 62, No. 3, pp. 609-615, DOI: 10.1109/TC.2011.239, février 2013
 
24 Rahmouni K., Chabanet S., Lambelin S., Pétrot F., Design of a medium voltage protection device using system simulation approaches: a case study, IJES - International Journal of Embedded Systems , Ed. InderScience Publishers, Vol. 5, No. 1-2, pp. 53-66, DOI: 10.1504/IJES.2013.052144, janvier 2013
 
25 Horrein P.H., Hennebert Ch., Pétrot F., An environment for (re)configuration and execution management of heterogeneous flexible radio platforms, Microprocessors and Microsystems, Ed. Elsevier, Vol. 37, No. 6-7, pp. 701-712, DOI: 10.1016/j.micpro.2012.06.002, janvier 2013
 
26 Horrein P.H., Hennebert Ch., Pétrot F., Integration of GPU Computing in a Software Radio Environment, Journal of Signal Processing Systems, Ed. Springer , Vol. 69, No. 1, pp. 55-65, DOI: 10.1007/s11265-011-0639-1, octobre 2012
 
27 Shen H., Hamayun M.M., Pétrot F., Native Simulation of MPSoC Using Hardware-Assisted Virtualization, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Ed. IEEE, Vol. 31, No. 7, pp. 1074 - 1087 , DOI: 10.1109/TCAD.2012.2187526, janvier 2012
 
28 Pétrot F., Gligor M., Hamayun M.M., Shen H., Fournel N., Gerin P., On MPSoC Software Execution at the Transaction Level, IEEE Design and Test of Computers, Ed. IEEE, Vol. 28, No. 3, pp. 32-43, DOI: 10.1109/MDT.2010.118 , janvier 2011
 
29 Muller O., Baghdadi A., Jézéquel M., Parallelism Efficiency in Convolutional Turbo Decoding, Eurasip Advances in Signal Processing, Ed. Hindawi Publishing Corporation, Vol. vol. 2010, Article ID 927920, pp. 11 pages, DOI: 10.1155/2010/927920, 2010
 
30 Meunier Q., Pétrot F., Lightweight Transactional Memory systems for NoCs based architectures: Design, implementation and comparison of two policies, Journal of Parallel and Distributed Computing (JPDC), Ed. Academic Press, London, UK, Vol. 70, No. 10, pp. 1024-1041, DOI: 10.1016/j.jpdc.2010.02.007, octobre 2010
 
31 Meunier Q., Pétrot F., Roch J.-L., Hardware/software support for adaptive work-stealing in on-chip multiprocessor, Journal of Systems Architecture (JSA), Ed. Elsevier, Vol. 56, No. 8, pp. 392-406, DOI: 10.1016/j.sysarc.2010.06.007, août 2010
 
32 Guironnet de Massas P., Pétrot F., Evaluation of the implementation cost of cache coherence protocols using omniscient actions , Design Automation for Embedded Systems, Ed. Springer , Vol. 14, No. 1, pp. 21-42, DOI: 10.1007/s10617-010-9050-6 , janvier 2010
 
33 Huang K., Yan X., Han Sang-Il, Chae Soo-Ik, Jerraya A. A., Popovici K.M., Guérin X., Brisolara L., Carro L., Gradual Refinement for Application Specific MPSoC Design from Simulink Model to RTL Implementation, Journal of Zhejiang University SCIENCE A (JZUS-A), Ed. Springer , Vol. 10, Number 2, February , pp. 151-164, DOI: 10.1631/jzus.A0820085 , février 2009
 
34 Han Sang-Il, Chae Soo-Ik, Brisolara L., Carro L., Popovici K.M., Guérin X., Jerraya A. A., Huang K., Li L., Yan X., Simulink(R) based Heterogeneous Multiprocessor SoC Design Flow for Mixed Hardware/Software refinement and simulation, Integration, the VLSI Journal, Ed. Elsevier, Vol. 42, No. 2, pp. 227-245, DOI: 10.1016/j.vlsi.2008.08.003 , février 2009
 
35 Metzger M., Anane A., Rousseau F., Vachon J., Aboulhamid E.M., Introspection Mechanisms for Runtime Verification in a System-Level Design Environment, Microelectronics journal, Ed. Elsevier, Vol. 40, No. 7, pp. 1124-1134, DOI: 10.1016/j.mejo.2008.04.010, janvier 2009
 
36 Kriaa L., Bouchhima A., Gligor M., Fouillard A.-M., Pétrot F., Jerraya A. A., Parallel Programming of Multi-Processor SoC : A HW-SW Interface perspective, Journal of Parallel Programming, Ed. Springer , Vol. 36, No. 1, pp. 68-92, DOI: 10.1007/s10766-007-0042-5, janvier 2008
 
37 Popovici K.M., Guérin X., Rousseau F., Paolucci P.S., Jerraya A. A., Platform based software design flow for heterogeneous MPSoC, Transactions on Embedded Computing Systems (TECS), Ed. ACM, NY, USA, Vol. 7, No. 4, pp. 27-50, DOI: 10.1145/1376804.1376807, janvier 2008
 
38 Sheibanyrad H., Greiner A., Miro-Panades I., Multisynchronous and Fully Asynchronous NoCs for GALS Architectures, IEEE Design and Test of Computers, Ed. IEEE, Vol. 25, No. 6, pp. 572-580, DOI: 10.1109/MDT.2008.167 , janvier 2008
 
39 Guironnet de Massas P., Amblard P., Pétrot F., On SPARC LEON-2 ISA Extensions Experiments for MPEG Encoding Acceleration, Journal of VLSI Design, Ed. Hindawi Publishing Corporation, Vol. 2007, pp. 10 p., DOI: 10.1155/2007/28686 , 2007
 
40 Lapalme J., Aboulhamid E.M., Nuta Nicolescu E.G., Rousseau F., Separating modeling and simulation aspects in hardware/software framework-based modeling languages , The Arabian Journal for Science and Engineering, Vol. 32, No. 2C, pp. 41 - 60, décembre 2007
 
41 Senouci B., Bouchhima A., Rousseau F., Jerraya A. A., Prototyping Multiprocessor System-on-Chip Applications: A Platform-Based Approach, IEEE Distrubuted Systems Online, Ed. IEEE, Vol. 8, No. 5, pp. 2, DOI: 10.1109/MDSO.2007.28 , janvier 2007
 
42 Han Sang-Il, Chae Soo-Ik, Brisolara L., Carro L., Reis R., Guérin X., Jerraya A. A., Memory-efficient multithreaded code generation from Simulink for heterogeneous MPSoC, Design Automation for Embedded Systems, Ed. Springer , Vol. 11, No. 4, pp. 249-283, DOI: 10.1007/s10617-007-9009-4, janvier 2007
 
43 Zergainoh N.-E., Tambour L., Urard P., Jerraya A. A., Macrocell builder: IP block-based design Environment for high-throughput VLSI dedicated digital signal processing systems, Journal on Applied Signal Processing, Vol. 2006, No. 1/Article ID 28636, pp. 1-11, DOI: 10.1155/ASP/2006/28636, décembre 2006
 
44 Zergainoh N.-E., Tambour L., Jerraya A. A., Automatic delay correction method for IP block-based design of VLSI dedicated digital signal processing systems: theoretical foundations and implementation, Transactions on Very Large Scale Integration (VLSI) Systems, Ed. IEEE, Vol. 14, No. 4, pp. 349- 360, janvier 2006
 
45 Jerraya A. A., Wolf W., Tenhunen H., Multiprocessor Systems-on-Chips , Computer, Ed. IEEE, Vol. 38, No. 7, pp. 36-40, DOI: 10.1109/MC.2005.231, juillet 2005
 
46 Yoo S., Jerraya A. A., Introduction to hardware abstraction layers for SoC, Computer, Ed. IEEE, Vol. 38, No. 2, pp. 63-69, DOI: 10.1109/MC.2005.61, février 2005
 
47 Yoo S., Jerraya A. A., Hardware/Software cosimulation from interface perspective, IEE Proceedings Computers and Digital Techniques, Ed. IEEE, Vol. 152, No. 3, pp. 369-379, DOI: 10.1049/ip-cdt:20045113, janvier 2005
 
48 Bacivarov I., Bouchhima A., Yoo S., Jerraya A. A., ChronoSym – a New Approach for Fast and Accurate SoC Cosimulation, IJES - International Journal of Embedded Systems , Ed. InderScience Publishers, Vol. 1, No. 1-2, pp. 103-111, DOI: 10.1504/IJES.2005.008812, janvier 2005
 
49 Jerraya A. A., Wolf W., Hardware/software interface codesign for embedded systems, Computer Review, Vol. 38, No. 2, pp. 63-69, DOI: 10.1109/MC.2005.61, janvier 2005
 
50 Zergainoh N.-E., Baghdadi A., Jerraya A. A., Hardware/software codesign of on-chip communication architecture for application-specific multiprocessor system-on-chip, IJES - International Journal of Embedded Systems , Ed. InderScience Publishers, Vol. 1/2, No. 1, pp. 112-124, janvier 2005
 
51 Augé I., Pétrot F., Donnet F., Gomez P., Platform-based design from parallel C specifications, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Ed. IEEE, Vol. Volume: 24, No. 12, pp. 1811- 1826, DOI: 10.1109/TCAD.2005.852431, janvier 2005
 
52 Zergainoh N.-E., Baghdadi A., Jerraya A. A., A generic architecture platform based-methodology for an efficient design of Hardware/Software application-specific multiprocessor System-On-Chip , Annals of Telecommunications - annales des télécommunications, Ed. Springer , Vol. 59, No. 7-8, pp. 784-806, juillet-août 2004
 
53 Wagner F.R., Cesario W., Carro L., Jerraya A. A., Strategies for the integration of hardware and software IP components in embedded systems-on-chip, Integration, the VLSI Journal, Ed. Elsevier, Vol. 37, No. 4, pp. 223-252, DOI: 10.1016/j.vlsi.2003.12.005, avril 2004
 
54 Cesario W., Gauthier L., Lyonnard D., Nuta Nicolescu E.G., Jerraya A. A., Object-based hardware/software component interconnection model for interface design in system-on-a-chip circuits, Journal of Systems and Software, Ed. Elsevier, Vol. 70, No. 3, pp. 229-244, DOI: 10.1016/S0164-1212(03)00071-2, mars 2004
 
55 Sasongko A., Baghdadi A., Rousseau F., Jerraya A. A., Towards SoC Validation Through Prototyping: A Systematic Approach Based on Reconfigurable Platform, Design Automation for Embedded Systems, Ed. Springer , Vol. 8, No. 2, pp. 155-171, DOI: 10.1023/B:DAEM.0000003960.00662.d7, juin 2003
 
56 Voros N.S., Sanchez L., Alonso A., Birbas A.N, Birbas M., Jerraya A. A., Hardware/Software Co-Design of Complex Embedded Systems: An Approach Using Efficient Process Models, Multiple Formalism Specification and Validation via Co-Simulation, Design Automation for Embedded Systems, Ed. Springer , Vol. 8, No. 1, pp. 5-49, DOI: 10.1023/A:1022388018837, mars 2003
 
57 Jerraya A. A., Baghdadi A., Cesario W., Gauthier L., Lyonnard D., Nuta Nicolescu E.G., Paviot Y., Application-specific multiprocessor systems-on-chip, Microelectronics journal, Ed. Elsevier, Vol. 33, No. 11, pp. 891-898, DOI: 10.1016/S0026-2692(02)00070-8, novembre 2002
 
58 Cesario W., Lyonnard D., Nuta Nicolescu E.G., Paviot Y., Yoo S., Jerraya A. A., Gauthier L., Diaz-Nava M., Multiprocessor SoC platforms: a component-based design approach, IEEE Design and Test of Computers, Ed. IEEE, Vol. 19, No. 6, pp. 52 - 63, DOI: 10.1109/MDT.2002.1047744, novembre-décembre 2002
 
59 Baghdadi A., Zergainoh N.-E., Cesario W., Jerraya A. A., Combining a performance estimation methodology with a hardware/software codesign flow supporting multiprocessor systems, IEEE Transactions on Software Engineering, Ed. IEEE, Vol. 28, No. 9, pp. 822 - 831, DOI: 10.1109/TSE.2002.1033223, septembre 2002
 
60 Gauthier L., Yoo S., Jerraya A. A., Automatic generation and targeting of application-specific operating systems and embedded systems softwar, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Ed. IEEE, Vol. 20, No. 11, pp. 1293-1301, DOI: 10.1109/43.959858, novembre 2001
 
61 Cesario W., Nuta Nicolescu E.G., Gauthier L., Lyonnard D., Jerraya A. A., Colif: A design representation for application-specific multiprocessor SOCs, IEEE Design and Test of Computers, Ed. IEEE, Vol. 18, No. 5, pp. 8-20, DOI: 10.1109/54.953268, septembre-octobre 2001
 
62 Souani C., Abid M., Torki K., Tourki R., VLSI design of 1-D DWT architecture with parallel filters, Integration, the VLSI Journal, Ed. Elsevier, Vol. 29, No. 2, pp. 181-207, DOI: 10.1016/S0167-9260(00)00007-9, septembre 2000
 
63 Hessel F., Coste P., Le Marrec Ph., Zergainoh N.-E., Nuta Nicolescu E.G., Daveau J.- M., Jerraya A. A., Interlanguage Communication Synthesis for Heterogeneous Specifications, Design Automation for Embedded Systems, Ed. Springer , Vol. 5, No. 3-4, pp. 223-236, DOI: 10.1023/A:1008945917092, août 2000
 
64 Valderrama C., Nacabal F., Paulin P., Jerraya A. A., Automatic VHDL-C Interface Generation for Distributed Cosimulation: Application to Large Design Examples, Design Automation for Embedded Systems, Ed. Springer , Vol. 3, No. 2-3, pp. 199-217, DOI: 10.1023/A:1008898525388, juin 1998
 
65 Marchioro G.F., Daveau J.- M., Ismail T., Jerraya A. A., Transformational partitioning for codesign, IEE Proceedings Computers and Digital Techniques, Ed. IEEE, Vol. 145, No. 3, pp. 181-95, DOI: 10.1049/ip-cdt:19981971, mai 1998
 
66 Abid M., Ben Ismail T., Changuel A., Valderrama C., Romdhani A., Marchioro G.F., Daveau J.- M., Jerraya A. A., Methodology for design of embedded systems, Integrated Computer-Aided Engineering, Ed. IOS Press, Vol. 5, No. 1, pp. 69-83, janvier 1998
 
67 Freund L., Israel M., Rousseau F., Berge J.M., Auguin M., Belleudy C., Gogniat G., A codesign experiment in acoustic echo cancellation: GMDFα, Transactions on Design Automation of Electronic Systems (TODAES), Ed. ACM, NY, USA, Vol. 2, No. 4, pp. 365-383 , DOI: 10.1145/268424.268433, octobre 1997
 
68 Jemai A., Kission P., Jerraya A. A., Combining architectural simulation and behavioral synthesis, IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Vol. E80-A, No. 10, pp. 1756-1766, octobre 1997
 
69 Abid M., Jerraya A. A., Towards hardware-software co-design: a case study of robot arm controller, Journal of Microelectronic System Integration, Ed. Plenum Press, Vol. 5, No. 3, pp. 167-182, septembre 1997
 
70 Kission P., Jerraya A. A., Behavioral design allowing modularity and component reuse, Journal of Microelectronic System Integration, Ed. Plenum Press, Vol. 5, No. 2, pp. 67-83, juin 1997
 
71 Valderrama C., Changuel A., Jerraya A. A., Virtual prototyping for modular and flexible hardware-software systems, Design Automation for Embedded Systems, Ed. Springer , Vol. 2, No. 3-4, pp. 267 - 282, DOI: 10.1023/A:1008829719142, mai 1997
 
72 Nacabal F., Valderrama C., Paulin P., Jerraya A. A., System-on-a-Chip Cosimulation and Compilation, IEEE Design and Test of Computers, Ed. IEEE, Vol. 14, No. 2, pp. 16-25, DOI: 10.1109/54.587736, avril-juin 1997
 
73 Goossens G., Van Praet J., Lanneer D., Geurts W., Kifli A., Liem Cl. B., Paulin P., Embedded software in real-time signal processing systems: design technologies, Proceedings of the IEEE , Ed. IEEE, Vol. 85, No. 3, pp. 436-454, DOI: 10.1109/5.558718, mars 1997
 
74 Daveau J.- M., Marchioro G.F., Ben Ismail T., Jerraya A. A., Protocol selection and interface generation for HW-SW codesign, Transactions on Very Large Scale Integration (VLSI) Systems, Ed. IEEE, Vol. 5, No. 1, pp. 136 - 144, DOI: 10.1109/92.555993, mars 1997
 
75 Liem Cl. B., Paulin P., Jerraya A. A., Compilation Methods for the Address Calculation Units of Embedded Processor Systems, Design Automation for Embedded Systems, Ed. Springer , Vol. 2, No. 1, pp. 71-77, DOI: 10.1023/A:1008862510877, janvier 1997
 
76 Sahroui A.E.K., Romdhani A., Jeffroy A., Jerraya A. A., Co-specification for co-design in the development of avionics systems, Control Engineering Practice, Ed. IFAC - International Federation of Automatic Control, Vol. 4, No. 6, pp. 871-876, DOI: 10.1016/0967-0661(96)00080-9, juin 1996
 
77 Ben Ismail T., Daveau J.- M., O'Brien K., Jerraya A. A., A system-level communication synthesis approach for hardware/software systems, Microprocessors and Microsystems, Ed. Elsevier, Vol. 20, No. 3, pp. 149-157, DOI: 10.1016/0141-9331(95)01072-6, mars 1996
 
78 Ismail T., O'Brien K., Jerraya A. A., PARTIF: interactive system-level partitioning, Journal of VLSI Design, Ed. Hindawi Publishing Corporation, Vol. 3, No. 3-4, pp. 333-345, mars-avril 1995
 
79 Ismail T., Jerraya A. A., Synthesis steps and design models for codesign, Computer, Ed. IEEE, Vol. 28, No. 2, pp. 44-52, DOI: 10.1109/2.347999, février 1995
 
80 Rahmouni M., O'Brien K., Jerraya A. A., A loop-based scheduling algorithm for hardware description languages, Parallel Processing Letters, Vol. 4, No. 3, pp. 351-364, mars 1994
 
remonter

5 Brevets

1 Rousseau F., Lock manager for multi-core architectures, No. 1858803, 26 septembre 2018
 
2 Mancini S., Vincent L., Procédé de prédiction d'une donnée à précharger dans une mémoire cache, No. 16201190.2-1953, 20 janvier 2017
 
3 Schwambach V., Procédé et dispositif de génération d’une représentation multi-résolutions d’une image et application à la détection d’objet utilisant une fenêtre de détection, No. 1553461, 17 avril 2015
 
4 Pétrot F., Sheibanyrad H., Architecture de communication à base de sérialiseur asynchrone entre circuits déposés sur des substrats de silicium empilés, No. 09/53637, 1 juin 2009
 
5 Sahnine C., Pétrot F., Composant de traitement d'un signal numérique, dispositif de modulation et/ou de démodulation multiporteuse, procédé de modulation et/ou de démodulation et programme d'ordinateur correspondants , No. WO/2008/145915 / PCT/FR2008/050703, 4 décembre 2008
 
remonter

20 Conférences invitées

 1 Pétrot F., Anghel L., Andrade Porras L.L., State of the art in hardware-accelerated neural networks, Invited Talk, Applied Machine Learning Days (AMLD 2020), Lausanne, SWITZERLAND, 27 au 29 janvier 2020
 
 2 Pétrot F., Prost-Boucle A., Bourge A., High-Throughput and High-Accuracy Classification with Convolutional Ternary Neural Networks, Invited Talk, International Workshop on Highly Efficient Neural Processing (HENP'2018), Torino, ITALY, 4 octobre 2018
 
 3 Rousseau F., Communication Consistency for Hardware Context Switch on Heterogeneous FPGAs, Invited paper, 18th International Forum on MPSoC (MPSoC'2018), Salt Lake City, UNITED STATES, 29 juillet au 3 août 2018
 
 4 Pétrot F., Prost-Boucle A., Bourge A., High-Throughput Ternary CNN on FPGA: Low Level Optimizations and Compression, Invited Talk, 18th International Forum on MPSoC (MPSoC'2018), Snowbird, UTAH, UNITED STATES, 29 juillet au 3 août 2018
 
 5 Pétrot F., Simulation rapide des systèmes multiprocesseurs, Séminaire invité, Architecture, hier, aujourd'hui, demain", Colloque en l'honneur de Michel Auguin, Daniel Etiemble et Bernard Goossens, Toulouse, FRANCE, 2 juillet 2018
 
 6 Herkersdorf A., Pétrot F., Effective System Level Simulation Techniques and Cross-Layer Perspectives on Low Power Design, Invited Tutorial, Design, Automation and Test in Europe (DATE'2018), Dresden, GERMANY, 19 au 23 mars 2018
 
 7 Andrade Porras L.L., Prost-Boucle A., Pétrot F., Overview of the State of the Art in Embedded Machine Learning, Invited talk (Special Session), Design, Automation & Test in Europe Conference & Exhibition (DATE'2018), pp. 1-6, Dresden, GERMANY, DOI: 10.23919/DATE.2018.8342164, 19 au 23 mars 2018
 
 8 Rousseau F., Accurate Study and Optimization of Synchronization Barriers in a NoC based MPSoC Architecture, Invited Talk, Forum MPSoC 2017, Annecy, FRANCE, 2 au 7 juillet 2017
 
 9 Montémont G., Monnet O., Stanchina S., Bernard M., Verger L., Recent Improvements to HiSPECT Imaging Module, Invited Talk, IEEE Nuclear Science Symposium (NSS/MIC'16), Strasbourg, FRANCE, 29 octobre au 6 novembre 2016
 
10 Rousseau F., Efficient Hardware Context-Switch for Task Migration between Heterogeneous FPGA, Invited Talk, 16th International Forum on MPSoC, Nara, JAPAN, 11 au 15 juillet 2016
 
11 Pétrot F., On the analysis of virtual platform generated traces, Invited Talk, 16th International Forum on MPSoC, Nara, JAPAN, 11 au 15 juillet 2016
 
12 Pétrot F., Simulation rapide et précise de systèmes manycore, Invited Talk, Ecole d'hiver Francophone sur les Technologies de Conception des Systèmes embarqués Hétérogènes, Vilard de Lans, FRANCE, 6 au 8 janvier 2016
 
13 Pétrot F., Some Design Issues for 3D NoCs : From Circuits to Systems, Keynote in 8th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC'14), Darmstadt, GERMANY, 18 avril au 20 mai 2014
 
14 Pétrot F., Advanced Virtual Prototyping of Multiprocessor SoCs, Invited talk (Special Session), IEEE Symposium on Low-Power and High-Speed Chips (Cool Chips'14), Yokohama, JAPAN, 18 au 20 avril 2012
 
15 Pétrot F., An analytical model for Many-Functionally Asymmetric Core SoC Architectures, 11th International Forum on Embedded MPSoC and Multicore, Beaune, FRANCE, 4 au 8 juillet 2011
 
16 Pétrot F., Fouillard A.-M., Simulation based hardware/software power management exploration for SMP MPSoC, Invited Tutorial, MEDEA+ Desgin Automation Conference, Leuven, BELGIUM, 1 mai 2008
 
17 Popovici K.M., Jerraya A. A., Simulink based Hardware-Software Codesign Flow for Heterogeneous MPSoC, Summer Computer Simulation Conference (SCSC'07), pp. 497-504, San Diego, CA, UNITED STATES, 15 au 18 juillet 2007
 
18 Jerraya A. A., Application specific multi-processor system on chip, Invited Talk, First Advanced Computing Workshop Trends in Embedded Computing, Autrans, FRANCE, 12 au 13 décembre 2000
 
19 Zergainoh N.-E., Marchioro G.F., Jerraya A. A., Hw/Sw codesign of an ATM network interface card starting from a system level specification, URSI International Symposium on Signals, Systems, and Electronics (ISSSE'98), pp. 315-320, Pisa, ITALY, DOI: 10.1109/ISSSE.1998.738090, 29 septembre au 2 octobre 1998
 
20 Zergainoh N.-E., Marchioro G.F., Daveau J.- M., Jerraya A. A., Using SDL for hardware/software co-design of an ATM network interface card, 1st Workshop of the forum society on SDL and MSC, Berlin, GERMANY, 29 juin au 1 juillet 1998
 
remonter

320 Conférences internationales

  1 Perais A., Leveraging Targeted Value Prediction to Unlock New Hardware Strength Reduction Potential, IEEE/ACM International Symposium on Microarchitecture (MICRO 2021), Athens, GREECE, DOI: 10.1145/3466752.3480050, 18 au 26 octobre 2021
 
  2 Trevisan Jost T., Durand Y., Fabre Ch., Cohen A., Pétrot F., Seamless Compiler Integration of Variable Precision Floating-Point Arithmetic, International Symposium on Code Generation and Optimization (CGO 2021), Atlanta, UNITED STATES, 27 février au 3 mars 2021
 
  3 Morgan F., Beretta A., Gallivan I., Clancy J., Rousseau F., Callaly F., RISC-V Online Tutor and Lab, International Conference on Remote Engineering and Virtual Instrumentation (REV 2021), Hong Kong, HONG KONG, 24 au 26 février 2021
 
  4 Badaroux M., Pétrot F., Arbitrary and Variable Precision Floating-Point Arithmetic Support in Dynamic Binary Translation, 26th Asia and South Pacific Design Automation Conference (ASP-DAC 2021), Tokyo (Virtual event), JAPAN, DOI: 10.1145/3394885.3431416, 18 au 21 janvier 2021
 
  5 Fernandez-Mesa B.J., Andrade Porras L.L., Pétrot F., Simulation of Ideally Switched Circuits in SystemC, Asia and South Pacific Design Automation Conference (ASP-DAC 2021), Tokyo, JAPAN, DOI: 10.1145/3394885.3431417, 18 au 21 janvier 2021
 
  6 Leclaire N., Mancini S., Delnondedieu C., Henriques J.P., Efficient Implementation of Convolution and Winograd on ASMP Embedded Multicore Vector Processor, IEEE International Workshop on Signal Processing Systems (SIPS 2020), Coimbra (Virtual event), PORTUGAL, 20 au 22 octobre 2020
 
  7 Trevisan Jost T., Durand Y., Fabre Ch., Cohen A., Pétrot F., VP Float: First Class Treatment for Variable Precision Floating Point Arithmetic, International Conference on Parallel Architectures and Compilation Techniques (PACT 2020), pp. 355-356, Atlanta, UNITED STATES, 5 au 7 octobre 2020
 
  8 Pêcheux F., Andrade Porras L.L., Louërat M.-M., Bournias I., Chotin-Avot R., Genius D., Virtual Prototyping of Open Source Heterogeneous Systems with an Open Source Framework Featuring SystemC MDVP Extensions, Forum for Specification and Design Languages (FDL 2020), pp. 1-8, Kiel, GERMANY, DOI: 10.1109/FDL50818.2020.9232947, 15 au 17 septembre 2020
 
  9 De Vita A., Pau D., Di Benedetto L., Rubino A., Pétrot F., Licciardo G.D., Low Power Tiny Binary Neural Network with improved accuracy in Human Recognition Systems, Euromicro Conference on Digital System Design (DSD 2020), pp. 309-315, Kranj, SLOVENIA, DOI: DOI 10.1109/DSD51259.2020.00057, 26 au 28 août 2020
 
 10 France-Pillois M., Martin J., Rousseau F., Implementation and Evaluation of a Hardware Decentralized Synchronization Lock for MPSoCs, International Parallel and Distributed Processing Symposium (IPDPS 2020), pp. 1112-1121, New Orleans, UNITED STATES, DOI: 10.1109/IPDPS47924.2020.00117, 18 au 22 mai 2020
 
 11 Fernandez-Mesa B.J., Andrade Porras L.L., Pétrot F., Accurate and Efficient Continuous Time and Discrete Events Simulation in SystemC, Design, Automation and Test in Europe (DATE 2020), Grenoble, FRANCE, 9 au 13 mars 2020
 
 12 Alcantara Souza M., Cota Freitas H., Pétrot F., Coherence State Awareness in Way-Replacement Algorithms for Multicore Processors, Anais do XX Simpósio em Sistemas Computacionais de Alto Desempenho (WSCAD 2019), pp. 240-251, Campo Grande, BRAZIL, 16 au 18 novembre 2019
 
 13 Deschamps Cl., Pétrot F., Burton M., Jenn E., Gathering Memory Hierarchy Statistics in QEMU, Design and Verification Conference and Exhibition (DVCon 2019), pp. 1-8, Munich, GERMANY, 29 au 31 octobre 2019
 
 14 Bonicel L., Bohrer R., Leprettre B., Rousseau F., Pétrot F., Multi-Triggered Embedded Software Code Generation for Electrical Metering and Protection Applications, Workshop on Rapid System Prototyping (RSP 2019), New-York, UNITED STATES, 17 au 18 octobre 2019
 
 15 Fernandez-Brillet L., Leclaire N., Mancini S., Cleyet-Merle S., Nicolas M., Henriques J.P., Delnondedieu C., Speeding-up CNN inference through dimensionality reduction, Design and Architectures for Signal and Image Processing (DASIP 2019), Montreal, CANADA, 16 au 18 octobre 2019
 
 16 Fernandez-Brillet L., Mancini S., Cleyet-Merle S., Nicolas M., Tunable CNN Compression Through Dimensionality Reduction, IEEE International Conference on Image Processing (ICIP 2019), Taipei, TAIWAN, DOI: 10.1109/ICIP.2019.8803585, 22 au 25 septembre 2019
 
 17 Fernandez-Mesa B.J., Andrade Porras L.L., Pétrot F., Electronic System Level Design of Heterogeneous Systems: a Motor Speed Control System Case Study, IEEE International New Circuits and Systems Conference (NEWCAS 2019), Munich, GERMANY, 23 au 26 juin 2019
 
 18 Brignon E., Pierre L., Assertion-Based Verification through Binary Instrumentation, Design, Automation and Test in Europe (DATE'2019), Florence, ITALY, 25 au 29 mars 2019
 
 19 France-Pillois M., Martin J., Rousseau F., Accurate MPSoC prototyping platform and methodology for the studying of the Linux synchronization barrier slowdown issues, International Symposium on Rapid System Prototyping (RSP'2018), pp. 56-62, Torino, ITALY, 4 au 5 octobre 2018
 
 20 Baumela T., Gruber O., Muller O., Pétrot F., Message-Oriented Devices on FPGAs, International Symposium on Rapid System Prototyping (RSP 2018), pp. 8-14, Torino, ITALY, DOI: 10.1109/RSP.2018.8631987, 4 au 5 octobre 2018
 
 21 Chabot M., Pierre L., Nabais-Moreno A., Automated Testing for Cyber-physical Systems: From Scenarios to Executable Tests, Forum on specification & Design Languages (FDL'2018), Munich, GERMANY, 10 au 12 septembre 2018
 
 22 Dumas J., Guthmuller E., Pétrot F., Dynamic Coherent Cluster: A Scalable Sharing Set Management Approach, 29th International Conference on Application-ecific Systems, Architectures and Processors (ASAP'2018), pp. 1-8, Milano, ITALY, DOI: 10.1109/ASAP.2018.8445107, 10 au 12 juillet 2018
 
 23 France-Pillois M., Martin J., Rousseau F., Linux Synchronization Barrier on MPSoC: Hardware/Software Accurate Study and Optimization, International Conference on Application-Specific Systems, Architectures and Processors (ASAP 2018), pp. 1-4, Milano, ITALY, DOI: doi.org/10.1109/ASAP.2018.8445120, 10 au 12 juillet 2018
 
 24 Christodoulis G., Selva M., Broquedis F., Desprez F., Muller O., An FPGA target for the StarPU heterogeneous runtime system, 13th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (RECOSOC 2018), pp. 1-8, Lille, FRANCE, DOI: 10.1109/ReCoSoC.2018.8449373, 9 au 11 juillet 2018
 
 25 France-Pillois M., Martin J., Rousseau F., Optimization of the GNU OpenMP Synchronization Barrier in MPSoC, International Conference of Architecture of Computing Systems (ARCS'2018), pp. 57-69, Braunschweig, GERMANY, DOI: doi.org/10.1007/978-3-319-77610-1_5, 9 au 12 avril 2018
 
 26 Matoussi O., Pétrot F., A mapping approach between IR and binary CFGs dealing with aggressive compiler optimizations for performance estimation, 23rd Asia and South Pacific Design Automation Conference (ASPDAC'2018), pp. 452-457, Jeju, KOREA, DOI: 10.1109/ASPDAC.2018.8297365, 22 au 25 janvier 2018
 
 27 Wicaksana A., Bourge A., Muller O., Sasongko A., Rousseau F., Prototyping Dynamic Task Migration on Heterogeneous Reconfigurable Systems, 28th International Symposium on Rapid System Prototyping: Shortening the Path from Specification to Prototype (RSP 2017), pp. 16-22, Seoul, KOREA, 19 au 20 octobre 2017
 
 28 Matoussi O., Pétrot F., IR-level annotation strategy dealing with aggressive loop optimizations for performance estimation in native simulation: work-in-progress, 12th IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis (ACM/IFIP 2017), pp. 13:1-13:2, Séoul, KOREA, 15 au 20 octobre 2017
 
 29 Prost-Boucle A., Bourge A., Pétrot F., Scalable high-performance architecture for convolutional ternary neural networks on FPGA, 27th International Conference on Field Programmable Logic and Applications (FPL 2017), pp. 1-7, Ghent, BELGIUM, 4 au 8 septembre 2017
 
 30 Bel Hadj Amor H., Sheibanyrad H., Pétrot F., A Distributed NUCA Architecture Using an Efficient NoC Multicasting Support, Euromicro Conference on Digital System Design (DSD 2017), pp. 184-191, Vienne, AUSTRIA, 30 août au 1 septembre 2017
 
 31 Faravelon A., Gruber O., Pétrot F., Optimizing Memory Access Performance Using Hardware Assisted Virtualization in Retargetable Dynamic Binary Translation, Euromicro Conference on Digital System Design (DSD 2017), pp. 40-46, Vienne, AUSTRIA, 30 août au 1 septembre 2017
 
 32 Dumas J., Guthmuller E., Fuguet Tortolero C., Pétrot F., Trace-driven exploration of sharing set management strategies for cache coherence in manycores, 15th IEEE International New Circuits and Systems Conference (NEWCAS 2017), pp. 77-80, Strasbourg, FRANCE, 25 au 28 juin 2017
 
 33 Bernard M., Montémont G., Stanchina S., Verger L., Mancini S., Adaptation of the Field of View of a Cardiac SPECT System in Real Time, The 14th International Meeting on Fully Three-Dimensional Image Reconstruction in Radiology and Nuclear Medicine (FULLY3D 2017), Xi'an, CHINA, DOI: 10.12059/Fully3D.2017-11-3202017, 18 au 23 juin 2017
 
 34 Bel Hadj Amor H., Sheibanyrad H., Pétrot F., A Meta-Routing Method to Create Multiple Virtual Logical Networks on a Single Hardware NoC, 2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2017), pp. 200-205, Bochum, GERMANY, DOI: 10.1109/ISVLSI.2017.43, 3 au 5 juin 2017
 
 35 Alemdar H., Leroy V., Prost-Boucle A., Pétrot F., Ternary neural networks for resource-efficient AI applications, 2017 International Joint Conference on Neural Networks (IJCNN 2017), pp. 2547-2554, Anchorage, AK, UNITED STATES, DOI: 10.1109/IJCNN.2017.7966166, 14 au 19 mai 2017
 
 36 Dumas J., Guthmuller E., Fuguet Tortolero C., Pétrot F., A Method for Fast Evaluation of Sharing Set Management Strategies in Cache Coherence Protocols, 30th International Conference on Architecture of Computing Systems (ARCS 2017), pp. 111-123, Vienna, AUSTRIA, DOI: 10.1007/978-3-319-54999-6_9, 3 au 6 avril 2017
 
 37 Matoussi O., Pétrot F., Modeling instruction cache and instruction buffer for performance estimation of VLIW architectures using native simulation, Design, Automation & Test in Europe Conference & Exhibition (DATE 2017), pp. 266-269, Lausanne, SWITZERLAND, DOI: 10.23919/DATE.2017.7926995, 27 au 31 mars 2017
 
 38 Hadj Salem K., Kieffer Y., Mancini S., Minimisation du temps total de traitement pour optimiser le fonctionnement d’un contrôleur de buffers pour les systèmes de vision embarquée, 18ème édition du congrès annuel de la Société Française de Recherche Opérationnelle et d'Aide à la Décision (ROADEF 2017), Metz, FRANCE, 22 au 24 février 2017
 
 39 Matoussi O., Pétrot F., Loop aware IR-level annotation framework for performance estimation in native simulation, 22nd Asia and South Pacific Design Automation Conference (ASPDAC 2017), pp. 220-225, Chiba, JAPAN, DOI: 10.1109/ASPDAC.2017.7858323, 16 au 19 janvier 2017
 
 40 Alcantara O., Costa W., Fresse V., Rousseau F., A survey of NoC evaluation platforms on FPGAs, International Conference on Field-Programmable Technology, Xi'an, CHINA, 7 au 9 décembre 2016
 
 41 Bernard M., Montémont G., Stanchina S., Mancini S., Real-Time Processing for an Adaptable SPECT System Based on CZT Detectors, IEEE Nuclear Science Symposium (NSS/MIC'16), Strasbourg, FRANCE, 26 octobre au 6 novembre 2016
 
 42 Hadj Salem K., Kieffer Y., Mancini S., Memory Management in Embedded Vision Systems: Optimization Problems and Solution Methods, The Conference on Design, Architectures for Signal and Image Processing (DASIP'16), Rennes, FRANCE, 12 au 14 octobre 2016
 
 43 Wicaksana A., Prost-Boucle A., Muller O., Rousseau F., Automated Non-Regression Testing for Accelerator Prototyping on FPGA, International symposium on Rapid System Prototyping (RSP'16), pp. 45-51, Pittsbrugh, UNITED STATES, 6 au 7 octobre 2016
 
 44 Njoyah Ntafam P., Paire E., Clouard A., Pétrot F., Simulation driven insertion of data prefetching instructions for early software-on-SoC optimization, 2016 International Symposium on Rapid System Prototyping (RSP'16), pp. 93-99, Pittsburgh, PA, UNITED STATES, DOI: 10.1145/2990299.2990315, 6 au 7 octobre 2016
 
 45 Guy S., Mancini S., Prototyping a Panoptic Camera by means of High Level Synthesis: Demo, International Conference on Distributed Smart Camera, Paris, FRANCE, 12 au 15 septembre 2016
 
 46 Hadj Salem K., Kieffer Y., Mancini S., Formulation and Practical Solution for the Optimization of Memory Accesses in Embedded Vision Systems, The 9th International Workshop on Computational Optimization (WCO'16), Gdansk, POLAND, 11 au 14 septembre 2016
 
 47 Pontié S., Bourge A., Prost-Boucle A., Maistri P., Muller O., Leveugle R., Rousseau F., HLS-based methodology for fast iterative development applied to Elliptic Curve arithmetic, Euromicro/IEEE Conference on Digital System Design (DSD'16), pp. 511-518, Limassol, CYPRUS, DOI: 10.1109/DSD.2016.51, 31 août au 2 septembre 2016
 
 48 Hadj Salem K., Kieffer Y., Mancini S., Optimisation du Fonctionnement d’un Contrôleur de Buffers pour les Systèmes de Vision Embarquée, Conférence d’informatique en Parallélisme, Architecture et Système (ComPAS'16), Lorient, FRANCE, 5 au 7 juillet 2016
 
 49 Bernard M., Montémont G., Stanchina S., Mancini S., Enabling real-time reconstruction for high intrinsic resolution SPECT systems, IEEE-NPSS Real Time Conference (RT'16), Padova, ITALY, 5 au 10 juin 2016
 
 50 Vincent L., Mancini S., Lesecq S., Charles H.P., Model Free Adaptive Data Prefetching using Hypothesis Tests, DAC 2016 conference, WIP workshop, Austin, TX, UNITED STATES, 5 au 9 juin 2016
 
 51 Kieffer Y., Hadj Salem K., Mancini S., Multi-objective optimization for the scheduling of embedded vision accelerators, The 29th Conference of the European Chapter on Combinatorial Optimization (ECCO'16), Budapest, HUNGARY, 26 au 28 mai 2016
 
 52 Hadj Salem K., Kieffer Y., Mancini S., Efficient Algorithms for Memory Management in Embedded Vision Systems, The 11th IEEE International Symposium on Industrial Embedded Systems (SIES-WIP'16), Krakow, POLAND, 23 au 25 mai 2016
 
 53 Vivet P., Thonnard Y., Lemaire R., Beigné E., Bernard Ch., Darve F., Lattard D., Miro-Panades I., Santos Cr., Clermidy F., Cheramy S., Pétrot F., Flamand E., Michailos J., A 4x4x2 homogeneous scalable 3d network-on-chip circuit with 326mflit/s 0.66pj/b robust and fault-tolerant asynchronous 3d links, IEEE International Solid-State Circuits Conference (ISSCC'16), San Francisco, Ca, UNITED STATES, DOI: 10.1109/ISSCC.2016.7417949, 31 janvier au 4 février 2016
 
 54 Raffaëlli L., Vallée F., Fayolle G., De Souza Ph., Rouah X., Pfeiffer M., Géronimi S., Pétrot F., Ahiad S., Facing ADAS validation complexity with usage oriented testing, 8th European congress on EMBEDDED REAL TIME SOFTWARE AND SYSTEMS (ERTS'16), pp. 13, Toulouse, FRANCE, 27 au 29 janvier 2016
 
 55 Sarrazin G., Brunie N., Pétrot F., Virtual prototyping of floating point units, Workshop on Rapid Simulation and Performance Evaluation - Methods and Tools (Rapido'16), pp. 1-6, Prague, CZECH REPUBLIC, DOI: 10.1145/2852339.2852340, 18 au 20 janvier 2016
 
 56 Goulahsen A., Saade J., Pétrot F., Line coding methods for high speed serial links, International Symposium on Microelectronics (IMS'15), pp. 318-323, Orlando, FL, UNITED STATES, DOI: 10.4071/isom-2015-WA63 , 27 au 29 octobre 2015
 
 57 Payet M., Fresse V., Rousseau F., Dynamic Data Flow Analysis for NoC Based Application Synthesis, IEEE International Symposium on Rapid System Prototyping (RSP'15), pp. 61-67, Amsterdam, NETHERLANDS, 8 au 9 octobre 2015
 
 58 Schwambach V., Cleyet-Merle S., Issard A., Mancini S., Fast Parallel Appli- cation and Multiprocessor Design Space Exploration from Sequential Code, International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS), Amsterdam, NETHERLANDS, 4 au 9 octobre 2015
 
 59 El-Antably A., Gruber O., Fournel N., Rousseau F., Transparent and Portable Agent Based Task Migration for Data-Flow Applications on Multi-tiled Architectures, International Conference on Hardware/Software Codesign and System Synthesis (CODES-ISSS'15), pp. 183 - 192, Amsterdam, NETHERLANDS, DOI: 10.1109/CODESISSS.2015.7331381, 4 au 9 octobre 2015
 
 60 Schwambach V., Cleyet-Merle S., Issard A., Mancini S., Image Tiling for Embedded Applications with Non-Linear Constraints, Design & Architectures for Signal & Image Processing (DASIP 2015), Cracow, POLAND, 23 au 25 septembre 2015
 
 61 El-Antably A., Fournel N., Rousseau F., Integrating Task Migration Capability in Software Tool-Chain for Data-Flow Applications Mapped on Multi-tiled Architectures, Euromicro Conference on Digital System Design (DSD'15), pp. 33-40, Funchal, PORTUGAL, 26 au 28 août 2015
 
 62 Fresse V., Combes C., Payet M., Rousseau F., Methodological Framework for NoC Resources Dimensioning on FPGAs, International Workshop on Design and Performance of Networks on Chip (DPNoC'15), Belfort, FRANCE, 17 au 20 août 2015
 
 63 Schwambach V., Cleyet-Merle S., Issard A., Mancini S., Estimation rapide et précise de l’accélération d’applications séquentielles sur des multiprocesseurs embarqués, Conférence en Parallélisme, Architecture et Système (ComPAS’2015), Lille, FRANCE, 30 juin au 3 juillet 2015
 
 64 Schwambach V., Cleyet-Merle S., Issard A., Mancini S., Parana: Fast Parallel Application and Multiprocessor Design Space Exploration from Sequential Code, Design Automation Conference (DAC) Work-in-Progress Session, San Francisco, CA, UNITED STATES, 9 au 10 juin 2015
 
 65 Saade J., Goulahsen A., Picco A., Huloux J., Pétrot F., Low overhead, DC-Balanced and run length limited Line Coding, IEEE 19th Workshop on Signal and Power Integrity (SPI'15), pp. 1-4, Berlin, GERMANY, DOI: 10.1109/SaPIW.2015.7237405, 10 au 13 mai 2015
 
 66 Bourge A., Muller O., Rousseau F., Automatic High-Level Hardware Checkpoint Selection for Reconfigurable Systems , Field-Programmable Custom Computing Machines (FCCM'15), Vancouver, CANADA, 3 au 5 mai 2015
 
 67 Schwambach V., Cleyet-Merle S., Issard A., Mancini S., Estimating the Potential Speedup of Computer Vision Applications on Embedded Multiprocessors, DATE Friday Workshop on Heterogeneous Architectures and Design Methods for Embedded Image Systems (HIS 2015) , pp. 1-2, Grenoble, FRANCE, DOI: arXiv:1502.07446, 13 mars 2015
 
 68 Faravelon A., Fournel N., Pétrot F., Fast and accurate branch predictor simulation, Design, Automation & Test in Europe Conference & Exhibition (DATE'15), pp. 317-320, Grenoble, FRANCE, 9 au 13 mars 2015
 
 69 Bourge A., Muller O., Rousseau F., A Novel Method for Enabling FPGA Context-Switch, ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, pp. 261, Monterey, UNITED STATES, 22 au 24 février 2015
 
 70 Cunha M., Fournel N., Pétrot F., Collecting traces in dynamic binary translation based virtual prototyping platforms, Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools (RAPIDO'15), pp. 1-6, Amsterdam, NETHERLANDS, DOI: 10.1145/2693433.2693437, 21 janvier 2015
 
 71 Vincent L., Mancini S., Charles H.P., Lesecq S., Adaptive Data Prefetching for High Performance Processors, Workshop at the HIPEAC Conference High Performance Embedded Systems (HPES'15), Amsterdam, NETHERLANDS, 19 au 21 janvier 2015
 
 72 Alcantara O., Fresse V., Rousseau F., Evaluation of SNMP-like Protocol to Manage a NoC Emulation Platform, IEEE International Conference on Field-Programmable Technology (FPT'14), pp. 199-206, Shanghai, CHINA, DOI: 10.1109/FPT.2014.7082776, 10 au 12 décembre 2014
 
 73 Chen Hui, Godet-Bar G., Rousseau F., Pétrot F., Device driver generation targeting multiple operating systems using a model-driven methodology, IEEE International Symposium on Rapid System Prototyping (RSP'14), pp. 30-36, New Delhi, INDIA, DOI: 10.1109/RSP.2014.6966689, 16 au 17 octobre 2014
 
 74 El-Antably A., Fournel N., Rousseau F., Lightweight Task Migration in Embedded Multi-Tiled Architectures Using Task Code Replication, IEEE International Symposium on Rapid System Prototyping (RSP'14), pp. 93-99, Delhi, INDIA, DOI: 10.1109/RSP.2014.6966898, 16 au 17 octobre 2014
 
 75 Vincent L., Mancini S., Closed-loop Adaptive and Stochastic Prefetch Mechanism for Data Array, Conference on Design and Architectures for Signal and Image Processing (DASIP'14), Madrid, SPAIN, 8 au 10 octobre 2014
 
 76 Schor L., Bacivarov I., Murillo L.G., Paolucci P.S., Rousseau F., El-Antably A., Buecs R.L., Fournel N., Leupers R., Rai D., Thiele L., Tosoratto L., Vicini P., Weinstock J.H., EURETILE Design Flow: Dynamic and Fault Tolerant Mapping of Multiple Applications Onto Many-Tile Systems, IEEE International Symposium on Parallel and Distributed Processing with Applications (ISPA'14), pp. 182-189, Milano, ITALY, DOI: 10.1109/ISPA.2014.32, 26 au 28 août 2014
 
 77 Schwambach V., Cleyet-Merle S., Issard A., Mancini S., Application level Performance Optimization: A Computer Vision Case Study on STHORM, International Conference on Computational Science (ICCS) Workshop on Architecture, Languages, Compilation and Hardware support for Emerging ManYcore systems (ALCHEMY), pp. 1113-1122, Cairns, AUSTRALIA, DOI: 10.1016/j.procs.2014.05.100, 10 au 12 juin 2014
 
 78 Saade J., Goulahsen A., Picco A., Huloux J., Pétrot F., A Scalable Low Overhead Line Coding For Asynchronous High Speed Serial Transmission, 18th IEEE Workshop on Signal and Power Integrity (SPI'14), pp. 1-4, Ghent, BELGIUM, DOI: 10.1109/SaPIW.2014.6844527, 11 au 14 mai 2014
 
 79 Lagraa S., Termier A., Pétrot F., Scalability bottlenecks discovery in MPSoC platforms using data mining on simulation traces, Best Paper Award in Design Automation and Test in Europe (DATE'14), pp. 1-6, Dresden, GERMANY, DOI: 10.7873/DATE.2014.199, 24 au 28 mars 2014
 
 80 Fournel N., Michel L., Pétrot F., Automated generation of efficient instruction decoders for instruction set simulators, Conference on Computer Aided Design (ICCAD'13), pp. 739-746, San Jose, CA, UNITED STATES, DOI: 10.1109/ICCAD.2013.6691197, 18 au 21 novembre 2013
 
 81 Alcantara O., Fresse V., Rousseau F., FlexOE: A Congestion-Aware Routing Algorithm for NoCs, International Symposium on Rapid System Prototyping (RSP'13), pp. 23-29, Montréal, CANADA, 3 au 4 octobre 2013
 
 82 Pierre L., Pancher F., Suescun R., Quévremont J., On the Effectiveness of Assertion-Based Verification in an Industrial Context, 18th International Workshop on Formal Methods for Industrial Critical Systems (FMICS'13), pp. 78-93 , Madrid, SPAIN, DOI: 10.1007/978-3-642-41010-9_6, 23 au 24 septembre 2013
 
 83 Rousseau F., Fresse V., Tan J., Adaptive NoC-Based MPSoC System for Spectral Imaging Algorithm Dedicated to Art Authentication, 21st European Signal Processing Conference (EUSIPCO'13), Marrakech, MOROCCO, 9 au 13 septembre 2013
 
 84 Foroutan S., Akesson B., Goossens G., Pétrot F., A General Framework for Average-Case Performance Analysis of Shared Resources, Euromicro Conference on Digital System Design (DSD'13), pp. 78-85, Santander, SPAIN, DOI: 10.1109/DSD.2013.116, 4 au 6 septembre 2013
 
 85 Prost-Boucle A., Muller O., Rousseau F., Fast and Autonomous HLS Methodology for Hardware Accelerator Generation Under Resource Constraints, Euromicro Conference on Digital System Design (DSD'13), pp. 201 – 208, Santander, SPAIN, DOI: 10.1109/DSD.2013.30, 4 au 6 septembre 2013
 
 86 El-Antably A., Rousseau F., Lightweight task migration in embedded multi-tiled architectures using task code replication, Commuting Architectures Software tools and nano-Technologies for Numerical Embedded ans Scalable Systems (CASTNESS'13), Barcelona, SPAIN, 17 juin 2013
 
 87 Saade J., Pétrot F., Picco A., Huloux J., Goulahsen A., A system-level overview and comparison of three High-Speed Serial Links: USB 3.0, PCI Express 2.0 and LLI 1.0, Workshop on Design and Diagnostics of Electronic Circuits and Systems (DDECS'13), pp. 147-152, Karlovy Vary, CZECH REPUBLIC, DOI: 10.1109/DDECS.2013.6549807, 8 au 10 avril 2013
 
 88 Jaber M., Chagoya-Garzon A., Rousseau F., From System Model Formalization Towards Correct and Efficient HW/SW Design, 8th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS'13), pp. 85-90, Abu Dhabi, UNITED ARABIAN EMIRATES, 26 au 28 mars 2013
 
 89 Lagraa S., Termier A., Pétrot F., Data Mining MPSoC Simulation Traces to Identify Concurrent Memory Access Patterns, Design Automation and Test in Europe Conference (DATE'13), pp. 755-760, Grenoble, FRANCE, 18 mars 2013
 
 90 Butt S., Mancini S., Rousseau F., Lavagno L., Design of a pseudo-log image transform IP in an HLS-based memory management framework, Conference of Real-Time Image and Video Processing 2013, pp. 1-15, Burlingame, Ca, UNITED STATES, DOI: 10.1117/12.2004272, 6 au 7 février 2013
 
 91 Hamayun M.M., Pétrot F., Fournel N., Native simulation of complex VLIW instruction sets using static binary translation and Hardware-Assisted Virtualization, Asian South-Pacific Design Automation Conference (ASP-DAC'13), pp. 576-581, Yokohama, JAPAN, DOI: 10.1109/ASPDAC.2013.6509660, 22 au 25 janvier 2013
 
 92 Dubois F., Catalano V., Coppola M., Pétrot F., Accurate on-chip router Area modeling with Kriging methodology, International Conference on Computer-Aider Design (ICCAD'12), San José, CA, UNITED STATES, 5 au 8 novembre 2012
 
 93 Fresse V., Tan J., Rousseau F., Emulation platform for an adaptive NoC-based MPSoC architecture dedicated to spectral imaging for art authentication, International Conference on Image Processing Theory, Tools and Applications (IPTA'12), pp. 1-6, Istanbul, TURKEY, 15 au 18 octobre 2012
 
 94 Lagraa S., Termier A., Pétrot F., Automatic congestion detection in MPSoC programs using data mining on simulation traces, 23rd IEEE International Symposium on Rapid System Prototyping (RSP'12), pp. 64 - 70, Tampere, FINLAND, DOI: 10.1109/RSP.2012.6380692, 11 au 12 octobre 2012
 
 95 Fresse V., GE Zhiwei, Tan J., Rousseau F., Case Study: Deployment of the 2D NoC on 3D for the Generation of Large Emulation Platforms, 23rd International Symposium on Rapid System Prototyping (RSP'12), pp. 23-29, Tampere, FINLAND, DOI: 10.1109/RSP.2012.6380686, 11 au 12 octobre 2012
 
 96 Michel L., Fournel N., Pétrot F., Fast simulation of systems embedding VLIW processors, IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis (CODES+ISSS'12), pp. 143-150, Tampere, FINLAND, DOI: 10.1145/2380445.2380472, 7 au 12 octobre 2012
 
 97 Chagoya-Garzon A., Rousseau F., Pétrot F., Multi-Device Driver Synthesis Flow for Heterogeneous Hierarchical Systems, 15th Euromicro Conference on Digital System Design (DSD'12), pp. 389 - 396 , Izmir, TURKEY, DOI: 10.1109/DSD.2012.88 , 5 au 8 septembre 2012
 
 98 Xu Yan, Muller O., Horrein P.H., Pétrot F., HCM: An Abstraction Layer for Seamless Programming of DPR FPGA, 2nd International Conference on Field Programmable Logic and Applications (FPL'12), pp. 583 - 586, Oslo, NORWAY, DOI: 10.1109/FPL.2012.6339212 , 29 au 31 août 2012
 
 99 Bahmani M., Sheibanyrad H., Pétrot F., Dubois F., Durante P., A 3D-NoC Router Implementation Exploiting Vertically-Partially-Connected Topologies , IEEE Computer Society Annual Symposium on VLSI (ISVLSI'12), pp. 9-14, Amherst, Ma, UNITED STATES, DOI: 10.1109/ISVLSI.2012.19, 19 au 21 août 2012
 
100 Foroutan S., Sheibanyrad H., Pétrot F., Cost-efficient buffer sizing in shared-memory 3D-MPSoCs using wide I/O interfaces, The Design Automation Conference (DAC'12), pp. 366-375, San Francisco, CA, UNITED STATES, DOI: 10.1145/2228360.2228427, 3 au 7 juin 2012
 
101 Mancini S., Rousseau F., Enhancing Non-Linear Kernels by an Optimized Memory Hierarchy in a High Level Synthesis Flow, Design, Automation and Test in Europe (DATE'12), pp. 1130-1133, Dresden, GERMANY, 12 au 16 mars 2012
 
102 Hedde D., Pétrot F., Fast Memory Consistency Analysis using Non-Intrusive Simulation Traces, The System, Software, SoC and Silicon Debug Conference (S4D'11), pp. 17-22, Munich, GERMANY, 19 au 20 septembre 2011
 
103 Horrein P.H., Hennebert Ch., Pétrot F., An Environment for (re)configuration and Execution Managenment of Flexible Radio Platforms , 14th Euromicro Conference on Digital System Design (DSD’11), pp. 327-334, Oulu, FINLAND, DOI: 10.1109/DSD.2011.47, 31 août au 2 septembre 2011
 
104 Chagoya-Garzon A., Poste N., Rousseau F., Semi-Automation of Configuration Files Generation for Heterogeneous Multi-Tile Systems, Computer Software and Application Conference (COMPSAC’11), pp. 157 - 166 , Munich, GERMANY, DOI: 10.1109/COMPSAC.2011.28 , 18 au 21 juillet 2011
 
105 Darve F., Sheibanyrad H., Vivet P., Pétrot F., Physical Implementation of an Asynchronous 3D-NoC Router Using Serial Vertical Links, IEEE Computer Society Annual Symposium on VLSI (ISVLSI'11) , pp. 25 - 30 , Chennai, INDIA, DOI: 10.1109/ISVLSI.2011.59 , 4 au 6 juillet 2011
 
106 Hedde D., Pétrot F., A non intrusive simulation-based trace system to analyse Multiprocessor Systems-on-Chip software, 22nd IEEE International Symposium on Rapid System Prototyping (RSP’11), pp. 106-112, Karlsruhe, GERMANY, DOI: 10.1109/RSP.2011.5929983 , 24 au 27 mai 2011
 
107 Tan J., Fresse V., Rousseau F., Generation of emulation platforms for NoC exploration on FPGA , International Symposium on Rapid System Prototyping (RSP’11), pp. 186 - 192 , Karlshrue, GERMANY, DOI: 10.1109/RSP.2011.5929994 , 24 au 27 mai 2011
 
108 Chen Hui, Godet-Bar G., Rousseau F., Pétrot F., Me3D: A model-driven methodology expediting embedded device driver development , 22nd IEEE International Symposium on Rapid System Prototyping (RSP’11), pp. 171-177, Karlsruhe, GERMANY, DOI: 10.1109/RSP.2011.5929992 , 24 au 27 mai 2011
 
109 Dubois F., Cano J., Coppola M., Flich J., Pétrot F., Spidergon STNoC design flow , IEEE/ACM International Symposium on Networks on Chip (NoCS’11), pp. 267 - 268 , Pittsburg, Pa., UNITED STATES, 1 au 4 mai 2011
 
110 Michel L., Fournel N., Pétrot F., Speeding-up SIMD instructions dynamic binary translation in embedded processor simulation , Design Automation and Test in Europe Conference (DATE’11), pp. 277-280, Grenoble, FRANCE, 14 au 18 mars 2011
 
111 Shen H., Pétrot F., Using Amdahl’s Law for Performance Analysis of Many-Core SoC Architectures Based on Functionally Asymmetric Processors , 24th International Conference Architecture of Computing Systems (ARCS'11), pp. 38-49, Como, ITALY, DOI: 10.1007/978-3-642-19137-4_4, 24 au 25 février 2011
 
112 Gligor M., Pétrot F., Handling dynamic frequency changes in statically scheduled cycle-accurate simulation, 16th Asia and South Pacific Design Automation Conference (ASP-DAC’11), pp. 407 - 412 , Yokohama, JAPAN, DOI: 10.1109/ASPDAC.2011.5722224 , 25 au 28 janvier 2011
 
113 Hassan K., Pétrot F., Locatelli R., Coppola M., EEEP: an extreme end to end flow control protocol for SDRAM access through networks on chip, Fifth International Workshop on Interconnection Network Architecture: On-Chip, Multi-Chip (INA-OCMC '11), pp. 3-6, Heraklion, GREECE, DOI: 10.1145/1930037.1930039, 23 janvier 2011
 
114 Hedde D., Pétrot F., A Non-Intrusive Simulation-Based Trace System for Fine-Grain Analysis of Multiprocessor Systems-on Chips Software , The System, Software, SoC and Silicon Debug Conference (S4D'10), pp. 85-90 , Southampton, UNITED KINGDOM, 15 au 16 septembre 2010
 
115 El Mrabti A., Rousseau F., Pétrot F., Martin J., Lemaire R., Vaumorin E., Design Environment for the Support of Configurable Network Interfaces in NoC-based Platforms, International Conference on Embedded Computer Systems: Architectures, MOdeling and Simulation (SAMOS X), pp. 63-70, Samos, GREECE, 19 au 23 juillet 2010
 
116 Fresse V., Tan J., Rousseau F., Exploration of an adaptive NoC architecture on FPGA dedicated to multi and hysperspectral algorithm for art authentication, IEEE International Conference on Image Processing Theory, Tools and Applications (IPTA'10), pp. 529-534, Paris, FRANCE, DOI: 10.1109/IPTA.2010.5586801, 7 au 10 juillet 2010
 
117 Rahmouni K., Pétrot F., Improving the tests coverage of a medium voltage protection device using system simulation approaches, IEEE Symposium on Industrial Embedded Systems (SIES’10), pp. 184 - 187 , Trente, ITALY, DOI: 10.1109/SIES.2010.5551389 , 7 au 9 juillet 2010
 
118 Leveugle R., Prost-Boucle A., A new automated instrumentation for emulation-based fault injection, 1st IEEE Latin American Symposium on Circuits and Systems (LASCAS'10), pp. 220-223, Iguaçu Falls, BRAZIL, 24 au 26 février 2010
 
119 Shen H., Pétrot F., A flexible hybrid simulation platform targeting multiple configurable processors SoC, IEEE Asia South-Pacific Design Automation Conference (ASP-DAC’10), pp. 155-160, Taipei, TAIWAN, DOI: 10.1109/ASPDAC.2010.5419904 , 18 au 21 janvier 2010
 
120 Gerin P., Hamayun M.M., Pétrot F., Native MPSoC co-simulation environment for software performance estimation, 7th IEEE/ACM international conference on Hardware/software codesign and system synthesis (CODES+ISSS'09), pp. 403-412 , Grenoble, FRANCE, DOI: 10.1145/1629435.1629490, 11 au 16 octobre 2009
 
121 Gligor M., Fournel N., Pétrot F., Using Binary Translation in Event Driven Simulation for Fast and Flexible MPSoC Simulation, International Conference on Hardware-Software Codesign and System Synthesis (CODES+ISSS’09), pp. 71-80 , Grenoble, FRANCE, DOI: 10.1145/1629435.1629446, 11 au 16 octobre 2009
 
122 Gligor M., Fournel N., Pétrot F., Colas-Bigey F., Fouillard A.-M., Teninge Ph., Coppola M., Practical Design Space Exploration of an H264 Decoder for Handheld Devices Using a Virtual Platform, Power and Timing Modeling, Optimization and Simulation (PATMOS’09), Delft, NETHERLANDS, 9 au 11 septembre 2009
 
123 El Mrabti A., Sheibanyrad H., Rousseau F., Pétrot F., Lemaire R., Martin J., Abstract Description of System Application and Hardware Architecture for Hardware/Software Code Generation, 12th Euromicro Conference on Digital System Design (DSD’09), pp. 567 – 574, Patras, GREECE, 27 au 29 août 2009
 
124 Gligor M., Fournel N., Pétrot F., Adaptive Dynamic Voltage and Frequency Scaling Algorithm for Symmetric Multiprocessor Architecture , EUROMICRO Conference on Digital System Design Architectures, Methods and Tools (DSD’09), pp. 613 - 616, Patras, GREECE, 27 au 29 août 2009
 
125 Hedde D., Horrein P.H., Pétrot F., Rolland R., Rousseau Fra., A MPSoC prototyping platform for flexible radio applications, 12th Euromicro Conference on Digital System Design: Architecture, Methods and Tools (DSD’09), pp. 559-566, Patras, GREECE, 27 au 29 août 2009
 
126 Rahmouni K., Gerin P., Chabanet S., Pétrot F., Pianu P., Modelling and architecture exploration of a medium voltage protection device, IEEE Symposium on Industrial Embedded Systems (SIES’09), pp. 46-49, Lausanne, SWITZERLAND, DOI: 10.1109/SIES.2009.5196191 , 8 au 10 juillet 2009
 
127 Guérin X., Pétrot F., A System Framework for the Design of Embedded Software Targeting Heterogeneous Multi-Core SoCs, 20th IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP’09), pp. 153-160, Boston, MA., UNITED STATES, DOI: 10.1109/ASAP.2009.9, 7 au 9 juillet 2009
 
128 Meunier Q., Pétrot F., Lightweight Transactional Memory Systems for Large Scale Shared Memory MPSoCs , Joint 7th International IEEE Northeast Workshop on Circuits and Systems and TAISA Conference (NEWCAS-TAISA’09), pp. 432 - 435, Toulouse, FRANCE, 28 juin au 1 juillet 2009
 
129 Chagoya-Garzon A., Guérin X., Rousseau F., Pétrot F., Rossetti D., Lonardo A., Vicini P., Paolucci P.S., Synthesis of communication mechanisms for multi-tile systemsbased on heterogeneous Multi-processor System-on-Chips, 20th IEEE/IFIP International Symposium on Rapid System Prototyping(RSP'09), pp. 48-54, Paris, FRANCE, DOI: 10.1109/RSP.2009.12, 23 au 26 juin 2009
 
130 El Mrabti A., Pétrot F., Bouchhima A., Extending IP-XACT to support an MDE based approach for SoC design, Design Automation and Test in Europe (DATE’09), pp. 586-589 , Nice, FRANCE, 2 au 24 avril 2009
 
131 Bouchhima A., Gerin P., Pétrot F., Automatic instrumentation of embedded software for high level hardware/software co-simulation, Asia and South Pacific Design Automation Conference (ASP-DAC’09), pp. 546-551, Yokohama, JAPAN, DOI: 10.1109/ASPDAC.2009.4796537, 19 au 22 janvier 2009
 
132 Popovici K.M., Jerraya A. A., Flexible and Abstract Communication and Interconnect Modeling for MPSoC, Asia and South Pacific Design Automation Conference (ASP-DAC’09), pp. 143-148 , Yokohama, JAPAN, 19 au 22 janvier 2009
 
133 Shen H., Pétrot F., Novel Task Migration Framework on Configurable Heterogeneous MPSoC Platforms, 14th Asia and South Pacific Design Automation Conference (ASP-DAC’09), pp. 733-738, Yokohama, JAPAN, DOI: 10.1109/ASPDAC.2009.4796567, 19 au 22 janvier 2009
 
134 Kouadri Mostéfaoui A., Senouci B., Pétrot F., Large Scale On-Chip Networks : An Accurate Multi-FPGA Emulation Platform, 11th EUROMICRO Conference on Digital System Design Architectures Methods and Tools (DSD’08), pp. 3-9, Parma, ITALY, DOI: 10.1109/DSD.2008.130 , 3 au 5 septembre 2008
 
135 Chureau A., Pétrot F., An intermediate format for automatic generation of MPSoC virtual prototypes, International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (IC-SAMOS'08), pp. 165 - 172 , Samos, GREECE, DOI: 10.1109/ICSAMOS.2008.4664860, 21 au 24 juillet 2008
 
136 Shen H., Gerin P., Pétrot F., Configurable Heterogeneous MPSoC Architecture Exploration Using Abstraction Levels, Rapid System Prototyping Symposium (RSP’08), pp. 51-57 , Monterey, CA., UNITED STATES, DOI: 10.1109/RSP.2008.18, 2 au 5 juin 2008
 
137 Moreno E., Popovici K.M., Calazans N., Jerraya A. A., Integrating abstract NoC models within MPSoC design, Rapid System Prototyping Symposium (RSP’08), pp. 65-71, Monterey, CA, UNITED STATES, DOI: 10.1109/RSP.2008.29 , 2 au 5 juin 2008
 
138 Senouci B., Kouadri Mostéfaoui A., Rousseau F., Pétrot F., Multi-CPU/FPGA Platform Based Heterogeneous Multiprocessor prototyping: New Challenges for Embedded Software Designers , Rapid System Prototyping Symposium (RSP’08), pp. 41-47 , Monterey, CA., UNITED STATES, DOI: 10.1109/RSP.2008.27, 2 au 5 juin 2008
 
139 Demontes L., Bonaciu M., Amblard P., Software for Multi Processor System on Chip: moving from generic RISC platforms to CELL, Rapid System Prototyping Symposium (RSP’08), pp. 34-40, Monterey, Ca, UNITED STATES, DOI: 10.1109/RSP.2008.21, 2 au 5 juin 2008
 
140 Popovici K.M., Jerraya A. A., Multilevel Communication Modeling for Multiprocessor System-on-Chip, International Symposium on VLSI Design Automation and Test (VLSI-DAT’08), pp. 136-139, Hsinchu, TAIWAN, 23 au 25 avril 2008
 
141 Kouadri Mostéfaoui A., Senouci B., Pétrot F., Networks-In-Package: Performances management and design methodology, IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT’08), pp. 140-143, Hsinchu, TAIWAN, DOI: 10.1109/VDAT.2008.4542432 , 23 au 25 avril 2008
 
142 Guironnet de Massas P., Pétrot F., Comparison of memory write policies for NoC based Multicore Cache Coherent Systems, Proceedings of Design Automation and Test in Europe (DATE'08), pp. 997-1002, Munich, GERMANY, DOI: 10.1109/DATE.2008.4484811, 10 au 14 mars 2008
 
143 Gerin P., Guérin X., Pétrot F., Efficient implementation of native software simulation for MPSoC , Proceedings of Design Automation and Test in Europe (DATE'08), pp. 676-681, Munich, GERMANY, DOI: 10.1109/DATE.2008.4484756, 10 au 14 mars 2008
 
144 Shen H., Pétrot F., MPSoC Communication Architecture Exploration Using an Abstraction Refinement Method, 21st International Conference on VLSI Design, pp. 403-408, Hyderabad, INDIA, DOI: 10.1109/VLSI.2008.64, 4 au 8 janvier 2008
 
145 Dubois Ma., Aboulhamid E.M., Rousseau F., Accelerations for Heterogeneous Systems Cosimulation, International Conference on Electronics, Circuits and Systems (ICECS’07), pp. 294-297, Marrakech, MOROCCO, 11 au 14 décembre 2007
 
146 Shen H., Pétrot F., Service Dependency Graph for HW/SW Interfaces Modeling: The Motion-JPEG Case Study, 7th International Conference on ASIC (Asicon’07), pp. 930-933, Guilin, CHINA, DOI: 10.1109/ICASIC.2007.4415784, 26 au 29 octobre 2007
 
147 Kriaa L., Houari A., Gligor M., Bouchhima A., Pétrot F., Low Power oriented Hardware dependent Software Implementation in MPSoC Architectures, North-East Workshop on Circuirs and Systems (NEWCAS’07), pp. 49, Montreal, CANADA, 5 au 8 août 2007
 
148 Sahnine C., Zergainoh N.-E., Callonnec D., Pétrot F., Towards a High-Throughput and Low Power Reconfigurable Architecture of Advanced OFDM Modulator for Software-Defined Radio Systems, IEEE International Midwest Symposium on Circuits and Systems (MWSCAS’07), pp. 1205-1208, Montréal, CANADA, DOI: 10.1109/NEWCAS.2007.4488010, 5 au 8 août 2007
 
149 Guérin X., Popovici K.M., Youssef W., Rousseau F., Jerraya A. A., Flexible Application Software Generation for Heterogeneous Multi-Processor System-on-Chip, Computer Software and Application Conference (COMPSAC’07), pp. 279-286, Beijing, CHINA, DOI: http://doi.ieeecomputersociety.org/10.1109/COMPSAC.2007.117 , 23 au 27 juillet 2007
 
150 Kouadri Mostéfaoui A., Senouci B., Pétrot F., Scalable Multi-FPGA Platform for Networks-On-Chip Emulation, 18th International Conference Application-specific Systems, Architectures and Processors (ASAP’07), pp. 54-64, Montréal, Québec, CANADA, 9 au 11 juillet 2007
 
151 Huang K., Han Sang-Il, Popovici K.M., Brisolara L., Guérin X., Li L., Yan X., Chae Soo-Ik, Carro L., Jerraya A. A., Simulink-Based MPSoC Design Flow: Case Study of Motion-JPEG and H.264, 44th ACM/IEEE Design Automation Conference (DAC'07), pp. 39-42, San Diego, CA, UNITED STATES, DOI: 10.1109/DAC.2007.375049, 4 au 8 juin 2007
 
152 Popovici K.M., Guérin X., Rousseau F., Paolucci P.S., Jerraya A. A., Efficient software development platforms for multimedia applications at different abstraction levels , IEEE/IFIP International Workshop on Rapid System Prototyping (RSP’07), pp. 113-119, Porto Alegre, RS, BRAZIL, 28 au 30 mai 2007
 
153 Popovici K.M., Guérin X., Brisolara L., Jerraya A. A., Mixed hardware software multilevel modeling and simulation for multithreaded heterogeneous MPSoC, International Symposium on VLSI Design, Automation and Test (VLSI-DAT’07), pp. 79-82, Hsinchu, TAIWAN, 25 au 27 avril 2007
 
154 Atat Y., Zergainoh N.-E., Simulink-based MPSoC Design: New Approach to Bridge the Gap between Algorithm and Architecture Design, IEEE Computer Society Annual Symposium on VLSI (ISVLSI '07), pp. 9-14, Porto Alegre, BRAZIL, DOI: 10.1109/ISVLSI.2007.90, 9 au 11 mars 2007
 
155 Chureau A., Bouchhima A., Jerraya A. A., Gerin P., Shen H., Flexible and Executable Hardware/Software Interface Modeling for Multiprocessor SoC Design Using SystemC, 12th Asia and South Pacific Design Automation Conference (ASP-DAC'07), pp. 390-395, Yokohama, JAPAN, DOI: 10.1109/ASPDAC.2007.358017, 23 au 26 janvier 2007
 
156 Oyamada M., Wagner F.R., Bonaciu M., Cesario W., Jerraya A. A., Software Performance Estimation in MPSoC Design, 12th Asia and South Pacific Design Automation Conference (ASP-DAC’07), pp. 38-43, Yokohama, JAPAN, DOI: 10.1109/ASPDAC.2007.357789, 23 au 26 janvier 2007
 
157 Sahnine C., Zergainoh N.-E., Callonnec D., Pétrot F., Efficient Design Approach and Advanced Architectures for Universal OFDM Systems, PhD research in Microelectronics and Electronics (PRIME’07), pp. 33-36, Bordeaux, FRANCE, DOI: 10.1109/RME.2007.4401804, 1 janvier 2007
 
158 Lapalme J., Aboulhamid E.M., Nuta Nicolescu E.G., Rousseau F., Separating Modeling and Simulation Aspects in Hardware/Software System Design, International Conference on Microlectronics (ICM'06), pp. 202 - 205, Dhahran, SAUDI ARABIE, DOI: 10.1109/ICM.2006.373302, 16 au 19 décembre 2006
 
159 Dubois Ma., Rousseau F., Aboulhamid E.M., Acceleration for a Compiled Transaction Level Modeling Simulation, IEEE International Conference on Electronics, Circuits and Systems (ICECS 2006), pp. 1176-1179, Nice, FRANCE, DOI: 10.1109/ICECS.2006.379650, 10 au 13 décembre 2006
 
160 Dubois Ma., Rousseau F., Aboulhamid E.M., Towards an Efficient Simulation of Multi-Language Descriptions of Heterogeneous Systems, Asia Pacific Conference on Circuits and Systems (APCCAS’06), pp. 538-541, Singapour, SINGAPORE, DOI: 10.1109/APCCAS.2006.342527, 4 au 7 décembre 2006
 
161 Metzger M., Bastien F., Rousseau F., Vachon J., Aboulhamid E.M., Semi-formal verification tool implementation using introspection mechanisms in a System-Level Design environment, Forum on specification & Design Language (FDL’06), pp. 265-271, Darmstad, GERMANY, 19 au 22 septembre 2006
 
162 Pétrot F., Greiner A., Gomez P., On cache coherency and memory consistency issues in NoC based shared memory multiprocessor SoC architectures, 10th Euromicro conference on Digital System Design (DSD’06), pp. 53-60, Dubrovnik, CROATIA, DOI: 10.1109/DSD.2006.73, 30 août au 1 septembre 2006
 
163 Han Sang-Il, Guérin X., Chae Soo-Ik, Jerraya A. A., Buffer memory optimization for video codec application modeled in Simulink, 43rd Design Automation Conference (DAC'06), pp. 689-694, San Francisco, Ca, UNITED STATES, DOI: 10.1145/1146909.1147084, 24 au 28 juillet 2006
 
164 Jerraya A. A., Bouchhima A., Pétrot F., Programming models and HW-SW Interfaces Abstraction for Multi-Processor SoC, Design Automation Conference (DAC'06), pp. 280 - 285, San Francisco, CA, UNITED STATES, DOI: 10.1109/DAC.2006.229246, 24 au 28 juillet 2006
 
165 Greiner A., Pétrot F., Carrier M., Benabdenbi M., Chotin-Avot R., Labayrade R., MP-SoC Architecture for an Obstacle Detection Application in Pre-Crash Situation, 2nd International Workshop on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC'06), pp. 24-30, Montpellier, FRANCE, 1 juillet 2006
 
166 Guironnet de Massas P., Amblard P., Experiments around SPARC LEON-2 for MPEG encoding, International Conference Mixed Design of Integrated Circuits and Systems (MIXDES’06), pp. 285-289, Gdynia, POLAND, 22 au 24 juin 2006
 
167 Bouchhima A., Kriaa L., Chen X., Youssef W., Pétrot F., Jerraya A. A., A Unified HW/SW Interface Refinement Approach for MPSoC Design, 4th International IEEE North-East Workshop on Circuirs and Systems (NEWCAS’06), pp. 1-4, Gatineau, Québec, CANADA, 18 au 21 juin 2006
 
168 Brassard O., Rousseau F., David J.P., Kastle M., Aboulhamid E.M., Automatic generation of embedded systems with .NET framework based tools, IEEE 4th International NorthEast Workshop on Circuits and Systems (NEWCAS'06), pp. 165-168, Gatineau, Québec, CANADA, DOI: 10.1109/NEWCAS.2006.250904, 18 au 21 juin 2006
 
169 Senouci B., Bouchhima A., Rousseau T., Pétrot F., Jerraya A. A., Fast Prototyping of POSIX based applications on a Multiprocessor SoC Architecture: “Hardware-dependent Software oriented approach” , Seventeenth IEEE International Workshop on Rapid System Prototyping (RSP'06), pp. 69-75, Chania, GREECE, DOI: 10.1109/RSP.2006.17, 14 au 16 juin 2006
 
170 Metzger M., Bastien F., Rousseau F., Vachon J., Aboulhamid E.M., Introspection mechanisms for Semi-Formal Verification in a System-Level Design environment, IEEE Workshop on Rapid System Prototyping (RSP’06), pp. 91-97, Chania, GREECE, DOI: 10.1109/RSP.2006.22, 14 au 16 juin 2006
 
171 Kriaa L., Bouchhima A., Youssef W., Pétrot F., Fouillard A.-M., Jerraya A. A., Service Based Component Design Approach for Flexible Hardware/Software Interface Modeling, Seventeenth IEEE International Workshop on Rapid System Prototyping (RSP'06), pp. 156-162, Chania, Crete, GREECE, DOI: 10.1109/RSP.2006.35, 14 au 16 juin 2006
 
172 Greiner A., Pétrot F., Carrier M., Benabdenbi M., Chotin-Avot R., Labayrade R., Mapping an obstacles detection, stereo vision-based, software application on a multi-processor system-on-chip, IEEE Intelligent Vehicles Symposium, pp. 370-376, Tokyo, JAPAN, DOI: 10.1109/IVS.2006.1689656, 13 au 15 juin 2006
 
173 Tsikhanovich A., Rousseau F., Aboulhamid E.M., Bois G., Transaction Level Modeling in hardware/software system design using net framework, IEEE Canadian Conference on Electrical and Computer Engineering (CCECE'06), pp. 140-143, Ottawa, Ontario, CANADA, DOI: 10.1109/CCECE.2006.277692, 7 au 10 mai 2006
 
174 Kriaa L., De Moraes Sarmento A., Youssef W., Bouchhima A., Pétrot F., Jerraya A. A., Fouillard A.-M., Flexible hardware/software interface modeling using high level service based component model, The 13th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI'06), Nagoya, JAPAN, 3 au 4 avril 2006
 
175 Amblard P., Recognition and evaluation of Jevons' language by composing 2-state automata, ETAPS Workshop : Synchronous Language Applications Programming (SLAP'06), Vienna, AUSTRIA, 25 mars 2006
 
176 Dumitrascu F., Bacivarov I., Pieralisi L., Bonaciu M., Jerraya A. A., Flexible MPSoC platform with fast interconnect exploration for optimal system performance for a specific application, Design Automation and Test Conference in Europe (DATE'06), pp. 166 - 171, Munich, GERMANY, 6 au 10 mars 2006
 
177 Han Sang-Il, Chae Soo-Ik, Jerraya A. A., Functional modeling techniques for efficient SW code generation of video codec applications, 11th Asia and South Pacific Design Automation Conference (ASP-DAC'06), Yokohama, JAPAN, DOI: 10.1109/ASPDAC.2006.1594806, 24 au 27 janvier 2006
 
178 Bonaciu M., Bouchhima A., Youssef W., Chen X., Cesario W., Jerraya A. A., High-level architecture exploration for MPEG4 encoder with custom parameters, Asia and South Pacific Design Automation Conference (ASP-DAC'06), Yokohama, JAPAN, DOI: 10.1109/ASPDAC.2006.1594711, 24 au 27 janvier 2006
 
179 Kriaa L., Adriano S., Vaumorin E., Nouacer R., Blanc F., Pajaniradja S., Coussy P., Martin E., Heller D., Tabet F., SystemC'mantic1: A high level modeling and Co-design Framework for Reconfigurable Real Time Systems, Forum on specificiation and Design Languages (FDL'05), pp. 341-352, Lausanne, SWITZERLAND, 27 au 30 septembre 2005
 
180 Bouchhima A., Chen X., Pétrot F., Cesario W., Jerraya A. A., A Unified HW/SW Interface Model to Remove Discontinuities between HW and SW Design, 5th ACM international conference on Embedded software (EMSOFT'05), Jersey City NJ, UNITED STATES, DOI: 10.1145/1086228.1086258, 18 au 22 septembre 2005
 
181 De Moraes Sarmento A., Kriaa L., Grasset A., Youssef W., Bouchhima A., Rousseau F., Cesario W., Jerraya A. A., Service Dependency Graph, an Efficient Model for Hardware/Software Interfaces Modeling and Generation for SoC Design, International Conference on Hardware - Software Codesign and System Synthesis (CODES-ISSS'05), pp. 261 - 266, New York, UNITED STATES, 18 au 21 septembre 2005
 
182 Abril A., Mehrez H., Pétrot F., Gobert J., Miro C., Energy estimation and optimization in architectural descriptions of complex embedded systems, Microtechnologies for the New Millennium 2005 : VLSI Circuits and Systems, Sevilla, SPAIN, DOI: 10.1117/12.608256, 30 juin 2005
 
183 Petkov I., Amblard P., Hristov M., Jerraya A. A., Effective Hardware Verification of ARM Based System on Chip Design, 12th International Conference Mixed Design of Integrated Circuits and Systems (MIXDES'05), Krakow, POLAND, 22 au 25 juin 2005
 
184 Rousseau F., Sasongko A., Jerraya A. A., Shortening SoC Design Time with New Prototyping Flow on Reconfigurable Platform, International IEEE Northeast Workshop on Circuits and Systems Conference (NEWCAS'05) , pp. 207-210, Gatineau, Québec, CANADA, DOI: 10.1109/NEWCAS.2005.1496713, 19 au 22 juin 2005
 
185 Grasset A., Rousseau F., Jerraya A. A., Automatic generation of component wrappers by composition of hardware library elements starting from communication service specification, 16th International Workshop on Rapid System Prototyping (RSP'05), pp. 47-53, Montreal, CANADA, DOI: 10.1109/RSP.2005.16, 8 au 10 juin 2005
 
186 Lemaire R., Clermidy F., Durand Y., Lattard D., Jerraya A. A., Performance evaluation of a NoC-based design for MC-CDMA telecommunications using NS-2, 16th International Workshop on Rapid System Prototyping (RSP'05), pp. 24-30, Montreal, CANADA, DOI: 10.1109/RSP.2005.37, 8 au 10 juin 2005
 
187 Petkov I., Amblard P., Hristov M., Jerraya A. A., Systematic design flow for fast hardware/software prototype generation from bus functional model for MPSoC, 16th International Workshop on Rapid System Prototyping (RSP'05), pp. 218-224, Montréal, CANADA, DOI: 10.1109/RSP.2005.48, 8 au 10 juin 2005
 
188 Amblard P., The earliest formal language and its associated finite state evaluation automaton : Jevons' machine, 11th International conference Automata and Formal Languages (AFL'05), Dobogoko, HUNGARY, 17 au 20 mai 2005
 
189 Abril A., Mehrez H., Pétrot F., Gobert J., Miro C., Architectural Energy Estimation of Embedded Systems using Cycle Accurate Simulation, Microtechnologies for the New Millennium 2005 : VLSI Circuits and Systems II, Sevilla, SPAIN, 9 au 11 mai 2005
 
190 Pétrot F., Abril A., Mehrez H., Gobert J., Miro C., Energy Estimation and Optimisation of Embedded Systems using Cycle Accurate Simulation, Symposium on low power and high-speed chips (COOL Chips'05), pp. 195, Yokohama, JAPAN, 20 au 22 avril 2005
 
191 Amblard P., Using lustre in practical educational activities : digital circuits design, formal languages, ETAPS Workshop : Synchronous Language Applications Programming (SLAP'05), Edinburgh, SCOTLAND, UNITED KINGDOM, 3 avril 2005
 
192 Jerraya A. A., Long Term Trends for Embedded System Design, 12th Mixed Design of Integrated Circuits and Systems Conference (MIXDEX'05), Krakow, POLAND, 24 au 27 janvier 2005
 
193 Zergainoh N.-E., Popovici K.M., Jerraya A. A., Urard P., IP-block-based design environment for high-throughput VLSI dedicated digital signal processing systems, Asia and South Pacific Design Automation Conference (ASP-DAC'05), pp. 612-618, Shanghai, CHINA, 18 au 21 janvier 2005
 
194 Cho Y., Yoo S., Choi K., Zergainoh N.-E., Jerraya A. A., Scheduler implementation in MPSoC Design, Asia South Pacific Design Automation Conference (ASP-DAC'05), pp. 151-156, Shangai, CHINA, DOI: 10.1109/ASPDAC.2005.1466148 , 18 au 21 janvier 2005
 
195 Bouchhima A., Bacivarov I., Youssef W., Bonaciu M., Jerraya A. A., Using abstract CPU subsystem simulation model for high level HW/SW architecture exploration, Asia South Pacific Design Automation Conference (ASP-DAC'05), pp. 969-972, Shangai, CHINA, DOI: 10.1109/ASPDAC.2005.1466501, 18 au 21 janvier 2005
 
196 Bacivarov I., Jerraya A. A., Yoo S., A fast and accurate validation technique for operating system in multi-processor system-on-chip design, International Conference on Advanced Topics in Optoelectronics, Microelectronics, and Nanotechnologies (ATOM'04), pp. 342-348, Bucharest, ROMANIA, DOI: 10.1117/12.520078, 24 au 26 novembre 2004
 
197 Zergainoh N.-E., Jerraya A. A., Popovici K.M., Urard P., Matlab based environment for designing DSP systems using IP blocks, The 12th Workshop on Synthesis and System Integration of Mixed Information technologies (SASIMI'04), pp. 296 - 302, Kanazawa, JAPAN, 18 au 19 octobre 2004
 
198 Jerraya A. A., Long term trends for embedded system design, Euromicro Symposium on Digital System Design (DSD'04), pp. 20-26, Rennes, FRANCE, DOI: 10.1109/DSD.2004.62, 31 août au 3 septembre 2004
 
199 Amblard P., Proving good synchronization between Finite State Machines : a case study, EUROMICRO Symposium on Digital System Design (DSD'04), Rennes, FRANCE, 31 août au 3 septembre 2004
 
200 Gharsalli F., Baghdadi A., Bonaciu M., Majauskas G., Cesario W., Jerraya A. A., An efficient architecture for the implementation of message passing programming model on massive multiprocessor, 15th IEEE International Workshop on Rapid System Prototyping (RSP'04), pp. 80-87, Geneva, SWITZERLAND, DOI: 10.1109/IWRSP.2004.1311100, 28 au 30 juin 2004
 
201 De Moraes Sarmento A., Cesario W., Jerraya A. A., Automatic building of executable models from abstract SoC architectures made of heterogeneous subsystems, 15th IEEE International Workshop on Rapid System Prototyping (RSP'04), pp. 88-95, Geneva, SWITZERLAND, DOI: 10.1109/IWRSP.2004.1311101, 28 au 30 juin 2004
 
202 Grasset A., Rousseau F., Jerraya A. A., Network interface generation for MPSOC: from communication service requirements to RTL implementation, 15th IEEE International Workshop on Rapid System Prototyping (RSP'04), pp. 66-69, Geneva, SWITZERLAND, DOI: 10.1109/RSP.2004.32, 28 au 30 juin 2004
 
203 Amblard P., Lagnier F., Levy M., Introduction to formal processor verification at logic level : a case study, Workshop on Computer Architecture Education (WCAE'04), pp. 42- 47, Munich, GERMANY, 19 au 23 juin 2004
 
204 Han Sang-Il, Baghdadi A., Bonaciu M., Chae Soo-Ik, Jerraya A. A., An efficient scalable and flexible data transfer architecture for multiprocessor SoC with massive distributed memory, Design Automation Conference (DAC'04), pp. 250-255, San Diego, CA, UNITED STATES, DOI: 10.1145/996566.996636, 7 au 11 juin 2004
 
205 Youssef W., Yoo S., Sasongko A., Paviot Y., Jerraya A. A., Debugging HW/SW interface for MPSoC: video encoder system design case study, Design Automation Conference (DAC'04), pp. 908-913, San Diego, CA, UNITED STATES, DOI: 10.1145/996566.996808, 7 au 11 juin 2004
 
206 Dziri A., Cesario W., Wagner F.R., Jerraya A. A., Unified component integration flow for multi-processor SoC design and validation, Design, Automation and Test in Europe Conference and Exhibition (DATE'04), pp. 1132-1137 , Paris, FRANCE, 29 mars au 2 avril 2004
 
207 Yoo S., Youssef W., Bouchhima A., Jerraya A. A., Multi-processor SoC design methodology using a concept of two-layer hardware-dependent software, Design, Automation and Test in Europe Conference and Exhibition (DATE'04), pp. 1382-1383, Paris, FRANCE, DOI: 10.1109/DATE.2004.1269098, 16 au 20 février 2004
 
208 Jerraya A. A., EuroSoC: towards a joint university/industry research infrastructure for system on chip and system in package, Asia and South Pacific Design Automation Conference (ASP-DAC'04) , pp. 18, Yokohama, JAPAN, DOI: 10.1109/ASP-DAC.2004.96, 27 au 30 janvier 2004
 
209 Bouchhima A., Yoo S., Jerraya A. A., Fast and accurate timed execution of high level embedded software using HW/SW interface simulation model, IEEE Asia and South Pacific Design Automation Conference (ASP-DAC'04) , pp. 469-474, Yokohama, JAPAN, DOI: 10.1109/ASPDAC.2004.1337621, 27 au 30 janvier 2004
 
210 Petkov I., Jerraya A. A., Automatic generation of HW-SW interfaces for MPSOC, 12th International Scientific and Applied Science Conference Electronics (ET'03), pp. 201-206, Sozopol, BULGARIA, 24 au 27 septembre 2003
 
211 Petkov I., Amblard P., Hristov M., Jerraya A. A., Physical design of HW interfaces for MPSoC, 7th International Symposium on Microelectronics Technologies and Microsystems in cooperation with 12th International Scientific and Applied Science Conference ELECTRONICS 2003, pp. 230-235, Sofia-Sozopol, BULGARIA, 1 septembre 2003
 
212 Amblard P., Lagnier F., Levy M., Finite state machines: composition, verification, minimization: a case study, 10th International Conference Mixed Design of Integrated Circuits and Systems (MIXDES'03), pp. 214-219, Lodz, POLAND, 26 au 28 juin 2003
 
213 Tambour L., Zergainoh N.-E., Urard P., Michel H., Jerraya A. A., An efficient methodology and semi automated flow for design and validation of complex digital signal processing ASICS macro cells, 14th IEEE International Workshop on Rapid Systems Prototyping (RSP'03), pp. 56-63, San Diego, California, UNITED STATES, DOI: 10.1109/IWRSP.2003.1207030, 9 au 11 juin 2003
 
214 Baghdadi A., Sasongko A., Rousseau F., Jerraya A. A., Embedded application prototyping on a communication-restricted reconfigurable platform, 14th IEEE International Workshop on Rapid System Prototyping (RSP'03), pp. 33-39, San Diego, CA, UNITED STATES, DOI: 10.1109/IWRSP.2003.1207027, 9 au 11 juin 2003
 
215 Hunsinger F., François S., Jerraya A. A., Definition of a systematic method for the generation of software test programs allowing the functional verification of system on chip (SoC), 4th International Workshop on Microprocessor Test and Verification Common Challenges and Solutions (MTV'03), pp. 11-16, Austin, TX, UNITED STATES, DOI: 10.1109/MTV.2003.1250257, 29 au 30 mai 2003
 
216 Yoo S., Bacivarov I., Bouchhima A., Paviot Y., Jerraya A. A., Building fast and accurate SW simulation models based on hardware abstraction layer and simulation environment abstraction layer, Design, Automation and Test in Europe Conference and Exhibition (DATE'03), pp. 550-555, Munich, GERMANY, DOI: 10.1109/DATE.2003.10103, 3 au 7 mars 2003
 
217 Yoo S., Jerraya A. A., Introduction to hardware abstraction layers for SoC, Design, Automation and Test in Europe (DATE'03), pp. 336-337, Munich, GERMANY, DOI: 10.1109/DATE.2003.1253629, 3 au 7 mars 2003
 
218 Cho Y., Choi K., Zergainoh N.-E., Lee G., Yoo S., Scheduling and timing analysis of HW/SW on-chip communication in MP SoC design, Design, Automation and Test in Europe (DATE'03), Munich, GERMANY, 3 au 7 mars 2003
 
219 Dziri A., Samet F., Wagner F.R., Cesario W., Jerraya A. A., Combining architecture exploration and a path to implementation to build a complete SoC design flow from system specification to RTL, Asia and South Pacific Design Automation Conference (ASP-DAC'03) , pp. 219-224, Kitakyushu, JAPAN, DOI: 10.1109/ASPDAC.2003.1195020, 21 au 24 janvier 2003
 
220 Bacivarov I., Yoo S., Jerraya A. A., Timed HW-SW cosimulation using native execution of OS and application SW, Seventh IEEE International High Level Design Validation and Test Workshop (HLDVT'02), pp. 51-56, Cannes, FRANCE, DOI: 10.1109/HLDVT.2002.1224428, 27 au 29 octobre 2002
 
221 Gharsalli F., Lyonnard D., Rousseau F., Jerraya A. A., Unifying memory and processor wrapper architecture in multiprocessor SoC design, 15th International Symposium on System Synthesis (ISSS'02), pp. 26-31, Kyoto, JAPAN, DOI: 10.1109/ISSS.2002.1227147, 2 au 4 octobre 2002
 
222 Nuta Nicolescu E.G., Yoo S., Bouchhima A., Jerraya A. A., Validation in a component-based design flow for multicore SoCs, 15th International Symposium on System Synthesis (ISSS'02), pp. 162-167, Kyoto, JAPAN, DOI: 10.1145/581199.581236, 2 au 4 octobre 2002
 
223 Amblard P., Lagnier F., Levy M., Using formal tools to study complex circuits behaviour, Euromicro Symposium on Digital System Design (DSD'02), pp. 180-186, Dortmund, GERMANY, DOI: 10.1109/DSD.2002.1115367, 4 au 6 septembre 2002
 
224 Gharsalli F., Meftali S., Rousseau F., Jerraya A. A., Automatic generation of embedded memory wrapper for multiprocessor SoC, Design Automation Conference (DAC'02), pp. 596-601, New Orleans, UNITED STATES, DOI: 10.1109/DAC.2002.1012695, 10 au 14 juin 2002
 
225 Cesario W., Baghdadi A., Gauthier L., Lyonnard D., Nuta Nicolescu E.G., Paviot Y., Yoo S., Jerraya A. A., Diaz-Nava M., Component-based design approach for multicore SoCs, Design Automation Conference (DAC'02), pp. 789-794, New Orleans, LA, UNITED STATES, DOI: 10.1109/DAC.2002.1012730, 10 au 14 juin 2002
 
226 Kriaa L., Youssef W., Nuta Nicolescu E.G., Martinez S., Levitan S.P., Martinez J., Kurzweg T., Jerraya A. A., Courtois B., SystemC-based cosimulation for global validation of MOEMS, Design, Test, Integration and Packaging of MEMS/MOEMS (DTIP'02), pp. 64-70, Cannes, FRANCE, 6 au 8 mai 2002
 
227 Yoo S., Nuta Nicolescu E.G., Gauthier L., Jerraya A. A., Automatic generation of fast timed simulation models for operating systems in SoC design, Design, Automation and Test in Europe Conference and Exhibition (DATE'02), pp. 620-627, Paris, FRANCE, DOI: 10.1109/DATE.2002.998365 , 4 au 8 mars 2002
 
228 Cesario W., Baghdadi A., Lyonnard D., Yoo S., Bianchi R.A., Paviot Y., Gauthier L., Nuta Nicolescu E.G., Jerraya A. A., HW/SW interfaces design of a VDSL modem using automatic refinement of a virtual architecture specification into a multiprocessor SoC: a case study, Design, Automation and Test in Europe (DATE'02), Paris, FRANCE, 4 au 8 mars 2002
 
229 Nuta Nicolescu E.G., Martinez S., Kriaa L., Youssef W., Yoo S., Charlot B., Jerraya A. A., Application of multi-domain and multi-language cosimulation to an optical MEM switch design, 7th Asia and South Pacific Design Automation Conference and 15h International Conference on VLSI Design (ASP-DAC'02), pp. 426-431, Bangalore, INDIA, DOI: 10.1109/ASPDAC.2002.994958, 7 au 11 janvier 2002
 
230 Gharsalli F., Jerraya A. A., Meftali S., Rousseau F., Automatic code-transformations and architecture refinement, for application-specific, IFIP International Conference on Very Large Scale Integration - The Global System on Chip Design & CAD Conference (VLSI-SOC'01), Montpellier, FRANCE, 3 au 5 décembre 2001
 
231 Yoo S., Nuta Nicolescu E.G., Gauthier L., Jerraya A. A., Fast timed cosimulation of HW/SW implementation of embedded multiprocessor SoC communication, Sixth IEEE International High Level Design Validation and Test Workshop (HLDVT'01), pp. 79-82, Monterey, CA, UNITED STATES, DOI: 10.1109/HLDVT.2001.972811, 9 novembre 2001
 
232 Juneidi Z., Torki K., Martinez S., Nuta Nicolescu E.G., Courtois B., Jerraya A. A., Global modeling and simulation of System-on-Chip embedding MEMS devices, 4th International Conference on ASIC (ASICON'01), pp. 666-669, Shanghai, CHINA, DOI: 10.1109/ICASIC.2001.982651, 23 au 25 octobre 2001
 
233 Baghdadi A., Gauthier L., Nuta Nicolescu E.G., Yoo S., Jerraya A. A., Cesario W., Lyonnard D., Paviot Y., Application-specific multiprocessor systems-on-chip, The Tenth Workshop on Synthesis And System Integration of Mixed Technologies (SASIMI'01), Nara, JAPAN, 18 au 19 octobre 2001
 
234 Gauthier L., Jerraya A. A., Yoo S., Application-specific operating systems generation and targeting for embedded SoCs, The Tenth Workshop on Synthesis And System Integration of MIxed Technologies (SASIMI'01), Nara, JAPAN, 18 au 19 octobre 2001
 
235 Rousseau F., Nicolau A., Mishra P., Dutt N., Architecture description language driven design space exploration in the presence of coprocessors, The Tenth Workshop on Synthesis And System Integration of MIxed Technologies (SASIMI'01), Nara, JAPAN, 18 au 19 octobre 2001
 
236 Baghdadi A., Zergainoh N.-E., Lyonnard D., Jerraya A. A., Generic architecture platform for multiprocessor system-on-chip design, International Workshop on Distributed and Parallel Embedded Systems (DIPES'00), pp. 53-63, Paderborn, GERMANY, 1 octobre 2001
 
237 Meftali S., Gharsalli F., Rousseau F., Jerraya A. A., An optimal memory allocation for application-specific multiprocessor system-on-chip, International Symposium on System Synthesis (ISSS'01), pp. 19-24, Montreal, CANADA, DOI: 10.1145/500001.500006, 30 septembre au 3 octobre 2001
 
238 Cesario W., Nuta Nicolescu E.G., Gauthier L., Lyonnard D., Jerraya A. A., Colif: A multilevel design representation for application-specific multiprocessor system-on-chip design, 12th International Workshop on Rapid System Prototyping (RSP'01), pp. 110-115, Monterey, CA, UNITED STATES, DOI: 10.1109/IWRSP.2001.933847, 25 au 27 juin 2001
 
239 Lyonnard D., Yoo S., Baghdadi A., Jerraya A. A., Automatic generation of application-specific architectures for heterogeneous multiprocessor system-on-chip, 38th Design Automation Conference (DAC'01), pp. 518-523, Las Vegas, Nevada, UNITED STATES, DOI: 10.1109/DAC.2001.156194, 18 au 22 juin 2001
 
240 Yoo S., Nuta Nicolescu E.G., Lyonnard D., Baghdadi A., Jerraya A. A., A generic wrapper architecture for multi-processor SoC cosimulation and design, Ninth International Symposium on Hardware/Software Codesign (CODES'01), pp. 195-200, Copenhagen, DENMARK, DOI: 10.1145/371636.371722, 1 avril 2001
 
241 Svarstad K., Nuta Nicolescu E.G., Jerraya A. A., A model for describing communication between aggregate objects in the specification and design of embedded systems, Design, Automation and Test in Europe. Conference and Exhibition (DATE'01), pp. 77-84, Munich, GERMANY, DOI: 10.1109/DATE.2001.915004, 13 au 16 mars 2001
 
242 Baghdadi A., Lyonnard D., Zergainoh N.-E., Jerraya A. A., An efficient architecture model for systematic design of application-specific multiprocessor SoC, Design, Automation and Test in Europe Conference (DATE'01), pp. 55-62, Munich, GERMANY, DOI: 10.1109/DATE.2001.915001, 13 au 16 mars 2001
 
243 Gauthier L., Yoo S., Jerraya A. A., Automatic generation and targeting of application specific operating systems and embedded systems software, Design, Automation and Test in Europe. Conference and Exhibition (DATE'01), pp. 679-685, Munich, GERMANY, DOI: 10.1109/DATE.2001.915098, 13 au 16 mars 2001
 
244 Matheron G., Jerraya A. A., Electronic system design methodology: Europe's positioning, Design, Automation and Test in Europe. Conference and Exhibition (DATE'01), pp. 720, Munich, GERMANY, DOI: 10.1109/DATE.2001.10012, 13 au 16 mars 2001
 
245 Nuta Nicolescu E.G., Yoo S., Jerraya A. A., Mixed-level cosimulation for fine gradual refinement of communication in SoC design, Design, Automation and Test in Europe. Conference and Exhibition (DATE'01), pp. 754-759, Munich, GERMANY, DOI: 10.1109/DATE.2001.915113, 13 au 16 mars 2001
 
246 Svarstad K., Ben-Fredj N., Nuta Nicolescu E.G., Jerraya A. A., A higher level system communication model for object-oriented specification and design of embedded systems, Asia and South Pacific Design Automation Conference (ASP-DAC'01), pp. 69-77, Yokohama, JAPAN, DOI: 10.1109/ASPDAC.2001.913283, 30 janvier au 2 février 2001
 
247 Gerin P., Yoo S., Nuta Nicolescu E.G., Jerraya A. A., Scalable and flexible cosimulation of SoC designs with heterogeneous multi-processor target architectures, Asia and South Pacific Design Automation Conference (ASP-DAC'01), pp. 63-68, Yokohama, JAPAN, DOI: 10.1109/ASPDAC.2001.913282, 30 janvier au 2 février 2001
 
248 Cesario W., Gauthier L., Lyonnard D., Nuta Nicolescu E.G., Jerraya A. A., An XML-based meta-model for the design of multiprocessor embedded systems, VHDL International Users Forum Fall Workshop (VIUF'00), pp. 75-82, Orlando, FL, UNITED STATES, DOI: 10.1109/VIUF.2000.890272, 18 au 20 octobre 2000
 
249 Gauthier L., Jerraya A. A., Software & RTOS targeting for multiprocessor architectures, MEDEA Conference on Embedded System Design, Munich, GERMANY, 11 au 13 octobre 2000
 
250 Ouni R., Soudani A., Nasri S., Abid M., Torki K., Tourki R., Interoperability of ATM-Ethernet interworking system: design and congestion control, 1st European Conference on Universal Multiservice Networks (ECUMN'00), Colmar, FRANCE, DOI: 10.1109/ECUMN.2000.880729, 2 au 4 octobre 2000
 
251 Baghdadi A., Zergainoh N.-E., Lyonnard D., Jerraya A. A., Generic architecture platform for multiprocessor embedded system-on-chip design, International Workshop on Distributed and Parallel Embedded Systems (DIPES'00), pp. 53-64, Paderborn, GERMANY, 1 octobre 2000
 
252 Cesario W., Sugar Z., Moussa I., Jerraya A. A., Efficient integration of behavioral synthesis within existing design flows, 13th International Symposium on System Synthesis (ISSS'00), pp. 85-90, Madrid, SPAIN, DOI: 10.1109/ISSS.2000.874033, 20 au 22 septembre 2000
 
253 Hessel F., Coste P., Nuta Nicolescu E.G., Le Marrec Ph., Zergainoh N.-E., Jerraya A. A., Multi-level communication synthesis of heterogeneous multilanguage specification, International Conference on Computer Design (ICCD'00), pp. 525-530, Austin, Texas, UNITED STATES, DOI: 10.1109/ICCD.2000.878332, 17 au 20 septembre 2000
 
254 Hessel F., Coste P., Nuta Nicolescu E.G., Le Marrec Ph., Zergainoh N.-E., Jerraya A. A., Multi-level communication synthesis of heterogeneous multilanguage specifications, International Conference on Computer Design (ICCD'00), Austin, Texas, UNITED STATES, 17 au 20 septembre 2000
 
255 Cesario W., Jerraya A. A., Sugar Z., Moussa I., Rethinking behavioral synthesis for a better integration within existing design flows, International Conference on Computer Design (ICCD'00), pp. 513-518, Austin, TX, UNITED STATES, DOI: 10.1109/ICCD.2000.878330, 17 au 20 septembre 2000
 
256 Gauthier L., Jerraya A. A., Cycle-true simulation of the ST10 microcontroller including the core and the peripherals, 11th International Workshop on Rapid System Prototyping (RSP'00) Shortening the Path from Specification to Prototype, pp. 60-65, Paris, FRANCE, DOI: 10.1109/IWRSP.2000.855195, 21 au 23 juin 2000
 
257 Baghdadi A., Zergainoh N.-E., Cesario W., Roudier T., Jerraya A. A., Design space exploration for hardware/software codesign of multiprocessor systems, 11th International Workshop on Rapid System Prototyping (RSP'00), pp. 8-13, Paris, FRANCE, DOI: 10.1109/IWRSP.2000.854975, 21 au 23 juin 2000
 
258 Amblard P., Lagnier F., Levy M., Introducing digital circuits design and formal verification concurrently, European Workshop on Microelectonics Education (EWME'00), Aix-en-Provence, FRANCE, 18 au 19 mai 2000
 
259 Nuta Nicolescu E.G., Coste P., Hessel F., Le Marrec Ph., Jerraya A. A., Multilanguage design of a robot arm controller: Case study, IEEE Computer Society Workshop on VLSI 2000. System Design for a System on Chip Era, pp. 29-34, Orlando, Florida, UNITED STATES, DOI: 10.1109/IWV.2000.844526, 27 au 28 avril 2000
 
260 Coste P., Hessel F., Jerraya A. A., Multilanguage codesign using SDL and matlab, SASIMI 2000, Kyoto, JAPAN, 1 avril 2000
 
261 Gauthier L., Jerraya A. A., Cycle-true simulation of the ST10 microcontroller, Design, Automation and Test in Europe (DATE'00), pp. 742, Paris, FRANCE, DOI: 10.1109/DATE.2000.840875, 27 au 30 mars 2000
 
262 Mir S., Charlot B., Nuta Nicolescu E.G., Coste P., Parrain F., Zergainoh N.-E., Courtois B., Jerraya A. A., Rencz M., Towards design and validation of mixed-technology SOCs, Great Lakes Symposium on VLSI , pp. 29 - 33, Chicago, Illinois, UNITED STATES, DOI: 10.1145/330855.330950, 2 au 4 mars 2000
 
263 Ernst R., Jerraya A. A., Embedded system design with multiple languages, Asia and South Pacific Design Automation Conference (ASP-DAC'00) with EDA TechnoFair 2000, pp. 391-396, Yokohama, JAPAN, DOI: 10.1145/368434.368701, 25 au 28 janvier 2000
 
264 Zergainoh N.-E., Baghdadi A., Tambour L., Lyonnard D., Gauthier L., Jerraya A. A., Framework for system design, validation and fast prototyping of multiprocessor system-on-chip: applied to telecommunication systems, International Workshop on Distributed and Parallel Embedded Systems (DIPES'00), Paderborn, GERMANY, 18 au 19 janvier 2000
 
265 Hessel F., Le Marrec Ph., Valderrama C., Romdhani A., Jerraya A. A., MCI - multilanguage distributed co-simulation tool, International Workshop on Distributed and Parallel Embedded Systems (DIPES'99), pp. 191-200, Schloß Eringerfeld, GERMANY, 5 au 6 octobre 1999
 
266 Moussa I., Sugar Z., Suescun R., Diaz-Nava M., Pavesi M., Crudo S., Gazzi L., Jerraya A. A., Comparing RTL and behavioral design methodologies in the case of a 2M-transistor ATM shaper, Design Automation Conference (DAC'99), pp. 598-603, San Francisco, Ca, UNITED STATES, DOI: 10.1145/309847.310006, 26 au 31 juillet 1999
 
267 Hessel F., Coste P., Le Marrec Ph., Zergainoh N.-E., Daveau J.- M., Jerraya A. A., Communication interface synthesis for multilanguage specifications, IEEE International Workshop on Rapid System Prototyping (RSP'99), pp. 15-20, Clearwater, Florida , UNITED STATES, DOI: 10.1109/IWRSP.1999.779025, 16 au 18 juin 1999
 
268 Jerraya A. A., Ernst R., Multi-language system design, Design, Automation and Test in Europe (DATE '99), pp. 696-699, Munich, GERMANY, DOI: 10.1109/DATE.1999.761205, 9 au 12 mars 1999
 
269 Cesario W., Sugar Z., Suescun R., Jerraya A. A., Overlap and frontiers between behavioral and RTL synthesis, Conference and Exhibition on Design, Automation and Test in Europe (DATE'99), Munich, GERMANY, 9 au 12 mars 1999
 
270 Coste P., Hessel F., Le Marrec Ph., Sugar Z., Romdhani A., Suescun R., Zergainoh N.-E., Jerraya A. A., Multilanguage design of heterogeneous systems, Seventh International Workshop on Hardware/Software Codesign (CODES'99), pp. 54-58, Rome, ITALY, DOI: 10.1145/301177.301206, 3 mars 1999
 
271 Zitouni A., Abid M., Torki K., Souani C., Tourki R., Communication synthesis approach for distributed systems and its application during the design of a communication controller, Tenth International Conference on Microelectronics, Monastir, TUNISIA, DOI: 10.1109/ICM.1998.825611, 14 au 16 décembre 1998
 
272 Souani C., Abid M., Torki K., Tourki R., The design of MAC unit for DWT implementation, Tenth International Conference on Microelectronics (ICM'98), Monastir, TUNISIA, DOI: 10.1109/ICM.1998.825607, 14 au 16 décembre 1998
 
273 Voros N.S., Tsasakou S., Valderrama C., Arab M.- S., Birbas A.N, Birbas M., Mariatos V., Andritsou A., Hardware/software co-design of embedded systems using multiple formalisms for application development, IFIP International Conference FORTE/PSTV'98, Formal description Techniques & Protocol Specification, Testing and Verification, Paris, FRANCE, 3 au 6 novembre 1998
 
274 Marchioro G.F., Moreira P., Noah E., Snoeys W., Calin T., Cosculluela J., Velazco R., Nicolaidis M., Giraldo A., Faccio F., Anelli G., Campbell M., Delmastro M., Jarron P., Kouklinas K., Total dose and Single Event Effects (SEE) in a 0.25 µm CMOS technology, Fourth Workshop on electronics for LHC experiments (LEB'98), Roma, ITALY, 21 au 25 septembre 1998
 
275 Moussa I., Diaz-Nava M., Jerraya A. A., Cost evaluation in the design for reuse context, 2nd GI/ITG/GMM-Workshop, Reuse Techniques for VLSI Design, Karlsrube, GERMANY, 14 septembre 1998
 
276 Dusina J., Borrione D., Jerraya A. A., Formal Verification of the Allocation Step in High Level Synthesis, Forum on Design Languages (FDL'98), Lausanne, SWITZERLAND, 6 au 11 septembre 1998
 
277 Voros N.S., Karathanasis H., Valderrama C., Arab M.- S., Birbas A.N, Birbas M., Tsasakou S., A hardware/software co-design methodology for embedded telecommunication systems, Conference on European Multimedia, Microprocessor Systems and Electronic Commerce (EMMSEC'98), Bordeaux, FRANCE, 1 septembre 1998
 
278 Rawski M., Tomaszewicz P., Amblard P., Comparison of different decomposition techniques of a digital circuit - A case study, 5th International Conference MIXDES 98, Lodz, POLAND, 18 au 20 juin 1998
 
279 Le Marrec Ph., Valderrama C., Hessel F., Jerraya A. A., Attia M., Cayrol O., Hardware, software and mechanical cosimulation for automotive applications, Ninth International Workshop on Rapid System Prototyping (RSP'98), pp. 202-206, Leuven, BELGIUM, DOI: 10.1109/IWRSP.1998.676692, 3 au 5 juin 1998
 
280 Daveau J.- M., Marchioro G.F., Jerraya A. A., Hardware/software co-design of an ATM network interface card: a case study, 6th International Workshop on Hardware/Software Codesign (CODES/CASHE'98), pp. 111-115, Seattle, WA, UNITED STATES, DOI: 10.1109/HSC.1998.666247, 15 au 18 mars 1998
 
281 Jemai A., Kission P., Jerraya A. A., Architectural simulation in the context of behavioral synthesis, Design, Automation and Test in Europe Conference and Exhibition (DATE'98), pp. 590-595, Paris, FRANCE, DOI: 10.1109/DATE.1998.655918, 23 au 26 février 1998
 
282 Valderrama C., Liabeuf C., Nacabal F., Paulin P., Jerraya A. A., Automatic generation of VHDL-C interfaces for distributed cosimulation, SASIMI Workshop, Osaka, JAPAN, 1 au 2 décembre 1997
 
283 Cesario W., Kission P., Guillaume Ph., Jerraya A. A., Unified evaluation model for interconnection schemes used in behavioral synthesis, International Workshop on Logic and Architecture Synthesis (IWLAS'97), Grenoble, FRANCE, 1 décembre 1997
 
284 Marchioro G.F., Daveau J.- M., Jerraya A. A., Transformational partitioning for co-design of multiprocessor systems, IEEE/ACM International Conference on Computer Aided Design. Digest of Technical , pp. 508-515, San Jose, CA, UNITED STATES, DOI: 10.1109/ICCAD.1997.643585, 9 au 13 novembre 1997
 
285 Valderrama C., Le Marrec Ph., Jerraya A. A., VCI : a VHDL-C interface generation tool for cosimulation, IEEE Second International High Level Design Validation and Test Workshop (HLDTV'97), Oakland, CA, UNITED STATES, 1 novembre 1997
 
286 Wang J.C., Teruya M.Y., Neto J.V.V., Strum M., Jerraya A. A., A recursive high level synthesis system, 5th International Conference on VLSI and CAD (ICVC'97), pp. 412-414, Seoul, KOREA, 13 au 15 octobre 1997
 
287 Abou-Samra S.-J., Laurent B., Guyot A., Spurious transitions in adder circuits: analytical modelling and simulation, International Conference on Very Large Scale Integration (VLSI'97), Gramado, RS, BRAZIL, 1 août 1997
 
288 Liem Cl. B., Cornero M., Santana M., Paulin P., Jerraya A. A., Gentit J.M, Lopez J., Figari X., Bergher L., An embedded system case study: the firmware development environment for a multimedia audio processor, 34th Annual Design Automation Conference (DAC'97), pp. 780 - 785, Anaheim, California, UNITED STATES, DOI: 10.1145/266021.266373, 9 au 13 juin 1997
 
289 Daveau J.- M., Marchioro G.F., Valderrama C., Jerraya A. A., VHDL generation from SDL specification, XIII IFIP WG 10.5 Conference on Computer Hardware Description Languages and Their Applications (CHDL'97), Toledo, SPAIN, 20 au 25 avril 1997
 
290 Daveau J.- M., Marchioro G.F., Valderrama C., Jerraya A. A., VHDL generation from SDL specifications, IFIP TC10 WG10.5 International Conference on Computer Hardware Description Languages and their Applications (CHDL'97), pp. 182-201, Toledo, SPAIN, 20 au 25 avril 1997
 
291 Kission P., Jerraya A. A., Moussa I., Hardware reuse, 2nd Workshop on Libraries, Component Modeling & Quality Assurance, Toledo, SPAIN, 1 avril 1997
 
292 Liem Cl. B., Paulin P., Jerraya A. A., ReCode: the design and re-design of the instruction codes for embedded instruction-set processors, European Design and Test Conference (EDTC'97), pp. 612, Paris, FRANCE, DOI: 10.1109/EDTC.1997.582426, 17 au 20 mars 1997
 
293 Jemai A., Kission P., Jerraya A. A., Embedded architectural simulation within behavioral synthesis environment, Asia and South Pacific Design Automation Conference (ASP-DAC'97) , pp. 227-232, Chiba , JAPAN, DOI: 10.1109/ASPDAC.1997.600127, 28 au 31 janvier 1997
 
294 Pistorius R., P. Vijayaraghavan V., Kission P., Jerraya A. A., Personalization of the architecture produced by High Level Synthesis for the RT Level, International Workshop on Logic and Architecture Synthesis (IWLAS'96), Grenoble, FRANCE, 16 au 18 décembre 1996
 
295 Dusina J., Borrione D., Jerraya A. A., Correct reuse of complex design units during high level synthesis: verification issues, 1st IEEE International High Level Design Validation and Test Workshop (HLDVT'96), Oakland, Ca., UNITED STATES, 8 au 10 novembre 1996
 
296 Pirmez L., Pedroza A., Rahmouni M., Mesquita A., Kission P., Jerraya A. A., Analysis of different protocol description styles in VHDL for high-level synthesis, European Design Automation Conference (EURO DAC'96) with EURO VHDL'96 and Exhibition, pp. 490-495, Geneva, SWITZERLAND, DOI: 10.1109/EURDAC.1996.558248, 16 au 20 septembre 1996
 
297 Changuel A., Rolland R., Jerraya A. A., Design of an adaptive motors controller based on fuzzy logic using behavioural synthesis, European Design Automation Conference (EURO DAC'96) with EURO VHDL '96 and Exhibition , pp. 48-52, Geneva, SWITZERLAND, DOI: 10.1109/EURDAC.1996.558074, 16 au 20 septembre 1996
 
298 Abid M., Changuel A., Jerraya A. A., Exploration of hardware/software design space through a codesign of robot arm controller, European Design Automation Conference (EURO-DAC'96) with EURO-VHDL '96, pp. 42-47, Geneva, SWITZERLAND, DOI: 10.1109/EURDAC.1996.558055, 16 au 20 septembre 1996
 
299 Valderrama C., Nacabal F., Paulin P., Jerraya A. A., Automatic generation of interfaces for distributed C-VHDL cosimulation of embedded systems: an industrial experience, Seventh IEEE International Workshop on Rapid System Prototyping (IWRSP'96), pp. 72-77, Thessaloniki, GREECE, DOI: 10.1109/IWRSP.1996.506730, 19 au 21 juin 1996
 
300 Liem Cl. B., Paulin P., Jerraya A. A., Address calculation for retargetable compilation and exploration of instruction-set architectures, 33rd Annual Design Automation Conference (DAC'96), pp. 597-600, Las Vegas, Nevada, UNITED STATES, DOI: 10.1145/240518.240631, 14 au 16 juin 1996
 
301 Berrebi E., Kission P., Vernalde S., De-Troch S., Herluison J.C., Frehel J., Jerraya A. A., Bolsens I., Combined control flow dominated and data flow dominated high-level synthesis, 33rd Design Automation Conference (DAC'96), pp. 573 - 578, Las Vegas, Nevada, UNITED STATES, DOI: 10.1145/240518.240627, 3 au 7 juin 1996
 
302 Abid M., Changuel A., Jerraya A. A., A hardware/software codesign case study: design of a robot arm controller, European Design and Test Conference (ED&TC '96), pp. 599, Paris, FRANCE, DOI: 10.1109/EDTC.1996.494363, 11 au 14 mars 1996
 
303 Borrione D., Bouamama H., Suescun R., Validation of the Numeric_Bit package using the NQTHM theorem prover, 3rd Asia Pacific Conference on Hardware Description Languages (APCHDL'96), Bengalore, INDIA, 8 au 10 janvier 1996
 
304 Ismail T., Jerraya A. A., Design models and steps for codesign, IEEE Colloquium on Verification of Hardware Software Codesign, pp. 1/1 - 1/2 , London, UNITED KINGDOM, DOI: 10.1049/ic:19951038, 17 octobre 1995
 
305 Romdhani A., Chambert P., Jeffroy A., De-Chazelles P., Jerraya A. A., Composing ActivityCharts/StateCharts, SDL and SAO specifications for codesign in avionics, European Design Automation Conference with EURO-VHDL (EURO-DAC'95), pp. 585-590, Brighton, ENGLAND, UNITED KINGDOM, DOI: 10.1109/EURDAC.1995.527465, 18 au 22 septembre 1995
 
306 Rahmouni M., Jerraya A. A., Formulation and evaluation of scheduling techniques for control flow graphs, European Design Automation Conference with EURO-VHDL (EURO-DAC'95), pp. 386-391, Brighton, ENGLAND, UNITED KINGDOM, DOI: 10.1109/EURDAC.1995.527434, 18 au 22 septembre 1995
 
307 Kission P., Ding Hong, Jerraya A. A., VHDL based design methodology for hierarchy and component re-use, European Design Automation Conference with EURO-VHDL (EURO-DAC'95), pp. 470-475, Brighton, ENGLAND, UNITED KINGDOM, DOI: 10.1109/EURDAC.1995.527446, 18 au 22 septembre 1995
 
308 Liem Cl. B., Paulin P., Cornero M., Jerraya A. A., Industrial experience using rule-driven retargetable code generation for multimedia applications, Eighth International Symposium on System Synthesis (ISSS'95), pp. 60-65, Cannes, FRANCE, DOI: 10.1145/224486.224499, 13 au 15 septembre 1995
 
309 Daveau J.- M., Ismail T., Jerraya A. A., Synthesis of system-level communication by an allocation-based approach, Eighth International Symposium on System Synthesis (ISSS'95), pp. 150-155, Cannes, FRANCE, DOI: 10.1109/ISSS.1995.520627, 13 au 15 septembre 1995
 
310 Romdhani A., Hautbois R.P., Jeffroy A., De-Chazelles P., Jerraya A. A., Evaluation and composition of specification languages, an industrial point of view, Asia and South Pacific Design Automation Conference. IFIP Design Automation Conference, 1995. Proceedings of the ASP-DAC '95/CHDL '95/VLSI '95., IFIP International Conference on Hardware Description Languages. IFIP International Conference on Very Large S, pp. 519-523, Chiba, JAPAN, DOI: 10.1109/ASPDAC.1995.486364, 29 août au 1 septembre 1995
 
311 Kission P., Jerraya A. A., High level specification in electronic design, IEEE International Symposium on Industrial Electronics (ISIE'95), pp. 21-26, Athens, GREECE, DOI: 10.1109/ISIE.1995.496472, 10 au 14 juillet 1995
 
312 Romdhani A., Jeffroy A., De-Chazelles P., Sahroui A.E.K., Jerraya A. A., Modeling and rapid prototyping of avionics using STATEMATE, Sixth IEEE International Workshop on Rapid System Prototyping (IWRSP'95), pp. 62-67, Chapel Hill, NC , UNITED STATES, DOI: 10.1109/IWRSP.1995.518572, 7 au 9 juin 1995
 
313 Valderrama C., Changuel A., P. Vijayaraghavan V., Abid M., Ben Ismail T., Jerraya A. A., A unified model for co-simulation and co-synthesis of mixed hardware/software systems, European Design and Test Conference (ED&TC'95), pp. 180-184, Paris, FRANCE, DOI: 10.1109/EDTC.1995.470395, 6 au 9 mars 1995
 
314 Rahmouni M., Jerraya A. A., PPS: a pipeline path-based scheduler, European Design and Test Conference (ED&TC'95), pp. 557-561, Paris, FRANCE, DOI: 10.1109/EDTC.1995.470345, 6 au 9 mars 1995
 
315 Ismail T., Abid M., Jerraya A. A., COSMOS: a codesign approach for communicating systems, Third International Workshop on Hardware/Software Codesign (CODES'94), pp. 17-24, Grenoble, FRANCE, DOI: 10.1145/947189, 22 au 24 septembre 1994
 
316 Voss M., Ismail T., Jerraya A. A., Kapp K.H., Towards a theory for hardware/software codesign, Third International Workshop on Hardware/Software Codesign (HSC'94), pp. 173-180, Grenoble, FINLAND, DOI: 10.1109/HSC.1994.336709, 22 au 24 septembre 1994
 
317 Kission P., Ding Hong, Jerraya A. A., Accelerating the design process by using architectural synthesis, The Fifth International Workshop on Rapid System Prototyping (IWRSP'94) , pp. 205-212, Grenoble, FRANCE, DOI: 10.1109/IWRSP.1994.315892, 21 au 23 juin 1994
 
318 Ismail T., Abid M., O'Brien K., Jerraya A. A., An approach for hardware-software codesign, The Fifth International Workshop on Rapid System Prototyping (RSP'94). Shortening the Path from Specification to Prototype, pp. 73-80, Grenoble, FRANCE, DOI: 10.1109/IWRSP.1994.315907, 21 au 23 juin 1994
 
319 Kission P., Ming Hong, Jerraya A. A., Structured design methodology for high-level design, 31st Design Automation Conference (DAC'94), pp. 466-471, San Diego, CA, UNITED STATES, DOI: 10.1145/196244.196470, 6 au 10 juin 1994
 
320 Ismail T., O'Brien K., Jerraya A. A., Interactive system-level partitioning with PARTIF, European Design and Test Conference. EDAC, The European Conference on Design Automation. ETC European Test Conference. EUROASIC, The European Event in ASIC Design , pp. 464-468, Paris, FRANCE, DOI: 10.1109/EDTC.1994.326835, 28 février au 3 mars 1994
 
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42 Chapitres de livre

 1 Faravelon A., Gruber O., Pétrot F., Removing Load/Store Helpers in Dynamic Binary Translation, Multi‐Processor System‐on‐Chip, Architectures, Liliana Andrade, Frédéric Rousseau (Eds.) , Ed. ISTE - International Scientific and Technical Encyclopedia, pp. 133-160, Vol. 1, DOI: 10.1002/9781119818298.ch7, 2021
 
 2 Wicaksana A., Muller O., Rousseau F., Sasongko A., Maintaining Communication Consistency during Task Migrations in Heterogeneous Reconfigurable Devices, Multi-Processor System-on-Chip 1: Architectures, Liliana Andrade Porras & Frédéric Rousseau (Eds.) , Ed. Wiley, Chichester, UK, pp. 255-285, Vol. 1, 2021
 
 3 Vianes A., Rousseau F., Study and Comparison of Hardware Methods for Distributing Memory Bank Accesses in Many-core Architectures, Multi-Processor System-on-Chip 1: Architectures, Liliana Andrade Porras & Frédéric Rousseau (Eds.) , Ed. Wiley, Chichester, UK, pp. 161-194, Vol. 1, 2021
 
 4 Hadj Salem K., Kieffer Y., Mancini S., Meeting the Challenges of Optimized Memory Management in Embedded Vision Systems Using Operations Research, Recent Advances in Computational Optimization, Results of the Workshop on Computational Optimization WCO 2016, Fidanova, Stefka (Eds.) , Ed. Springer , pp. 177-205, Vol. 717, 2018
 
 5 Pétrot F., Michel L., Deschamps Cl., Multiprocessor System-on-Chip Prototyping Using Dynamic Binary Translation, Handbook of Hardware/Software Codesign, Soonhoi Ha, Jürgen Teich (Eds.) , Ed. Springer , pp. 565-591, Vol. 1, DOI: 10.1007/978-94-017-7267-9, 2017
 
 6 Foroutan S., Sheibanyrad H., Pétrot F., Network-on-Chip Performance Evaluation Using an Analytical Method, Multicore Technology: Architecture, Reconfiguration, and Modeling, Muhammad Yasir Qadri, Stephen J. Sangwine (Eds.) , Ed. CRC Press, pp. 353-407, 2013
 
 7 Pétrot F., Gerin P., Hamayun M.M., On Software Simulation for MPSoC. A Modeling Approach for Functional Validation and Performance Estimation, Design Technology for Heterogeneous Embedded Systems, Nicolescu, O'Connor, Piguet, editors (Eds.) , Ed. Springer , pp. 91-114, DOI: DOI/ 10.1007/978-94-007-1125-9_5, 2012
 
 8 Sheibanyrad H., Pétrot F., Asynchronous 3D-NoCs Making Use of Serialized Vertical Links, 3D Integration for NoC-based SoC Architectures , Hamed Sheibanyrad, Frédéric Pétrot and Axel Jantsch (Eds.) , Ed. Springer , pp. 149-165, DOI: DOI: 10.1007/978-1-4419-7618-5_7 , 2011
 
 9 Guérin X., Pétrot F., Operating System Support for Applications targeting Heterogeneous Multi-Core System-on-Chips, Multi-Core Embedded Systems , George Kornaros (Eds.) , Ed. CRC Press, pp. chapter 9, 24 p., DOI: http://www.crcpress.com/product/isbn/9781439811610;jsessionid=fVViXIaHOZIraRJqOguAuA**, 2010
 
10 Popovici K.M., Jerraya A. A., Hardware Abstraction Layer – Introduction and Overview, Hardware dependent Software, Concept, Tools and Applications, Principles and Practice, Wolfgang Ecker, Wolfgang Mller, Rainer Domer (Eds.) , Ed. Springer , pp. 67- 94, DOI: 10.1007/978-1-4020-9436-1, 2009
 
11 Dubois Ma., Rousseau F., Aboulhamid E.M., An Introduction to Cosimulation and Compilation Methods, System Level Design with .NET Technology, ABOULHAMID E. M., ROUSSEAU F. (Eds.) , Ed. CRC Press, pp. 177-202, 2009
 
12 Pétrot F., Gerin P., Simulation at Cycle Accurate and Transaction Accurate Levels, System Level Design with .NET Technology, ABOULHAMID E. M., ROUSSEAU F. (Eds.) , Ed. CRC Press, pp. 155-175, 2009
 
13 Augé I., Pétrot F., User Guided High Level Synthesis, High Level Synthesis, from Algorithm to Digital Circuit, P. Coussy & A. Moraviec (Eds.) , Ed. Springer , pp. 171-196 , DOI: DOI: 10.1007/978-1-4020-8588-8_10, 2008
 
14 Jerraya A. A., Daveau J.- M., Marchioro G.F., Valderrama C., Romdhani M., Ben Ismail T., Zergainoh N.-E., Hessel F., Coste P., Le Marrec Ph., Baghdadi A., Gauthier L., Hardware/Software Codesign , Design of Systems on Chip, Design and test, Reis Ricardo, Lubaszewski Marcelo, Jess Jochen A.G. (Eds.) , Ed. Springer , pp. 133-158, 2007
 
15 Metzger M., Bastien F., Rousseau F., Vachon J., Aboulhamid E.M., Observer-based verification using introspection: a system-level verification implementation, Advances in Design and Specification Languages for Embedded Systems – Selected Contributions from FDL’06, Sorin A. Huss (Eds.) , Ed. Springer , pp. 209-224, DOI: DOI 10.1007/978-1-4020-6149-3_13, 2007
 
16 Jerraya A. A., Bacivarov I., Performance evaluation methods for MPSoC Design, EDA for IC System Design, Verification, and Testing, Ed. CRC Press, pp. Chapter 6, 2006
 
17 Yoo S., Bouchhima A., Cesario W., Jerraya A. A., Gauthier L., Low-Power SoC with Power-Aware Operating Systems Generation, Low-Power Electronics Design, Christian Piguet (Eds.) , Ed. CRC Press, pp. chapitre 3, 2004
 
18 Cesario W., Wagner F.R., Jerraya A. A., Hardware/Software Interfaces Design for SoC, The Industrial Information Technology Handbook, Ed. CRC Press, pp. section VI, N°94, 2004
 
19 Majauskas G., Lyonnard D., Cesario W., Paviot Y., Gauthier L., Jerraya A. A., Stuikys V., Communication Co-Processor Design by Composition of Parameterized Cells, Information Technology and Control, Ed. , pp. 13-20, 2004
 
20 Cho Y., Lee G., Choi K., Yoo S., Zergainoh N.-E., Scheduling and timing analysis of HW/SW on-chip communication in MP SoC design, Embedded Software for SoC, Ed. Kluwer Academic Publishers, pp. 125-136, DOI: hal-00016129 , 2003
 
21 Yoo S., Jerraya A. A., Introduction to Hardware Abstraction Layers for SoC, Embedded Software for SoC, Ed. Kluwer Academic Publishers, pp. chapitre 14, 179-186, 2003
 
22 Yoo S., Nuta Nicolescu E.G., Bacivarov I., Youssef W., Bouchhima A., Jerraya A. A., Multi-level software validation for NoC, Networks-on-chip., Ed. Kluwer Academic Publishers, pp. 261-79, 2003
 
23 Paviot Y., Application du flot de ciblage logiciel, Conception des logiciels embarqués pour les systèmes monopuces, Ed. Hermès, pp. 196p. 16x24, 2003
 
24 Meftali S., Gharsalli F., Rousseau F., Jerraya A. A., Automatic code-transformation and architecture refinement for application-specific multiprocessor SoCs with shared memory, SOC Design Methodologies IFIP TC10 / WG10.5 Eleventh International Conference on Very Large Scale Integration of Systems-on-Chip (VLSI-SOC’01) December 3–5, 2001, Montpellier, France, Robert, M., Rouzeyre, B., Piguet, C., Flottes, M.-L. (Eds.) , Ed. Springer , pp. 193-204, 2002
 
25 Zergainoh N.-E., Méthodologie et modèles pour la conception digitale, Conception de haut niveau des systèmes monopuces, JERRAYA, A. (Eds.) , Ed. Hermès, pp. chapitre 1 : 19-64, 2002
 
26 Rousseau F., La conception système et le découpage logiciel/matériel, Conception de haut niveau des systèmes monopuces (Traité EGEM, Série électronique et micro-électronique), Ed. Hermès, pp. chapitre 4: 109-138, 2002
 
27 Hessel F., Jerraya A. A., Spécification et conception des systèmes hétérogènes, Conception de haut niveau des systèmes monopuces, Ed. Hermès, pp. 175-200 ; chapitre 6, 2002
 
28 Cesario W., Jerraya A. A., La conception comportementale, Conception de haut niveau des systèmes monopuces (Traité EGEM, Série électronique et micro-électronique), Ed. Hermès, pp. 65-108 ; chapitre 3, 2002
 
29 Valderrama C., Changuel A., P. Vijayaraghavan V., Abid M., Ben Ismail T., Jerraya A. A., A unified model for co-simulation and co-synthesis of mixed hardware/software systems, Readings in Hardware/Software Co-Design, G. De Micheli, R. Ernst, and W. Wolf (Eds.) , Ed. Morgan Kaufmann Publishers, pp. 579-583, 2001
 
30 Baghdadi A., Zergainoh N.-E., Lyonnard D., Jerraya A. A., Generic architecture platform for multiprocessor system-on-chip design, Architecture and Design of Distributed Embedded Systems, IFIP WG10.3/WG10.4/WG10.5 International Workshop on Distributed and Parallel Embedded Systems (DIPES 2000) October 18–19, 2000, Schloß Eringerfeld, Germany, Kleinjohann, Bernd (Eds.) , Ed. Kluwer Academic Publishers, pp. 53-63, 2001
 
31 Zergainoh N.-E., Baghdadi A., Tambour L., Lyonnard D., Gauthier L., Jerraya A. A., Framework for system design, validation and fast prototyping of multiprocessor SoCs, Architecture and Design of Distributed Embedded Systems Series: IFIP International Federation for Information Processing,, Ed. Kluwer Academic Publishers, pp. ., 2001
 
32 Daveau J.- M., Ben Ismail T., Marchioro G.F., Jerraya A. A., Protocol selection and interface generation for HW-SW codesign, Readings in Hardware/Software Co-Design, Ed. Morgan Kaufmann Publishers, pp. 366-374 : Chapitre 4, 2001
 
33 Daveau J.- M., Marchioro G.F., Valderrama C., Jerraya A. A., VHDL generation from SDL specification, Readings in Hardware/Software Co-Design, Ed. Morgan Kaufmann Publishers, pp. 125-134 : Chapitre 2, 2001
 
34 Hessel F., Le Marrec Ph., Valderrama C., Jerraya A. A., Romdhani A., MCI - multilanguage distributed co-simulation tool, Distributed and Parallel Embedded Systems, IFIP WG10.3/WG10.5 International Workshop on Distributed and Parallel Embedded Systems (DIPES’98) October 5–6, 1998, Schloß Eringerfeld, Germany, Rammig F.J. (Eds.) , Ed. Springer , pp. 191-200, Vol. 25, DOI: 10.1007/978-0-387-35570-2_17, 1999
 
35 Moussa I., Diaz-Nava M., Jerraya A. A., Analysing the cost of design for reuse, Reuse Techniques for VLSI Design, Ed. Kluwer Academic Publishers, pp. chapitre 2, 1999
 
36 Jerraya A. A., Romdhani A., Le Marrec Ph., Hessel F., Coste P., Valderrama C., Marchioro G.F., Daveau J.- M., Zergainoh N.-E., Multilanguage specification for system design and codesign, System-Level Synthesis, Ed. Kluwer Academic Publishers, pp. Vol. 357, 1999
 
37 Amblard P., A finite state description of the earliest logical computer : the Jevons'Machine, Mixed design of integrated circuits and systems, A. Napieralski, Z. Ciota, A. Martinez, G. de Mey, J. Cabestany (Eds), 1998, Ed. Kluwer Academic Publishers, pp. 256 p., DOI: http://www.lavoisier.fr/notice/gb062064.html, 1998
 
38 Liem Cl. B., Paulin P., Compilation techniques and tools for embedded processor architectures, Hardware/Software Codesign : Principles and Practice , W. Wolf, J. Staunstrup (Eds.) , Ed. Kluwer Academic Publishers, pp. 149-191, 1997
 
39 Daveau J.- M., Marchioro G.F., Ben Ismail T., Jerraya A. A., Cosmos: An SDL Based Hardware/Software Codesign Environment, Hardware/Software Co-Design and Co-Verification, Ed. Springer , pp. 59-87, Vol. 8, DOI: 10.1007/978-1-4757-2629-9_3, 1997
 
40 Valderrama C., Romdhani A., Daveau J.- M., Marchioro G.F., Changuel A., Jerraya A. A., COSMOS : a transformational co-design tools for multiprocessor architectures, Hardware/Software Co-Design: Principles and Practice, Ed. Kluwer Academic Publishers, pp. chapitre 10, 1997
 
41 Jerraya A. A., Romdhani A., Valderrama C., Le Marrec Ph., Hessel F., Marchioro G.F., Daveau J.- M., Languages for system level specification and design, Hardware/Software Co-Design: Principles and Practice, Ed. Kluwer Academic Publishers, pp. CHAPITRE 7, 1997
 
42 Paulin P., Cornero M., Liem Cl. B., Nacabal F., Donawa C., Sutarwala S., May T., Valderrama C., Trends in embedded systems technology: an industrial perspective, Hardware/Software Co-Design, Edited by M.G. Sami, G. De Micheli, Ed. Kluwer Academic Publishers, pp. , 1996
 
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17 Livres & Éditions Ouvrages

 1 Andrade Porras L.L., Rousseau F. (Eds.) Multi-Processor System-on-Chip 1: Architectures, Vol. 1, pp. 320, Ed. Wiley, Chichester, UK, 2021
 
 2 Andrade Porras L.L., Rousseau F. (Eds.) Multi-Processor System-on-Chip 2: Applications, Vol. 2, pp. 272, Ed. Wiley, Chichester, UK, 2021
 
 3 Sheibanyrad H., Pétrot F., Jantsch A. (Eds.) 3D Integration for NoC-based SoC Architectures, Integrated Circuits and Systems, pp. 278 p., Ed. Springer , 2011
 
 4 Popovici K.M., Rousseau F., Jerraya A. A., Wolf M. (Eds.) Embedded Software Design and Programming of Multiprocessor System-on-Chip: Simulink and SystemC Case Studies, Embedded Systems , pp. 290 p., Ed. Springer , 2010
 
 5 Aboulhamid E.M., Rousseau F. (Eds.) System Level Design with .NET Technology, pp. 328 p., Ed. CRC Press, 2009
 
 6 Jerraya A. A., Nuta Nicolescu E.G. (Eds.) Global Specification and Validation of Embedded Systems: Integrating Heterogeneous Components, Ed. Springer , 2007
 
 7 Jerraya A. A., Tenhunen H., Wolf W. (Eds.) Guest Editors' Introduction: Multiprocessor Systems-on-Chips, Special issue, Computer Review(International), Vol. 38, Issue 7, pp. 36-40, Ed. IEEE, 2005
 
 8 Jerraya A. A., Wolf W. (Eds.) MULTIPROCESSOR SYSTEMS-ON-CHIPS, pp. 608, Ed. Morgan Kaufmann Publishers, 2004
 
 9 Jerraya A. A., Nuta Nicolescu E.G. (Eds.) Spécification et validation des systèmes monopuces (Traité EGEM série Electronique et micro-éléctronique), pp. 216p. 16x24, Ed. Hermès, 2004
 
10 Jerraya A. A., Yoo S., Verkest D., Wehn N. (Eds.) Embedded Software for SoC, pp. 585, Ed. Kluwer Academic Publishers, 2003
 
11 Jerraya A. A. (Eds.) Conception de haut niveau des systèmes monopuces (Traité EGEM, Série électronique et micro-électronique), pp. 224p. 16x24, Ed. Hermès, 2002
 
12 Jerraya A. A. (Eds.) Conception logique et physique des systèmes monopuces (Traité EGEM Série électronique et micro-électronique), pp. 246p. 16x24, Ed. Hermès, 2002
 
13 Courtois B., Karam J.M., Walker J.A., Levitan S.P., Markus K., Tay A.A.O. (Eds.) Proceedings on Symposium on Design, Test, Integration and Packaging of MEMS/MOEMS (DTIP'2001), Cannes - Mandelieu, France, April 25-27, 2001, pp. 556 pages, Ed. TIMA Laboratory, 46 avenue Félix Viallet, 38031 Grenoble Cedex, 2001
 
14 Amblard P., Lagnier F., Sicard P., Fernandez J.-C., Maraninchi F., Waille Ph. (Eds.) Architectures logicielles et matérielles, Sciences Sup , Ed. Dunod, 2000
 
15 Jerraya A. A., Mermet J. (Eds.) System-Level Synthesis: Proceedings of the NATO Advanced Study Institute on System Level Sythesis for Electronic Design, held in Il Ciocco, Lucca, Italy, 11-12 August 1998, pp. 452 pages, Ed. Springer , 1999
 
16 Liem Cl. B. (Eds.) Retargetable compilers for embedded core processors : methods and experiences in industrial applications, Ed. Kluwer Academic Publishers, 1997
 
17 Jerraya A. A., Kission P., Ding Hong, Rahmouni M. (Eds.) Behavioral Synthesis and Component Reuse with VHDL, Ed. Kluwer Academic Publishers, 1996
 
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21 Revues nationales

 1 Rousseau F., Muller O., Conception des systèmes VLSI, Techniques de l'Ingénieur, Vol. E 2 455 / Base documentaire : TIB276DUO, novembre 2018
 
 2 Sarrazin G., Fournel N., Gerin P., Pétrot F., Simulation native basée sur le support matériel à la virtualisation cas des systèmes many-cœurs spécifiques, Technique et Science Informatiques (TSI), Vol. 34, No. 1-2, pp. 153-173, DOI: 10.3166/tsi.34.153-173 , janvier-février 2015
 
 3 Meunier Q., Pétrot F., Systèmes de mémoire transactionnelle pour les architectures à base de NoC Conception, implémentation et comparaison de deux politiques, Technique et Science Informatiques (TSI), Vol. 30/9 , pp. 1061-1087, DOI: 10.3166/tsi.30.1061-1087 , 2011
 
 4 Abril A., Mehrez H., Pétrot F., Gobert J., Miro C., Estimation et optimisation de la consommation dans les SoC utilisant la simulation précise au cycle, Technique et Science Informatiques (TSI), Vol. 27, n ̊ 1-2, pp. 203-233, 2008
 
 5 Amblard P., Un nouveau regard sur la machine logique de Jevons, Technique et Science Informatiques (TSI), Vol. 26, No. 10, pp. 1207-1225 , janvier 2007
 
 6 Rousseau F., Conception des Systèmes VLSI, Techniques de l'Ingénieur, Vol. E 2 455, 2005
 
 7 Zergainoh N.-E., Tambour L., Michel H., Jerraya A. A., Delay Correction in RTL Models of DSP SoC obtained by IP-based design approach, Technique et Science Informatiques (TSI), Vol. 24/10, pp. 1227-1257, 2005
 
 8 Gharsalli F., Rousseau F., Jerraya A. A., Hardware/software interface design for global memory integration in System-On-Chip, Technique et Science Informatiques (TSI), Vol. 24, No. 4, pp. 369-394, avril 2005
 
 9 Nuta Nicolescu E.G., Svarstad G., Cesario W., Gauthier L., Lyonnard D., Yoo S., Coste P., Jerraya A. A., Desiderata for the specification and design of electronic systems, Technique et Science Informatiques (TSI), Vol. 21, No. 3, pp. 291-314, mars 2002
 
10 Baghdadi A., Zergainoh N.-E., Cesario W., Jerraya A. A., Architecture design space exploration for hardware/software codesign: system-level performance estimation, Technique et Science Informatiques (TSI), Vol. 21, No. 1, pp. 9-35, DOI: 10.3166/tsi.21.9-35 , janvier 2002
 
11 Ouni R., Soudani A., Nasri S., Torki K., Abid M., Tourki R., TCP flow control technique for an interworking interface: hardware implementation, Computer Standards & Interfaces, Vol. 23, No. 5, pp. 383-397, novembre 2001
 
12 Cesario W., Jerraya A. A., Flexible design flow for behavioral synthesis. An effective approach for tool integration, Technique et Science Informatiques (TSI), Vol. 20, No. 10, pp. 1279-1304, octobre 2001
 
13 Nacabal F., Valderrama C., Hessel F., Paulin P., Jerraya A. A., Co-simulation C-VHDL pour la validation fonctionnel de logiciel embarqué, Technique et Science Informatiques (TSI), Vol. 19, No. 8, octobre 2000
 
14 Nacabal F., Valderrama C., Hessel F., Paulin P., Jerraya A. A., C-VHDL co-simulation for functional validation of embedded software, Technique et Science Informatiques (TSI), Vol. 19, No. 8, pp. 1097-126, octobre 2000
 
15 Souani C., Atri M., Abid M., Torki K., Tourki R., Design of new optimized architecture processor for DWT, Real Time Imaging, Vol. 6, No. 4, pp. 297-312, DOI: 10.1006/rtim.1999.0178, août 2000
 
16 Zitouni A., Souani C., Abid M., Torki K., Tourki R., A communication synthesis approach for distributed systems, Technique et Science Informatiques (TSI), Vol. 19, No. 4, pp. 515-547, avril 2000
 
17 Benmohammed M., Kission P., Rahmouni M., Liem Cl. B., Jerraya A. A., Automatic generation of reprogrammable controllers in a high level synthesis environment, Technique et Science Informatiques (TSI), Vol. 17, No. 10, pp. 1277-1297, décembre 1998
 
18 Abid M., Changuel A., Valderrama C., Jerraya A. A., Hardware-software codesign methodology starting from C/VHDL models, Technique et Science Informatiques (TSI), Vol. 17, No. 2, pp. 157-80, février 1998
 
19 Romdhani A., Sahroui A.E.K., Jeffroy A., Jerraya A. A., Traore I., Integration of partial specifications of avionics, Journal Européen des Systèmes Automatisés (RS-JESA) , Ed. Hermès, Vol. 31, No. 7, pp. 1221-1251, novembre 1997
 
20 Ismail T., Marchioro G.F., Jerraya A. A., Partitioning of VLSI systems from a high-level specification, Technique et Science Informatiques (TSI), Vol. 15, No. 8, pp. 1131-1165, août 1996
 
21 Aichouchi M., Kission P., Jerraya A. A., Linking architectural synthesis with register transfer level design tools, Technique et Science Informatiques (TSI), Vol. 15, No. 2, pp. 179-199, février 1996
 
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35 Conférences nationales

 1 Andrade Porras L.L., Benabdenbi M., Muller O., Rousseau F., Pétrot F., Teaching basic computer architecture, assembly language programming, and operating system design using RISC-V, RISC V week 2019, Paris, FRANCE, 1 au 2 octobre 2019
 
 2 Fernandez-Brillet L., Mancini S., Cleyet-Merle S., Nicolas M., Compression adaptative des CNNs par réduction de la dimensionnalité, XXVIIème Colloque francophone de traitement du signal et des images (GRETSI 2019), Lille, FRANCE, 26 au 29 août 2019
 
 3 Bernard M., Montémont G., Stanchina S., Mancini S., Verger L., Méthode de reconstruction en ligne pour un système SPECT adaptatif, Colloque GRETSI sur le traitement du signal et des images (GRETSI 2017), Juan les Pins, FRANCE, 5 au 8 septembre 2017
 
 4 Bourge A., Muller O., Rousseau F., Flot de conception automatique pour circuits commutables, Conférence d’informatique en Parallélisme, Architecture et Système (COMPAS'16), Lorient, FRANCE, 5 au 8 juillet 2016
 
 5 Muller O., Sasongko A., Rousseau F., Wicaksana A., Validation automatique d’une méthode de migration des tâches sur la plateforme Zynq, Journées Nationales du Réseau Doctoral en Micro-nanoélectronique (JNRD'16), Toulouse, FRANCE, 11 au 13 mai 2016
 
 6 Hadj Salem K., Kieffer Y., Mancini S., Minimisation des accès mémoires dans un cache intelligent pour les systèmes de vision embarquée, 17ème Congrès Annuel de la Société Française de Recherche Opérationnelle et Aide à la Décision, pp. 1-2, Compiègne, FRANCE, 10 février 2016
 
 7 Payet M., Fresse V., Rousseau F., Rémy P., Extraction du parallélisme à l'exécution pour la syntghèse d'applications basées sur un NoC, Conférence en Parallélisme , Architecture et Système (ComPAS'15), Lille, FRANCE, 30 juin au 3 juillet 2015
 
 8 Schwambach V., Cleyet-Merle S., Issard A., Mancini S., Estimating the Potential Speedup of Computer Vision Applications on Embedded Multiprocessors, 18ème Journées Nationales du Réseau Doctoral en Micro- nanoélectronique (JNRDM'15), Bordeaux, FRANCE, 5 au 7 mai 2015
 
 9 Bernard M., Montémont G., Stanchina S., Mancini S., Verger L., Intégration du modèle pour la reconstruction itérative de l’image en tomographie d’émission monophotonique, Journées Nationales du Réseau Doctoral en Micro-nanoélectronique (JNRDM'15), Bordeaux, FRANCE, 5 au 7 mai 2015
 
10 Bourge A., Ghiti A., Muller O., Rousseau F., Méthode de sélection de checkpoint matériel avec outil de synthèse de haut niveau , Journées Nationales du Réseau Doctoral en Microélectronique (JNRDM'14), pp. 4, Lille, FRANCE, 26 au 28 mai 2014
 
11 Mancini S., Adaptation dynamique en boucle fermée d'un pré-chargement stochastique dans les tableaux , Conférence en Parallélisme, Architecture et Système (COMPAS'14), Neuchâtel, SWITZERLAND, 22 au 25 avril 2014
 
12 Schwambach V., Cleyet-Merle S., Issard A., Mancini S., Optimisation de performance au niveau applicatif : étude de cas de vision embarquée sur STHORM, Conférence en Parallélisme, Architecture et Système (ComPAS’2014), Neuchâtel, SWITZERLAND, 22 avril au 25 août 2015
 
13 Schwambach V., Cleyet-Merle S., Issard A., Mancini S., Optimisation de performance au niveau applicatif: étude de cas de vision embarquée sur STHORM , Conférence en Parallélisme, Architecture et Système (COMPAS'14), Neuchâtel, SWITZERLAND, 22 au 25 avril 2014
 
14 Sarrazin G., Pétrot F., Fournel N., Gerin P., Simulation native de systèmes many-cœurs pouvant avoir des caractéristiques architecturales non génériques, Conférence d’informatique en Parallélisme (COMPAS'14), Architecture et Système, Neuchâtel, SWITZERLAND, 22 au 25 avril 2014
 
15 Prost-Boucle A., Muller O., Rousseau F., Méthodologie de génération rapide et automatique d’accélérateurs matériels sous contraintes de ressources : progression itérative et gloutonne, Conférence en Parallélisme, Architecture et Système (ComPAS'13), Grenoble, FRANCE, 15 au 18 janvier 2013
 
16 Mancini S., Rousseau F., Optimisation d’accélérateurs matériels de traitement par incorporation d’un gestionnaire de données et de contrôle dans un flot de HLS, Conférence en Parallélisme, Architecture et Système (ComPAS'13), Grenoble, FRANCE, 15 au 18 janvier 2013
 
17 El-Antably A., Rousseau F., Task migration in multi-tiled MPSoC : Challenges, state-of-the-art and preliminary solutions, Journées nationales du réseau doctoral en Microélectronique (JNRDM'12), Marseille, FRANCE, 18 au 20 mai 2012
 
18 Chagoya-Garzon A., Rousseau F., Gestion des Communications dans les Outils de Conception du Logiciel Embarqué pour les Systèmes Multi-tuiles Hétérogènes, Journées nationales du réseau doctoral en Microélectronique (JNRDM'10), Montpellier, FRANCE, 7 au 9 juin 2010
 
19 Meunier Q., Pétrot F., LightTM : Une Mémoire Transactionnelle conçue pour les MPSoCs , Symposium en Architecture de machines (SympA'13), pp. 1-12 , Toulouse, FRANCE, 9 au 11 septembre 2009
 
20 Pétrot F., Guironnet de Massas P., Migration de données dans les MPSoC : une solution matérielle, 3ème Symposium en Architecture de machines (SympA'13), pp. 1-12, Toulouse, FRANCE, 9 au 11 septembre 2009
 
21 Chagoya-Garzon A., Guérin X., Rousseau F., Outils de Génération du Logiciel pour les Systèmes sur Puce Multi-Processeur Hétérogènes, Journées Nationales du RÉseau Doctoral en Microélectronique (JNRDM’09), Bordeaux, FRANCE, 14 au 16 mai 2009
 
22 Chagoya-Garzon A., Guérin X., Rousseau F., Outils de génération de logiciel pour les systèmes sur puce multi-processeur hétérogènes, 11th Journées Nationales du Réseau Doctoral en Microélectronique (JNRDM’08), Bordeaux, FRANCE, 14 au 16 mai 2008
 
23 Guironnet de Massas P., Etude des problèmes de cohérence mémoire dans des systèmes multiprocesseurs à mémoire partagée intégrés sur une même puce, Journées GDR SoC-SiP, Paris, FRANCE, 13 au 15 juin 2007
 
24 Senouci B., Kouadri Mostéfaoui A., Rousseau F., Prototypage d’Applications POSIX sur une architecture, Journées nationales du réseau doctoral en Microélectronique (JNRDM'07), Lille, FRANCE, 14 au 16 mai 2007
 
25 Senouci B., Kouadri Mostéfaoui A., Rousseau F., Pétrot F., Prototypage d'Applications POSIX sur une architecture Multiprocesseur, Journées Nationales du Réseau Doctoral en Microélectronique (JNRDM’07), Lilles, FRANCE, 14 au 16 mai 2007
 
26 Atat Y., Zergainoh N.-E., Jerraya A. A., Environnement de Conception, de Validation, et de Prototypage Rapide des Systèmes Multiprocesseurs sur Puce, pour les applications de traitement de signal, 9ème Journées Nationales en Microélectronique, Rennes, FRANCE, 10 au 12 mai 2006
 
27 Atat Y., Zergainoh N.-E., Jerraya A. A., Conception des Systèmes sur puce à partir de Matlab\Simulink, 8ème Journées Nationales en Microélectronique, Paris, FRANCE, 10 au 12 mai 2005
 
28 Grasset A., Rousseau F., Jerraya A. A., Vers l'Automatisation de la Conception des Coprocesseurs de Communication pour les Systèmes Monopuces, Journées nationales du réseau doctoral en Microélectronique (JNRDM'05), Paris, FRANCE, 10 au 12 mai 2005
 
29 Grasset A., Rousseau F., Jerraya A. A., Génération des Interfaces de Communication pour Systèmes Multiprocesseurs Monopuces : de la Spécification des Services de Communication vers l'Implémentation RTL, Journées nationales du réseau doctoral en Microélectronique (JNRDM'04), Marseille, FRANCE, 4 au 6 mai 2004
 
30 Baghdadi A., Jerraya A. A., Zergainoh N.-E., Exploration et conception systématique d'architectures multiprocesseurs monopuces dédiées à des applications spécifiques, 3ème Colloque CAO de circuits et systèmes intégrés, Paris, FRANCE, 15 au 17 mai 2002
 
31 Tambour L., Urard P., Ghenassia F., Zergainoh N.-E., Valentin T., Jerraya A. A., Utilisation d'une méthode de correction de retards pour la vérification d'un assemblage de fonctions RTL par rapport à un assemblage de fonctions au niveau fonctionnel, 3ème Colloque CAO de circuits et systèmes intégrés, Paris, FRANCE, 15 au 17 mai 2002
 
32 Gharsalli F., Meftali S., Rousseau F., Jerraya A. A., Générateur d'adaptateurs mémoire pour les architectures multiprocesseurs monopuces, Colloque CAO (organisé par le CNRS), Paris, FRANCE, 1 mai 2002
 
33 Amblard P., De nouvelles pistes dans l'initiation à la conception de circuits digitaux : machines pipelinées et preuves de circuits, Sixièmes Journées Pédagogiques, Centre Commun de Microélectronique de l'Ouest (CCMO'00), Saint Malo, FRANCE, 29 novembre au 1 décembre 2000
 
34 Freund L., Israel M., Rousseau F., Berge J.M., Auguin M., Belleudy C., Gogniat G., Etude de la conception logiciel/matériel d’une application d’annulation d’écho acoustique, Colloques CAO de circuits intégrés et systèmes, Grenoble, FRANCE, 15 au 17 janvier 1997
 
35 Rousseau F., Berge J.M., Israel M., Synthèse des méthodes et algorithmes de partitionnement logiciel/matériel, Symposium Architectures Nouvelles de Machines, Rennes, FRANCE, 1 février 1996
 
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29 Autres communications

 1 Pétrot F., A Deadlock-Free Distributed Routing Algorithm for Vertically Partially Connected 3D-NoCs, 12th International Forum on Embedded MPSoC and Multicore, Quebec, CANADA, 2012
 
 2 Pétrot F., Foroutan S., Sheibanyrad H., Cost-Efficient Buffer Sizing in Shared-Memory 3D-MPSoCs Using Wide I/O Interfaces, 5th Design for 3D Silicon Integration Workshop, Grenoble, FRANCE, 2013
 
 3 Pétrot F., Meunier Q., Design and Use of Transactional Memory in MPSoCs, 9th International Seminar on Application Specific Multiprocessor SoC, Savanah, Georgia, UNITED STATES, 2009
 
 4 Baumela T., Gruber O., Pétrot F., Périphériques Orientés Message sur FPGA, Conférence d’informatique en Parallélisme, Architecture et Système (COMPAS 2018), pp. 1-9, Toulouse, FRANCE, 2018
 
 5 Jerraya A. A., Long term trends for embedded system design, CEPA 2 Workshop - Digital Platforms for Defence, Brussels, BELGIUM, 2005
 
 6 Pétrot F., Less TSVs in 3D chips through Asynchronous Serialization, 4th Design for 3D Silicon Integration Workshop, Grenoble, FRANCE, 2011
 
 7 Pétrot F., Guironnet de Massas P., De l’accès transparent et optimisé aux données dans les systèmes multiprocesseurs intégrés, 4ème Ecole d’hiver francophone sur les systèmes hétérogènes (FETCH'10), Chamonix, FRANCE, 2010
 
 8 Pétrot F., Gerin P., Estimation de performance du logiciel embarqué utilisant une technique d’annotation du code natif, 3ème Ecole d’hiver francophone sur les systèmes hétérogènes, Chexbres, SWITZERLAND, 2009
 
 9 Pétrot F., Fournel N., Gligor M., Annotation within dynamic binary translation for fast and accurate system simulation, 10th International Forum on Embedded MPSoC and Multicore (MPSoc'10), Gifu, JAPAN, 2010
 
10 Kriaa L., Pétrot F., Low power hardware dependent software for Multiprocessor System on Chip , MEDEA+ Desgin Automation Conference (DAC’07), Grenoble, FRANCE, 2007
 
11 Mancini S., Rousseau F., Design of non-linear kernel IPs for vision systems , WACS Congress, Clermont Ferrand, FRANCE, 2012
 
12 Pétrot F., HW/SW Interfaces Abstraction and Design for SoC, MEDEA+ Desgin Automation Conference, Les Mesnuls, FRANCE, 2005
 
13 Hedde D., Horrein P.H., Pétrot F., Rolland R., Rousseau Fra., Une plate-forme d'expérimentation multiprocesseur pour les réseaux sans fil , 10èmes Journées Pédagogiques du CNFM, pp. 163-168 , Saint-Malo, FRANCE, 2008
 
14 Pétrot F., A Few Open Problems in Vertically-Partially-Connected 3D-NoC, 15th International Forum on MPSoC for Software-defined Hardware, Ventura Beach Marriott, CA, UNITED STATES, 2015
 
15 Pétrot F., A Service Based Component Model for Multi-Level HW/SW Specifications , 5th International Seminar on Application Specific Multiprocessor SoC , Margaux, FRANCE, 2005
 
16 Amblard P., Finite state evaluation of logical formulas : Jevons' Approach (1870) and contemporary description , Acta Cybernetica, Ed. Szeged, University Szeged, Hungary, Vol. Vol 17, No. 4, pp. 665-684, 2006
 
17 Pétrot F., Abstract executable modeling of MPSoC HW/SW interfaces, International Forum on Application-Specific Multi-Processor SoC, Awaji Island, Hyogo, JAPAN, 2007
 
18 Pétrot F., Bouchhima A., Gerin P., Automatic timing annotation of native software for MPSoC simulation, 8th International Forum on Application-Specific Multi-Processor SoC (MPSoC), Aachen, GERMANY, 2008
 
19 Pétrot F., Utilisation de techniques de traduction binaire dynamique pour la simulation rapide et précise des MPSoCs, Ecole d'hiver Francophone sur les Technologies de Conception des Systèmes embarqués Hétérogènes (Fetch'11), Quebec, CANADA, 2011
 
20 Pétrot F., Fournel N., Gligor M., A Power Aware Transactional Level Multi-processor SoC Simulation Environment, MEDEA+/CATRENE Design Technology Conference, Dresden, GERMANY, 2009
 
21 Pétrot F., Guironnet de Massas P., Optimized and Transparent Data Accesses in Homogeneous MPSoC, Visionary scientific seminar, « The future of Computing : Massively Parallel Computing », IP-Embedded Systems Conference, Grenoble, FRANCE, 2009
 
22 Bruant J., Horrein P.H., Muller O., Groleat T., Pétrot F., (System)Verilog to Chisel Translation for Faster Hardware Design, 31th International Symposium on Rapid System Prototyping (RSP 2020), Virtual Conference, FRANCE, 2020
 
23 Christ M., Forget L., De Dinechin F., Lossless Differential Table Compression for Hardware Function Evaluation / Compression de table sans perte pour l'évaluation matérielle de fonctions, , Grenoble, FRANCE, 2020
 
24 Pétrot F., Hamayun M.M., Fournel N., Simulation native des systèmes intégrés utilisant le support matériel à la virtualisation, Ecole d'hiver Francophone sur les Technologies de Conception des Systèmes embarqués Hétérogènes, Leysin, SWITZERLAND, 2013
 
25 Ferres Bruno, Muller O., Rousseau F., Chisel Usecase: Designing General Matrix Multiply for FPGA, Applied Reconfigurable Computing. Architectures, Tools, and Applications (ARC 2020), pp. 61-72, Toledo, SPAIN, DOI: 10.1007/978-3-030-44534-8_5, 2020
 
26 Pétrot F., Kouadri Mostéfaoui A., De l’émulation des « NoC » à la synthèse des « NiP », 2ème Ecole d’hiver francophone sur les systèmes hétérogènes, Montebello, Québec, CANADA, 2008
 
27 Pétrot F., Traces non intrusives : un outil d'analyse du logiciel et du matériel pour les MPSoCs, Ecole d'hiver Francophone sur les Technologies de Conception des Systèmes embarqués Hétérogènes (FETCH'14), Ottawa, Ontario, CANADA, 2014
 
28 Abid M., Torki K., Zitouni A., Tourki R., Communication synthesis techniques for multiprocessor systems, International Journal of Electronics, Ed. Taylor & Francis group, Vol. Jan. ; 89(1), pp. 55-76, DOI: 10.1080/00207210110100339, 2002
 
29 Pétrot F., Gerin P., Chureau A., Shen H., Bouchhima A., Jerraya A. A., Modélisation des interfaces matériel/logiciel, 1ère Ecole d’hiver francophone sur les systèmes hétérogènes, Villard-de-Lans, FRANCE, 2007
 
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32 Rapports

 1 Bouchhima A., Youssef W., Pétrot F., Kriaa L., Gerin P., Jerraya A. A., A Unified HW/SW Interface Refinement Approach for MPSoC Design, ISRN: TIMA-RR--06/06-01--FR, 1 janvier 2006
 
 2 Gerin P., Shen H., Chureau A., Bouchhima A., Jerraya A. A., Flexible and Executable Hardware/Software Interface Modeling for Multiprocessor SoC Design Using SystemC, ISRN: TIMA-RR--06/11-01--FR, 1 janvier 2006
 
 3 Jerraya A. A., Pétrot F., Bouchhima A., Programming models and HW-SW Interfaces Abstraction for Multi-Processor SoC, ISRN: TIMA-RR--06/06-02--FR, 1 janvier 2006
 
 4 Rousseau F., Grasset A., Jerraya A. A., Automatic Generation of Component Wrappers from Communication Service Specification, ISRN: TIMA-RR--05/03-07--FR, 1 janvier 2005
 
 5 Sasongko A., Rousseau F., Jerraya A. A., Shortening SoC Design Time with New Prototyping Flow on Reconfigurable Platform, ISRN: TIMA-RR--05/05-01--FR, 1 janvier 2005
 
 6 Yoo S., Paviot Y., Youssef W., Sasongko A., Jerraya A. A., Debugging HW/SW Interface for MPSoC: Video Encoder System Design Case Study, ISRN: TIMA-RR--04/05-01--FR, 1 janvier 2004
 
 7 Jerraya A. A., Long Term Trends for Embedded System Design, ISRN: TIMA-RR--04/09-02--FR, 1 janvier 2004
 
 8 François S., Hunsinger F., Jerraya A. A., Definition of a systematic method for the generation of software test programs allowing the functional verification of System On Chip (SoC), ISRN: TIMA-RR--03/08-07--FR, 1 janvier 2003
 
 9 Jerraya A. A., Cesario W., Lyonnard D., Paviot Y., Baghdadi A., Gauthier L., Nicolescu B., Yoo S., Application-Specific Multiprocessor Systems-on-Chip, ISRN: TIMA-RR--02/11-03--FR, 1 janvier 2002
 
10 Meftali S., Jerraya A. A., Gharsalli F., Rousseau F., Automatic Generation of Embedded Memory Wrapper for Multiprocessor Soc, ISRN: TIMA-RR--02/03-2--FR, 1 janvier 2002
 
11 Samet F., Cesario W., Dziri A., Wagner F.R., Jerraya A. A., Combining architecture exploration and a path to implementation to build a complete SoC design flow from system specification to RTL, ISRN: TIMA-RR--02/11-01--FR, 1 janvier 2002
 
12 Kriaa L., Nuta Nicolescu E.G., Levitan S.P., Kurzweg T., Courtois B., Youssef W., Martinez S., Martinez J., Jerraya A. A., SystemC-Based Cosimulation for Global Validation of MOEMS, ISRN: TIMA--RR-02/01-1--FR, 1 janvier 2002
 
13 Rousseau F., Meftali S., Gharsalli F., Jerraya A. A., Unifying Memory and Processor Wrapper Architecture in Multiprocessor SoC Design, ISRN: TIMA--RR-02/04-03--FR, 1 janvier 2002
 
14 Nuta Nicolescu E.G., Martinez S., Kriaa L., Youssef W., Yoo S., Charlot B., Jerraya A. A., Application of Multi-domain and Multi-language Cosimulation to an Optical MEM Switch Design, ISRN: TIMA-RR--01/09-1--FR, 1 janvier 2001
 
15 Meftali S., Rousseau F., Gharsalli F., Jerraya A. A., Automatic Code-Transformation and Architecture Refinement for Application-Specific Multiprocessor SoCs with Shared Memory, ISRN: TIMA--RR-01/12-2--FR, 1 janvier 2001
 
16 Lyonnard D., Yoo S., Baghdadi A., Jerraya A. A., Automatic Generation of Application-Specific Architectures for Heterogeneous Multiprocessor System-on-Chip, ISRN: TIMA-RR--01/02-03--FR, 1 janvier 2001
 
17 Yoo S., Gauthier L., Nuta Nicolescu E.G., Jerraya A. A., Automatic Generation of Fast Timed Simulation Models for Operating Systems in Multiprocessor SoC Design, ISRN: TIMA--RR-01/11-2--FR, 1 janvier 2001
 
18 Martinez S., Nuta Nicolescu E.G., Kriaa L., Youssef W., Yoo S., Jerraya A. A., Courtois B., Conception de systèmes hétérogènes contenant des microsystèmes optiques , ISRN: TIMA--RR-01/11-1--FR, 1 janvier 2001
 
19 Torki K., Nuta Nicolescu E.G., Juneidi Z., Martinez S., Courtois B., Global Modeling and Simulation of System-on-Chip embedding MEMS devices, ISRN: TIMA-RR--01/10-1--FR, 1 janvier 2001
 
20 Hessel F., Coste P., Nuta Nicolescu E.G., Le Marrec Ph., Zergainoh N.-E., Jerraya A. A., Communication Synthesis of Multilanguage Specification, ISRN: TIMA-RR--00/06-1--FR, 1 janvier 2000
 
21 Gauthier L., Jerraya A. A., Cycle­true simulation of the ST10 microcontroller (core and peripherals), ISRN: TIMA-RR--00/02/1--FR, 1 janvier 2000
 
22 Baghdadi A., Zergainoh N.-E., Cesario W., Roudier T., Jerraya A. A., Design Space Exploration for Hardware/Software Codesign of Multiprocessor ArchitecturesMultiprocessor Architectures, ISRN: TIMA-RR--00/02-4--FR, 1 janvier 2000
 
23 Coste P., Hessel F., Jerraya A. A., Multilanguage Codesign Using SDL and Matlab, ISRN: TIMA-RR--00/02-3--FR, 1 janvier 2000
 
24 Nuta Nicolescu E.G., Coste P., Hessel F., Le Marrec Ph., Jerraya A. A., Multilanguage Design of a Robot Arm Controller: Case Study, ISRN: TIMA-RR--00/02-2--FR, 1 janvier 2000
 
25 Mir S., Charlot B., Nuta Nicolescu E.G., Coste P., Parrain F., Zergainoh N.-E., Courtois B., Jerraya A. A., Rencz M., Towards Design And Validation Of Mixed-Technology SOCs, ISRN: TIMA-RR--00/01-1--FR, 1 janvier 2000
 
26 Moussa I., Sugar Z., Suescun R., Bianchi R.A., Pavesi M., Gazzi L., Crudo S., Jerraya A. A., Comparing RTL and Behavioral Design Methodologies in the Case of a 2M Transistors ATM Shaper, ISRN: TIMA-RR--99/04-3--FR, 1 janvier 1999
 
27 Baghdadi A., Cesario W., Teruya M.Y., Roudier T., Zergainoh N.-E., Jerraya A. A., Estimation de performance au niveau système : une ouverture à l'exploration pour le codesign, ISRN: TIMA-RR--99-07-2--FR, 1 janvier 1999
 
28 Guillaume Ph., Boulanger B., Santana M., Cornero M., Paulin P., Exploitation au niveau des ressources d'adressage machine dans le cadre d'applications embarquées, ISRN: TIMA--RR-99/04-8--FR, 1 janvier 1999
 
29 Hessel F., Sugar Z., Suescun R., Zergainoh N.-E., Coste P., Le Marrec Ph., Romdhani M., Jerraya A. A., Multilanguage systems codesign, ISRN: TIMA-RR--99/01-2--FR, 1 janvier 1999
 
30 Jerraya A. A., Romdhani M., Le Marrec Ph., Hessel F., Coste P., Valderrama C., Marchioro G.F., Daveau J.- M., Zergainoh N.-E., Multilanguage specification for system design and codesign, ISRN: TIMA-RR--98/12-1--FR, 1 janvier 1998
 
31 Guillaume Ph., AMICAL extension for handling post synthesis analysis and energy estimation: averview of SYNRJ concepts, ISRN: TIMA-RR--97/05-1--FR, 1 janvier 1997
 
32 Guillaume Ph., Jerraya A. A., Caractérisation de la consommation associée à la synthèse architecturale : une méthodologie, ISRN: TIMA-RR--97/01-1--FR, 1 janvier 1997
 
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94 Thèses

 1 Fernandez-Mesa B.J., Exploration des approches de synchronisation directes pour la simulation unifiée et de haut niveau des systèmes continus/discrets, These de Doctorat, 14 octobre 2021
 
 2 Trevisan Jost T., Compilation and optimizations for variable precision floating-Point arithmetic: from language and libraries to code generation, These de Doctorat, 2 juillet 2021
 
 3 Baumela T., Externalisation of device drivers from embedded processors to devices, These de Doctorat, 24 février 2021
 
 4 Christodoulis G., Adapting a HPC runtime system to FPGAs, These de Doctorat, 5 décembre 2019
 
 5 Chabot M., Requirement Driven automated tests for Cyber-physical Systems, These de Doctorat, 30 octobre 2018
 
 6 Faravelon A., Acceleration of memory accesses in dynamic binary translation, These de Doctorat, 20 octobre 2018
 
 7 Wicaksana A., Portable infrastructure for heterogeneous reconfigurable devices in a cloud-FPGA environment, These de Doctorat, 2 octobre 2018
 
 8 France-Pillois M., Hardware support for inter-process communication in multiprocessor system, These de Doctorat, 27 septembre 2018
 
 9 Hadj Salem K., Optimization of the operation of a generator of memory hierarchies for embedded vision systems, These de Doctorat, 26 avril 2018
 
10 Njoyah Ntafam P., New performance evaluation methods for early and refined software development on SoC platforms, These de Doctorat, 20 avril 2018
 
11 Dumas J., Dynamic sharing set for scalable cache coherence protocols, These de Doctorat, 13 décembre 2017
 
12 Matoussi O., Native Simulation of MPSoC: Instrumentation and Modeling of NonFunctional Aspects, These de Doctorat, 30 novembre 2017
 
13 Bernard M., Modular processing system for emission tomography with CdZnTe detector, These de Doctorat, 6 novembre 2017
 
14 Bel Hadj Amor H., Memory hierarchy in embedded multiprocessor system built around networks on chip, These de Doctorat, 5 octobre 2017
 
15 Bourge A., Hardware task context switch on FPGA between heterogeneous reconfigurable devices in a cloud-FPGA environment, These de Doctorat, 23 novembre 2016
 
16 Payet M., Design of programmable systems based on NoC with High Level Synthesys: Symbolic analysis and distributed control, These de Doctorat, 26 octobre 2016
 
17 Sarrazin G., Functionnal native simulation for many-core systems, These de Doctorat, 23 mai 2016
 
18 Schwambach V., Methods and Tools for Rapid and Efficient Parallel Implementation of Computer Vision Algorithms on Embedded Multiprocessors, These de Doctorat, 30 mars 2016
 
19 Cunha M., Defining and using virtual platforms traces captured for debugging MPSoCs, These de Doctorat, 29 janvier 2016
 
20 El-Antably A., Study of task migration in a multi-tiled architecture - Automatic generation of an agent-based solution, These de Doctorat, 16 décembre 2015
 
21 Alcantara O., Synthesis of NoC emulation platforms for embedded systems: toward the next-generation of NoCs (manuscript available at the University of Saint-Etienne), These de Doctorat, 9 septembre 2015
 
22 Saade J., Programmable Low Overhead, Run Length Limited and DC-Balanced Line Coding for High-Speed Serial Data Transmission, These de Doctorat, 3 juin 2015
 
23 Michel L., Contributions to Dynamic Binary Translation: instruction parallelism support and optimized translators generator, These de Doctorat, 18 décembre 2014
 
24 Lagraa S., New MPSoC profiling tools based on data mining techniques, These de Doctorat, 13 juin 2014
 
25 Xu Yan, Lightweight Software Services for Dynamic Partial Reconfiguration of FPGAs, These de Doctorat, 13 mars 2014
 
26 Prost-Boucle A., Fast hardware accelerator generation using high-level synthesis under resource constraints, These de Doctorat, 8 janvier 2014
 
27 Bahmani M., Architectural exploration and performance analysis of Vertically-Partially-Connected Mesh-based 3D-NoC, These de Doctorat, 9 décembre 2013
 
28 Dubois F., A machine-learning based methodology to design analytical area and power models of highly parametric networks-on-chip, These de Doctorat, 4 juillet 2013
 
29 Hamayun M.M., Native Simulation of Multi-Processor System-on-Chip using Hardware-Assisted Virtualization, These de Doctorat, 4 juillet 2013
 
30 Hedde D., Analyse de la consistance mémoire dans les MPSoCs à l'aide du prototypage virtuel, These de Doctorat, 12 juin 2013
 
31 Mancini S., Gestion des données dans les systèmes numériques intégrés, HDR, 19 février 2013
 
32 Tan J., Exploration of a generic architecture on FPGA for the algorithms of the multispectral imaging , These de Doctorat, 12 juin 2012
 
33 Horrein P.H., Software design for flexible radio: integration of heterogeneous computing units, These de Doctorat, 10 janvier 2012
 
34 Hassan K., Customizable Memory Controller Architecture and Service Continuity for Off-Chip SDRAM Access in NoC-Based MPSoCs, These de Doctorat, 2 septembre 2011
 
35 El Mrabti A., Methods and tools for code generation for multi-core platforms based on high-level description of applications and architectures, These de Doctorat, 8 décembre 2010
 
36 Rahmouni K., Définition d'un flot de conception basé sur la simulation conjointe du matériel et du logiciel pour des systèmes destinés à la protection des réseaux électriques, These de Doctorat, 7 décembre 2010
 
37 Chagoya-Garzon A., Communication synthesis in a binary code generation flow targeting heterogeneous multi-tile architectures, These de Doctorat, 3 décembre 2010
 
38 Meunier Q., Study of two solutions for parallel programming support in integrated multiprocessors: work-stealing and transactional memories , These de Doctorat, 29 octobre 2010
 
39 Gligor M., Fast Simulation Strategies and Adaptive DVFS Algorithm for Low Power MPSoCs, These de Doctorat, 9 septembre 2010
 
40 Guérin X., An efficient embedded software development approach for multiprocessor system-on-chips, These de Doctorat, 12 mai 2010
 
41 Gerin P., Simulation models for software validation and architecture exploration of Multi-Processors System On Chip, These de Doctorat, 30 novembre 2009
 
42 Guironnet de Massas P., Study of methods and mechanisms for software-seamless data accesses in a multiprocessor system-on-chip, These de Doctorat, 12 novembre 2009
 
43 Kouadri Mostéfaoui A., Flexible Architectures for Networks-On-Chip Validation and Exploration, These de Doctorat, 24 août 2009
 
44 Shen H., Contribution to a modeling approach and an exploration flow targeted to heterogeneous MPSoC architectures based on configurable processors, These de Doctorat, 11 mars 2009
 
45 Sahnine C., Reconfigurable, high throughput and low power VLSI architecture for advanced OFDM digital processing, These de Doctorat, 30 janvier 2009
 
46 Senouci B., Fast MPSoC prototyping methodology on reconfigurable hardware platforms , These de Doctorat, 28 novembre 2008
 
47 Chureau A., Definition of a Service-Based Intermediate Representation for Virtual Prototyping of Systems-on-Chip, These de Doctorat, 12 novembre 2008
 
48 Popovici K.M., Multilevel programming environment for heterogeneous MPSOC architectures, These de Doctorat, 25 mars 2008
 
49 Oyamada M., Software performance estimation in MPSoC design, These de Doctorat, 5 décembre 2007
 
50 Atat Y., Simulink-based MPSoC Design: Bridge between Algorithm and Architecture Design, These de Doctorat, 21 mai 2007
 
51 Fiandino M., Definition of a new method in order to implement a network of thousand heterogenous processors on a chip, These de Doctorat, 2 mai 2007
 
52 Blampey A., Interoperability between hardware emulators and hardware prototyping platforms , These de Doctorat, 6 décembre 2006
 
53 Lemaire R., Design and modelling of a control system for telecommunication applications with a Network-on-Chip (NoC) architecture, These de Doctorat, 11 octobre 2006
 
54 Pieralisi L., Modeling flexible Networks On-Chip, These de Doctorat, 7 juillet 2006
 
55 Bonaciu M., Flexible and Scalable Algorithm/Architecture Platform for MP-SoC Design of High Definition Video Compression Algorithms, These de Doctorat, 4 juillet 2006
 
56 Bacivarov I., Performance evaluation for heterogeneous MPSoC design, These de Doctorat, 28 juin 2006
 
57 Bouchhima A., Embedded software modeling at different abstraction levels for validation and synthesis of system-on-chips, These de Doctorat, 6 mai 2006
 
58 Youssef W., Hardware/Software interfaces study in the scope of multiprocessor system-on-chip and parallel programming models, These de Doctorat, 10 mars 2006
 
59 Hunsinger F., Global validation method for system on chip, These de Doctorat, 6 mars 2006
 
60 Petkov I., Design of multiprocessor system on chip: link between simulation and realization, These de Doctorat, 30 janvier 2006
 
61 Kriaa L., Modeling and validation of heterogeneous system : execution model definition, These de Doctorat, 10 novembre 2005
 
62 De Moraes Sarmento A., Automatic Generation of Simulation Models for the validation of heterogeneous systems-on-chip, These de Doctorat, 28 octobre 2005
 
63 Rousseau F., Hardware/Software system design : from Hardware/Software partitioning to prototyping onto reconfigurable platforms, HDR, 8 juillet 2005
 
64 Grasset A., Network interface synthesis for system-on-chip: from specification to automatic generation, These de Doctorat, 4 janvier 2005
 
65 Sasongko A., Prototyping based on reconfigurable platform for verification of system-on-chip, These de Doctorat, 15 octobre 2004
 
66 Paviot Y., Communication services partitioning for automatic generation of hardware software interfaces , These de Doctorat, 1 juillet 2004
 
67 Dziri A., Design tools and hardware/software components integration models for heterogeneous embedded systems design, These de Doctorat, 26 mai 2004
 
68 Tambour L., A Methodology and Semi-Automated Flow for Design and Validation of Digital Signal Processing ASIC Macro-cells, These de Doctorat, 3 décembre 2003
 
69 Gharsalli F., Hardware-Software Interface Design for Global Memory Intégration in System on Chip, These de Doctorat, 1 juillet 2003
 
70 Lyonnard D., An approach for the systematic gathering of interface items toward the generation of multiprocessor architectures, These de Doctorat, 30 avril 2003
 
71 Nuta Nicolescu E.G., Specification and validation for heterogeneous embedded systems, These de Doctorat, 27 novembre 2002
 
72 Meftali S., Architectures exploration and memory allocation/assignment in multiprocessor SoC, These de Doctorat, 6 septembre 2002
 
73 Baghdadi A., Exploration and Systematic Design of Application-Specific Heterogeneous Multiprocessor SoC, These de Doctorat, 14 mai 2002
 
74 Gauthier L., OS generation for multitask software targeting on heterogeneous multiprocessor architectures for specific embedded systems., These de Doctorat, 5 décembre 2001
 
75 Coste P., Heterogeneous System Design, These de Doctorat, 12 janvier 2001
 
76 Le Marrec Ph., Multilevel co-simulation in a multilanguage design flow, These de Doctorat, 28 juin 2000
 
77 Hessel F., Multilanguage Codesign of Heterogeneous Systems, These de Doctorat, 16 juin 2000
 
78 Sugar Z., Behavioral Synthesis Based on Scheduling, These de Doctorat, 15 mai 2000
 
79 Cesario W., Flexible architectural synthesis, These de Doctorat, 14 octobre 1999
 
80 Laurent B., Design of reuse blocks - reflections on methodology, These de Doctorat, 18 juin 1999
 
81 Guillaume Ph., Contribution to the back-end of system on a chip synthesis, These de Doctorat, 11 juin 1999
 
82 Marchioro G.F., Transformational partitioning for the co-design of mixed hardware/software systems, These de Doctorat, 26 novembre 1998
 
83 Valderrama C., Virtual prototyping for the generation of mixed hardware/software architecture, These de Doctorat, 29 octobre 1998
 
84 Nacabal F., Tools for exploration of embedded programmable architectures in industrial applications, These de Doctorat, 27 février 1998
 
85 Daveau J.- M., System level specification and communication synthesis for hardware/software co-design, These de Doctorat, 19 décembre 1997
 
86 Berrebi E., Methodology for the industrial application of architectural, These de Doctorat, 11 décembre 1997
 
87 Liem Cl. B., Retargetable compilers and tools for embedded processors in industrial applications, These de Doctorat, 18 juillet 1997
 
88 Rahmouni M., Scheduling and optimizations for high-level synthesis of control designs, These de Doctorat, 21 février 1997
 
89 Romdhani M., Embedded systems engineering using a hardware/software co-design methodology. Application on avionics, These de Doctorat, 9 décembre 1996
 
90 P. Vijayaraghavan V., Exploration of links between the High Level Synthesis (HLS) and the Register Transfer Level (RTL) synthesis, These de Doctorat, 29 novembre 1996
 
91 Ding Hong, Synthèse architecturale interactive et flexible, These de Doctorat, 2 avril 1996
 
92 Kission P., High level synthesis involving hierarchy and the re-use of existing blocks, These de Doctorat, 25 janvier 1996
 
93 Ben Ismail T., System-level synthesis and hardware/software codesign, These de Doctorat, 9 janvier 1996
 
94 Aichouchi M., Linking architectural synthesis with register transfer level synthesis, These de Doctorat, 20 juin 1994
 
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