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Definition of a systematic method for the generation of software test programs allowing the functional verification of System On Chip (SoC)

Auteur(s) : S. François, F. Hunsinger, A. A. Jerraya

ISRN: TIMA-RR--03/08-07--FR

In this paper, we present a novel approach for hardware functional verification of system on chip (SoC). Our ap-proach is based on the use of on chip programmable proc-essors like CPUs or DSPs to generate test programs for hardware parts of the design. Traditionally test programs are written at a low level using specific functions for hard-ware accesses. This method is time consuming and error prone as tests are hand written. In this paper we introduce a method allowing the use of high level software test pro-grams. The link between hardware and software is achieved by using a custom operating system. This paper also focuses on the benefits that are obtained by handling high level test programs.