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On-Line Testable Design: Application to Decimation Filter for AMS Systems

Auteur(s) : M. A. Naal, S. Mir, E. Simeu

ISRN: TIMA-RR--03/08-01--FR

This paper presents an implementation of on-line testing techniques for the case of a decimation filter. The decimation filter is used in a ƒÃƒ´ƒnAnalogue-to-Digital converter that is in turn used in a Built-In-Self-Test (BIST) circuitry for mixed-signal core testing. Thus, the filter itself must be self-testable. Three different one-line self-test techniques are studied and compared for a 0.18ƒÝm CMOS technology. The first one uses a non-concurrent structural test technique and the others are both based on semi-concurrent test methodologies. In all cases, the on-line test circuitry is automatically synthesized and exploits the idle time of the functional units to apply either a structural or a functional test