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AMICAL extension for handling post synthesis analysis and energy estimation: averview of SYNRJ concepts

Auteur(s) : Ph. Guillaume

ISRN: TIMA-RR--97/05-1--FR

The circuit consumption is a major concern today in the design community, because of the growing integration density associated to a dramatic improve in performance of today processors and digital consumer application. As a result, there is a need in defining some so called Low-Power methodologies. This is particularly true at the highest design abstraction levels, i.e. system or behavioral. These levels are the most promising in term of optimization efficiency. This document contributes to this aim in trying to define a general consumption estimation model. It will allow to characterize behavioral synthesis and then orient it towards Low-Powered solutions. This model is suitable not only for DSP-like devices, on which a lot of works have already focused, but also for control-dominated systems which present data-dependent behavior. in order to deal with such systems, statistical data are extracted from VHDL behavioral description simulations. Translating a typical system behavior, these data are then exploited to estimate the corresponding circuit consumption at the RT Level. This document synthesizes the main concepts employed in order to provides consumption estimation for HLS, and introduces the implementation solutions in a tool called SYNRJ